Merge branch 'master' of git://git.denx.de/u-boot-arm
This commit is contained in:
Tom Rini
commit
b5c068f3f8
arch/arm
board
barco/titanium
freescale
friendlyarm/mini2440
mx1ads
wandboard
doc
include/configs
spl
@ -109,5 +109,5 @@ endif
|
||||
ifdef CONFIG_ARM64
|
||||
OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
|
||||
else
|
||||
OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rel.dyn
|
||||
OBJCFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
|
||||
endif
|
||||
|
||||
7
arch/arm/cpu/armv7/exynos/config.mk
Normal file
7
arch/arm/cpu/armv7/exynos/config.mk
Normal file
@ -0,0 +1,7 @@
|
||||
#
|
||||
# Copyright (C) Albert ARIBAUD <albert.u.boot@aribaud.net>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
SPL_OBJCFLAGS += -j .machine_param
|
||||
@ -24,7 +24,7 @@ ENTRY(lowlevel_init)
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
ldr r9, =gdata
|
||||
#else
|
||||
sub sp, #GD_SIZE
|
||||
sub sp, sp, #GD_SIZE
|
||||
bic sp, sp, #7
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||||
mov r9, sp
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||||
#endif
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||||
@ -5,6 +5,7 @@
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||||
*/
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||||
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||||
#include <common.h>
|
||||
#include <div64.h>
|
||||
#include <asm/io.h>
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||||
#include <asm/errno.h>
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||||
#include <asm/arch/imx-regs.h>
|
||||
@ -123,7 +124,7 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
|
||||
return 0;
|
||||
}
|
||||
|
||||
return (freq * 18) / ((div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
|
||||
return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
|
||||
ANATOP_PFD_FRAC_SHIFT(pfd_num));
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||||
}
|
||||
|
||||
|
||||
@ -92,8 +92,6 @@ SECTIONS
|
||||
}
|
||||
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||||
.dynsym _end : { *(.dynsym) }
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||||
.hash : { *(.hash) }
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||||
.got.plt : { *(.got.plt) }
|
||||
.dynbss : { *(.dynbss) }
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||||
.dynstr : { *(.dynstr*) }
|
||||
.dynamic : { *(.dynamic*) }
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||||
@ -101,4 +99,5 @@ SECTIONS
|
||||
.interp : { *(.interp*) }
|
||||
.gnu : { *(.gnu*) }
|
||||
.ARM.exidx : { *(.ARM.exidx*) }
|
||||
.gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
|
||||
}
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||||
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||||
@ -67,7 +67,7 @@ ENTRY(_main)
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||||
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
|
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#endif
|
||||
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
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||||
sub sp, #GD_SIZE /* allocate one GD above SP */
|
||||
sub sp, sp, #GD_SIZE /* allocate one GD above SP */
|
||||
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
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||||
mov r9, sp /* GD is above SP */
|
||||
mov r0, #0
|
||||
|
||||
@ -264,15 +264,9 @@ int board_phy_config(struct phy_device *phydev)
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
setup_iomux_enet();
|
||||
|
||||
ret = cpu_eth_init(bis);
|
||||
if (ret)
|
||||
printf("FEC MXC: %s:failed\n", __func__);
|
||||
|
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return ret;
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
|
||||
@ -186,13 +186,10 @@ int fecmxc_mii_postcall(int phy)
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
struct eth_device *dev;
|
||||
int ret;
|
||||
int ret = cpu_eth_init(bis);
|
||||
|
||||
ret = cpu_eth_init(bis);
|
||||
if (ret) {
|
||||
printf("FEC MXC: %s:failed\n", __func__);
|
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if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev = eth_get_dev_by_name("FEC");
|
||||
if (!dev) {
|
||||
|
||||
@ -192,15 +192,9 @@ int board_phy_config(struct phy_device *phydev)
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
setup_iomux_enet();
|
||||
|
||||
ret = cpu_eth_init(bis);
|
||||
if (ret)
|
||||
printf("FEC MXC: %s:failed\n", __func__);
|
||||
|
||||
return ret;
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
#define BOARD_REV_B 0x200
|
||||
|
||||
@ -453,15 +453,9 @@ int overwrite_console(void)
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
setup_iomux_enet();
|
||||
|
||||
ret = cpu_eth_init(bis);
|
||||
if (ret)
|
||||
printf("FEC MXC: %s:failed\n", __func__);
|
||||
|
||||
return ret;
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
|
||||
@ -106,17 +106,9 @@ int board_mmc_init(bd_t *bis)
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
setup_iomux_fec();
|
||||
|
||||
ret = cpu_eth_init(bis);
|
||||
if (ret) {
|
||||
printf("FEC MXC: %s:failed\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
static int setup_fec(void)
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||||
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@ -1,8 +0,0 @@
|
||||
#
|
||||
# (C) Copyright 2012
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := mini2440.o
|
||||
@ -1,118 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
|
||||
*
|
||||
* (C) Copyright 2009
|
||||
* Michel Pollet <buserror@gmail.com>
|
||||
*
|
||||
* (C) Copyright 2012
|
||||
* Gabriel Huau <contact@huau-gabriel.fr>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/s3c2440.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <netdev.h>
|
||||
#include "mini2440.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static inline void pll_delay(unsigned long loops)
|
||||
{
|
||||
__asm__ volatile ("1:\n"
|
||||
"subs %0, %1, #1\n"
|
||||
"bne 1b" : "=r" (loops) : "0" (loops));
|
||||
}
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||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
struct s3c24x0_clock_power * const clk_power =
|
||||
s3c24x0_get_base_clock_power();
|
||||
|
||||
/* to reduce PLL lock time, adjust the LOCKTIME register */
|
||||
clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
|
||||
clk_power->clkdivn = CLKDIVN_VAL;
|
||||
|
||||
/* configure UPLL */
|
||||
clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
|
||||
/* some delay between MPLL and UPLL */
|
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pll_delay(100);
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||||
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||||
/* configure MPLL */
|
||||
clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
|
||||
|
||||
/* some delay between MPLL and UPLL */
|
||||
pll_delay(10000);
|
||||
|
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return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations
|
||||
*/
|
||||
int board_init(void)
|
||||
{
|
||||
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
|
||||
|
||||
/* IOMUX Port H : UART Configuration */
|
||||
gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
|
||||
IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
|
||||
|
||||
gpio_direction_output(GPH8, 0);
|
||||
gpio_direction_output(GPH9, 0);
|
||||
gpio_direction_output(GPH10, 0);
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
|
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|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
|
||||
|
||||
/*
|
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* Configuring bus width and timing
|
||||
* Initialize clocks for each bank 0..5
|
||||
* Bank 3 and 4 are used for DM9000
|
||||
*/
|
||||
writel(BANK_CONF, &memctl->bwscon);
|
||||
writel(B0_CONF, &memctl->bankcon[0]);
|
||||
writel(B1_CONF, &memctl->bankcon[1]);
|
||||
writel(B2_CONF, &memctl->bankcon[2]);
|
||||
writel(B3_CONF, &memctl->bankcon[3]);
|
||||
writel(B4_CONF, &memctl->bankcon[4]);
|
||||
writel(B5_CONF, &memctl->bankcon[5]);
|
||||
|
||||
/* Bank 6 and 7 are used for DRAM */
|
||||
writel(SDRAM_64MB, &memctl->bankcon[6]);
|
||||
writel(SDRAM_64MB, &memctl->bankcon[7]);
|
||||
|
||||
writel(MEM_TIMING, &memctl->refresh);
|
||||
writel(BANKSIZE_CONF, &memctl->banksize);
|
||||
writel(B6_MRSR, &memctl->mrsrb6);
|
||||
writel(B7_MRSR, &memctl->mrsrb7);
|
||||
|
||||
gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
|
||||
PHYS_SDRAM_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_DRIVER_DM9000
|
||||
return dm9000_initialize(bis);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
@ -1,144 +0,0 @@
|
||||
#ifndef __MINI2440_BOARD_CONF_H__
|
||||
#define __MINI2440_BOARD_CONF_H__
|
||||
|
||||
/* PLL Parameters */
|
||||
#define CLKDIVN_VAL 7
|
||||
#define M_MDIV 0x7f
|
||||
#define M_PDIV 0x2
|
||||
#define M_SDIV 0x1
|
||||
|
||||
#define U_M_MDIV 0x38
|
||||
#define U_M_PDIV 0x2
|
||||
#define U_M_SDIV 0x2
|
||||
|
||||
/* BWSCON */
|
||||
#define DW8 0x0
|
||||
#define DW16 0x1
|
||||
#define DW32 0x2
|
||||
#define WAIT (0x1<<2)
|
||||
#define UBLB (0x1<<3)
|
||||
|
||||
#define B1_BWSCON (DW32)
|
||||
#define B2_BWSCON (DW16)
|
||||
#define B3_BWSCON (DW16 + WAIT + UBLB)
|
||||
#define B4_BWSCON (DW16 + WAIT + UBLB)
|
||||
#define B5_BWSCON (DW16)
|
||||
#define B6_BWSCON (DW32)
|
||||
#define B7_BWSCON (DW32)
|
||||
|
||||
/*
|
||||
* Bank Configuration
|
||||
*/
|
||||
#define B0_Tacs 0x0 /* 0clk */
|
||||
#define B0_Tcos 0x0 /* 0clk */
|
||||
#define B0_Tacc 0x7 /* 14clk */
|
||||
#define B0_Tcoh 0x0 /* 0clk */
|
||||
#define B0_Tah 0x0 /* 0clk */
|
||||
#define B0_Tacp 0x0 /* 0clk */
|
||||
#define B0_PMC 0x0 /* normal */
|
||||
|
||||
#define B1_Tacs 0x0
|
||||
#define B1_Tcos 0x0
|
||||
#define B1_Tacc 0x7
|
||||
#define B1_Tcoh 0x0
|
||||
#define B1_Tah 0x0
|
||||
#define B1_Tacp 0x0
|
||||
#define B1_PMC 0x0
|
||||
|
||||
#define B2_Tacs 0x0
|
||||
#define B2_Tcos 0x0
|
||||
#define B2_Tacc 0x7
|
||||
#define B2_Tcoh 0x0
|
||||
#define B2_Tah 0x0
|
||||
#define B2_Tacp 0x0
|
||||
#define B2_PMC 0x0
|
||||
|
||||
#define B3_Tacs 0x0
|
||||
#define B3_Tcos 0x3 /* 4clk */
|
||||
#define B3_Tacc 0x7
|
||||
#define B3_Tcoh 0x1 /* 1clk */
|
||||
#define B3_Tah 0x3 /* 4clk */
|
||||
#define B3_Tacp 0x0
|
||||
#define B3_PMC 0x0
|
||||
|
||||
#define B4_Tacs 0x0
|
||||
#define B4_Tcos 0x3
|
||||
#define B4_Tacc 0x7
|
||||
#define B4_Tcoh 0x1
|
||||
#define B4_Tah 0x3
|
||||
#define B4_Tacp 0x0
|
||||
#define B4_PMC 0x0
|
||||
|
||||
#define B5_Tacs 0x0
|
||||
#define B5_Tcos 0x0
|
||||
#define B5_Tacc 0x7
|
||||
#define B5_Tcoh 0x0
|
||||
#define B5_Tah 0x0
|
||||
#define B5_Tacp 0x0
|
||||
#define B5_PMC 0x0
|
||||
|
||||
/*
|
||||
* SDRAM Configuration
|
||||
*/
|
||||
#define SDRAM_MT 0x3 /* SDRAM */
|
||||
#define SDRAM_Trcd 0x0 /* 2clk */
|
||||
#define SDRAM_SCAN_9 0x1 /* 9bit */
|
||||
#define SDRAM_SCAN_10 0x2 /* 10bit */
|
||||
|
||||
#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
|
||||
|
||||
/*
|
||||
* Refresh Parameter
|
||||
*/
|
||||
#define REFEN 0x1 /* Refresh enable */
|
||||
#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
|
||||
#define Trp 0x1 /* 3clk */
|
||||
#define Trc 0x3 /* 7clk */
|
||||
#define Tchr 0x0 /* unused */
|
||||
#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
|
||||
|
||||
/*
|
||||
* MRSR Parameter
|
||||
*/
|
||||
#define BL 0x0
|
||||
#define BT 0x0
|
||||
#define CL 0x3 /* 3 clocks */
|
||||
#define TM 0x0
|
||||
#define WBL 0x0
|
||||
|
||||
/*
|
||||
* BankSize Parameter
|
||||
*/
|
||||
#define BK76MAP 0x2 /* 128MB/128MB */
|
||||
#define SCLK_EN 0x1 /* SCLK active */
|
||||
#define SCKE_EN 0x1 /* SDRAM power down mode enable */
|
||||
#define BURST_EN 0x1 /* Burst enable */
|
||||
|
||||
/*
|
||||
* Register values
|
||||
*/
|
||||
#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
|
||||
(B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
|
||||
(B7_BWSCON<<28)))
|
||||
|
||||
#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
|
||||
(B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
|
||||
#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
|
||||
(B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
|
||||
#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
|
||||
(B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
|
||||
#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
|
||||
(B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
|
||||
#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
|
||||
(B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
|
||||
#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
|
||||
(B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
|
||||
|
||||
#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
|
||||
(Trc<<18) + (Tchr<<16) + REFCNT
|
||||
|
||||
#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
|
||||
#define B6_MRSR (CL<<4)
|
||||
#define B7_MRSR (CL<<4)
|
||||
|
||||
#endif
|
||||
@ -1,16 +0,0 @@
|
||||
#
|
||||
# board/mx1ads/Makefile
|
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (c) Copyright 2004
|
||||
# Techware Information Technology, Inc.
|
||||
# http://www.techware.com.tw/
|
||||
#
|
||||
# Ming-Len Wu <minglen_wu@techware.com.tw>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
obj-y := mx1ads.o syncflash.o
|
||||
obj-y += lowlevel_init.o
|
||||
@ -1,68 +0,0 @@
|
||||
/*
|
||||
* board/mx1ads/lowlevel_init.S
|
||||
*
|
||||
* (c) Copyright 2004
|
||||
* Techware Information Technology, Inc.
|
||||
* http://www.techware.com.tw/
|
||||
*
|
||||
* Ming-Len Wu <minglen_wu@techware.com.tw>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
|
||||
#define SDCTL0 0x221000
|
||||
#define SDCTL1 0x221004
|
||||
|
||||
|
||||
_TEXT_BASE:
|
||||
.word CONFIG_SYS_TEXT_BASE
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
/* memory controller init */
|
||||
|
||||
ldr r1, =SDCTL0
|
||||
|
||||
/* Set Precharge Command */
|
||||
|
||||
ldr r3, =0x92120200
|
||||
/* ldr r3, =0x92120251
|
||||
*/
|
||||
str r3, [r1]
|
||||
|
||||
/* Issue Precharge All Commad */
|
||||
ldr r3, =0x8200000
|
||||
ldr r2, [r3]
|
||||
|
||||
/* Set AutoRefresh Command */
|
||||
ldr r3, =0xA2120200
|
||||
str r3, [r1]
|
||||
|
||||
/* Issue AutoRefresh Command */
|
||||
ldr r3, =0x8000000
|
||||
ldr r2, [r3]
|
||||
ldr r2, [r3]
|
||||
ldr r2, [r3]
|
||||
ldr r2, [r3]
|
||||
ldr r2, [r3]
|
||||
ldr r2, [r3]
|
||||
ldr r2, [r3]
|
||||
ldr r2, [r3]
|
||||
|
||||
/* Set Mode Register */
|
||||
ldr r3, =0xB2120200
|
||||
str r3, [r1]
|
||||
|
||||
/* Issue Mode Register Command */
|
||||
ldr r3, =0x08111800 /* Mode Register Value */
|
||||
ldr r2, [r3]
|
||||
|
||||
/* Set Normal Mode */
|
||||
ldr r3, =0x82124200
|
||||
str r3, [r1]
|
||||
|
||||
/* everything is fine now */
|
||||
mov pc, lr
|
||||
@ -1,178 +0,0 @@
|
||||
/*
|
||||
* board/mx1ads/mx1ads.c
|
||||
*
|
||||
* (c) Copyright 2004
|
||||
* Techware Information Technology, Inc.
|
||||
* http://www.techware.com.tw/
|
||||
*
|
||||
* Ming-Len Wu <minglen_wu@techware.com.tw>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
/*#include <mc9328.h>*/
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define FCLK_SPEED 1
|
||||
|
||||
#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
|
||||
#define M_MDIV 0xC3
|
||||
#define M_PDIV 0x4
|
||||
#define M_SDIV 0x1
|
||||
#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
|
||||
#define M_MDIV 0xA1
|
||||
#define M_PDIV 0x3
|
||||
#define M_SDIV 0x1
|
||||
#endif
|
||||
|
||||
#define USB_CLOCK 1
|
||||
|
||||
#if USB_CLOCK==0
|
||||
#define U_M_MDIV 0xA1
|
||||
#define U_M_PDIV 0x3
|
||||
#define U_M_SDIV 0x1
|
||||
#elif USB_CLOCK==1
|
||||
#define U_M_MDIV 0x48
|
||||
#define U_M_PDIV 0x3
|
||||
#define U_M_SDIV 0x2
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
|
||||
static inline void delay (unsigned long loops)
|
||||
{
|
||||
__asm__ volatile ("1:\n"
|
||||
"subs %0, %1, #1\n"
|
||||
"bne 1b":"=r" (loops):"0" (loops));
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
void SetAsynchMode (void)
|
||||
{
|
||||
__asm__ ("mrc p15,0,r0,c1,c0,0 \n"
|
||||
"mov r2, #0xC0000000 \n"
|
||||
"orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n");
|
||||
}
|
||||
|
||||
static u32 mc9328sid;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
mc9328sid = SIDR;
|
||||
|
||||
GPCR = 0x000003AB; /* I/O pad driving strength */
|
||||
|
||||
/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
|
||||
/* MX1_CS1L = 0x11110601; */
|
||||
|
||||
MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
|
||||
|
||||
/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
|
||||
* BCLK divider to 2 (i.e. BCLK to 48 MHz)
|
||||
*/
|
||||
CSCR = 0xAF000403;
|
||||
|
||||
CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
|
||||
CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
|
||||
|
||||
/* setup cs4 for cs8900 ethernet */
|
||||
|
||||
CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
|
||||
CS4L = 0x00001501;
|
||||
|
||||
GIUS (0) &= 0xFF3FFFFF;
|
||||
GPR (0) &= 0xFF3FFFFF;
|
||||
|
||||
readl(0x1500000C);
|
||||
readl(0x1500000C);
|
||||
|
||||
SetAsynchMode ();
|
||||
|
||||
icache_enable ();
|
||||
dcache_enable ();
|
||||
|
||||
/* set PERCLKs */
|
||||
PCDR = 0x00000055; /* set PERCLKS */
|
||||
|
||||
/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
|
||||
* PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
|
||||
* all sources selected as normal interrupt
|
||||
*/
|
||||
|
||||
/* MX1_INTTYPEH = 0;
|
||||
MX1_INTTYPEL = 0;
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
|
||||
|
||||
gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init (void)
|
||||
{
|
||||
|
||||
setenv ("stdout", "serial");
|
||||
setenv ("stderr", "serial");
|
||||
|
||||
switch (mc9328sid) {
|
||||
case 0x0005901d:
|
||||
printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",
|
||||
mc9328sid);
|
||||
break;
|
||||
case 0x04d4c01d:
|
||||
printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",
|
||||
mc9328sid);
|
||||
break;
|
||||
case 0x00d4c01d:
|
||||
printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",
|
||||
mc9328sid);
|
||||
break;
|
||||
|
||||
default:
|
||||
printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",
|
||||
mc9328sid);
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
|
||||
PHYS_SDRAM_1_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_NET
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = 0;
|
||||
#ifdef CONFIG_CS8900
|
||||
rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
|
||||
#endif
|
||||
return rc;
|
||||
}
|
||||
#endif
|
||||
@ -1,307 +0,0 @@
|
||||
/*
|
||||
* board/mx1ads/syncflash.c
|
||||
*
|
||||
* (c) Copyright 2004
|
||||
* Techware Information Technology, Inc.
|
||||
* http://www.techware.com.tw/
|
||||
*
|
||||
* Ming-Len Wu <minglen_wu@techware.com.tw>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
/*#include <mc9328.h>*/
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
typedef unsigned long * p_u32;
|
||||
|
||||
/* 4Mx16x2 IAM=0 CSD1 */
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/* Following Setting is for CSD1 */
|
||||
#define SFCTL 0x00221004
|
||||
#define reg_SFCTL __REG(SFCTL)
|
||||
|
||||
#define SYNCFLASH_A10 (0x00100000)
|
||||
|
||||
#define CMD_NORMAL (0x81020300) /* Normal Mode */
|
||||
#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
|
||||
#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
|
||||
#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
|
||||
#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
|
||||
#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
|
||||
|
||||
#define MODE_REG_VAL (CONFIG_SYS_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
|
||||
|
||||
/* LCR Command */
|
||||
#define LCR_READSTATUS (0x0001C000) /* 0x70 */
|
||||
#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
|
||||
#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
|
||||
#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
|
||||
#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
|
||||
|
||||
/* Get Status register */
|
||||
u32 SF_SR(void) {
|
||||
u32 tmp;
|
||||
|
||||
reg_SFCTL = CMD_PROGRAM;
|
||||
tmp = __REG(CONFIG_SYS_FLASH_BASE);
|
||||
|
||||
reg_SFCTL = CMD_NORMAL;
|
||||
|
||||
reg_SFCTL = CMD_LCR; /* Activate LCR Mode */
|
||||
__REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR);
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
/* check if SyncFlash is ready */
|
||||
u8 SF_Ready(void) {
|
||||
u32 tmp;
|
||||
|
||||
tmp = SF_SR();
|
||||
|
||||
if ((tmp & 0x00800000) && (tmp & 0x001C0000)) {
|
||||
printf ("SyncFlash Error code %08x\n",tmp);
|
||||
};
|
||||
|
||||
if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
|
||||
printf ("SyncFlash Error code %08x\n",tmp);
|
||||
};
|
||||
|
||||
if (tmp == 0x00800080) /* Test Bit 7 of SR */
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Issue the precharge all command */
|
||||
void SF_PrechargeAll(void) {
|
||||
|
||||
/* Set Precharge Command */
|
||||
reg_SFCTL = CMD_PREC;
|
||||
/* Issue Precharge All Command */
|
||||
__REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10);
|
||||
}
|
||||
|
||||
/* set SyncFlash to normal mode */
|
||||
void SF_Normal(void) {
|
||||
|
||||
SF_PrechargeAll();
|
||||
|
||||
reg_SFCTL = CMD_NORMAL;
|
||||
}
|
||||
|
||||
/* Erase SyncFlash */
|
||||
void SF_Erase(u32 RowAddress) {
|
||||
|
||||
reg_SFCTL = CMD_NORMAL;
|
||||
__REG(RowAddress);
|
||||
|
||||
reg_SFCTL = CMD_PREC;
|
||||
__REG(RowAddress);
|
||||
|
||||
reg_SFCTL = CMD_LCR; /* Set LCR mode */
|
||||
__REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */
|
||||
|
||||
reg_SFCTL = CMD_NORMAL; /* return to Normal mode */
|
||||
__REG(RowAddress) = 0xD0D0D0D0; /* Confirm */
|
||||
|
||||
while(!SF_Ready());
|
||||
}
|
||||
|
||||
void SF_NvmodeErase(void) {
|
||||
SF_PrechargeAll();
|
||||
|
||||
reg_SFCTL = CMD_LCR; /* Set to LCR mode */
|
||||
__REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */
|
||||
|
||||
reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
|
||||
__REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */
|
||||
|
||||
while(!SF_Ready());
|
||||
}
|
||||
|
||||
void SF_NvmodeWrite(void) {
|
||||
SF_PrechargeAll();
|
||||
|
||||
reg_SFCTL = CMD_LCR; /* Set to LCR mode */
|
||||
__REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */
|
||||
|
||||
reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
|
||||
__REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
|
||||
}
|
||||
|
||||
/****************************************************************************************/
|
||||
|
||||
ulong flash_init(void) {
|
||||
int i, j;
|
||||
|
||||
/* Turn on CSD1 for negating RESETSF of SyncFLash */
|
||||
|
||||
reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */
|
||||
udelay(200);
|
||||
|
||||
reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */
|
||||
__REG(MODE_REG_VAL); /* Issue Load Mode Register Command */
|
||||
|
||||
SF_Normal();
|
||||
|
||||
i = 0;
|
||||
|
||||
flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC;
|
||||
|
||||
flash_info[i].size = FLASH_BANK_SIZE;
|
||||
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
|
||||
|
||||
memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
|
||||
|
||||
for (j = 0; j < flash_info[i].sector_count; j++) {
|
||||
flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + j * 0x00100000;
|
||||
}
|
||||
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_SYS_FLASH_BASE,
|
||||
CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_ENV_ADDR,
|
||||
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
|
||||
return FLASH_BANK_SIZE;
|
||||
}
|
||||
|
||||
void flash_print_info (flash_info_t *info) {
|
||||
|
||||
int i;
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case (FLASH_MAN_MT & FLASH_VENDMASK):
|
||||
printf("Micron: ");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
|
||||
printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown Chip Type\n");
|
||||
return;
|
||||
break;
|
||||
}
|
||||
|
||||
printf(" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf(" Sector Start Addresses: ");
|
||||
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
|
||||
printf (" %08lX%s", info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last) {
|
||||
int iflag, cflag, prot, sect;
|
||||
int rc = ERR_OK;
|
||||
|
||||
/* first look for protection bits */
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN)
|
||||
return ERR_UNKNOWN_FLASH_TYPE;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last))
|
||||
return ERR_INVAL;
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
|
||||
return ERR_UNKNOWN_FLASH_VENDOR;
|
||||
|
||||
prot = 0;
|
||||
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect])
|
||||
prot++;
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf("protected!\n");
|
||||
return ERR_PROTECTED;
|
||||
}
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
|
||||
cflag = icache_status();
|
||||
icache_disable();
|
||||
iflag = disable_interrupts();
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
|
||||
|
||||
printf("Erasing sector %2d ... ", sect);
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
|
||||
get_timer(0);
|
||||
|
||||
SF_NvmodeErase();
|
||||
SF_NvmodeWrite();
|
||||
|
||||
SF_Erase(CONFIG_SYS_FLASH_BASE + (0x0100000 * sect));
|
||||
SF_Normal();
|
||||
|
||||
printf("ok.\n");
|
||||
}
|
||||
|
||||
if (ctrlc())
|
||||
printf("User Interrupt!\n");
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts();
|
||||
|
||||
if (cflag)
|
||||
icache_enable();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash.
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
|
||||
int i;
|
||||
|
||||
for(i = 0; i < cnt; i += 4) {
|
||||
|
||||
SF_PrechargeAll();
|
||||
|
||||
reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */
|
||||
__REG(addr + i) = __REG((u32)src + i);
|
||||
|
||||
while(!SF_Ready());
|
||||
}
|
||||
|
||||
SF_Normal();
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
@ -257,15 +257,9 @@ static void setup_display(void)
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
setup_iomux_enet();
|
||||
|
||||
ret = cpu_eth_init(bis);
|
||||
if (ret)
|
||||
printf("FEC MXC: %s:failed\n", __func__);
|
||||
|
||||
return ret;
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
|
||||
@ -65,11 +65,9 @@ Active arm arm920t at91 BuS eb_cpux9k2
|
||||
Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2_ram eb_cpux9k2:RAMBOOT Jens Scharsig <esw@bus-elektronik.de>
|
||||
Active arm arm920t at91 eukrea cpuat91 cpuat91 cpuat91 Eric Benard <eric@eukrea.com>
|
||||
Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard <eric@eukrea.com>
|
||||
Active arm arm920t imx - - mx1ads - -
|
||||
Active arm arm920t imx - - scb9328 - Torsten Koschorrek <koschorrek@synertronixx.de>
|
||||
Active arm arm920t ks8695 - - cm4008 - Greg Ungerer <greg.ungerer@opengear.com>
|
||||
Active arm arm920t ks8695 - - cm41xx - -
|
||||
Active arm arm920t s3c24x0 friendlyarm mini2440 mini2440 - Gabriel Huau <contact@huau-gabriel.fr>
|
||||
Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Müller <d.mueller@elsoft.ch>
|
||||
Active arm arm920t s3c24x0 samsung - smdk2410 - David Müller <d.mueller@elsoft.ch>
|
||||
Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
@ -1,28 +0,0 @@
|
||||
U-Boot for FriendlyARM Mini2440 (s3c2440)
|
||||
|
||||
This file contains information for the port of U-Boot to FriendlyARM
|
||||
mini2440
|
||||
|
||||
All information about the board can be found on :
|
||||
http://www.friendlyarm.net/products/mini2440
|
||||
|
||||
To build u-boot : ./MAKEALL mini2440
|
||||
|
||||
Overview :
|
||||
--------
|
||||
FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440
|
||||
ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9
|
||||
systems. It's a low cost board.
|
||||
|
||||
Boot Methods :
|
||||
------------
|
||||
Mini2440 can boot from NOR or NAND.
|
||||
|
||||
Build :
|
||||
-----
|
||||
./MAKEALL mini2440
|
||||
|
||||
or
|
||||
|
||||
make mini2440_config
|
||||
make
|
||||
@ -11,8 +11,10 @@ easily if here is something they might want to dig for...
|
||||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
omap730p2 arm arm926ejs - 2013-11-11
|
||||
pn62 powerpc mpc824x - 2013-11-11 Wolfgang Grandegger <wg@grandegger.com>
|
||||
mx1ads arm arm920t - 2014-01-13
|
||||
mini2440 arm arm920t - 2014-01-13 Gabriel Huau <contact@huau-gabriel.fr>
|
||||
omap730p2 arm arm926ejs 79c5c08d 2013-11-11
|
||||
pn62 powerpc mpc824x 649acfe1 2013-11-11 Wolfgang Grandegger <wg@grandegger.com>
|
||||
pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
|
||||
scpu arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
|
||||
omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta <kshitij@ti.com>
|
||||
|
||||
@ -1,163 +0,0 @@
|
||||
/*
|
||||
* include/configs/mx1ads.h
|
||||
*
|
||||
* (c) Copyright 2004
|
||||
* Techware Information Technology, Inc.
|
||||
* http://www.techware.com.tw/
|
||||
*
|
||||
* Ming-Len Wu <minglen_wu@techware.com.tw>
|
||||
*
|
||||
* This is the Configuration setting for Motorola MX1ADS board
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
|
||||
#define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */
|
||||
#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */
|
||||
|
||||
/*
|
||||
* Select serial console configuration
|
||||
*/
|
||||
#define CONFIG_IMX_SERIAL
|
||||
#define CONFIG_IMX_SERIAL1 /* internal uart 1 */
|
||||
/* #define _CONFIG_UART2 */ /* internal uart 2 */
|
||||
/* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */
|
||||
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
#define USE_920T_MMU 1
|
||||
|
||||
#if 0
|
||||
#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
|
||||
#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
|
||||
#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
|
||||
|
||||
/*
|
||||
* CS8900 Ethernet drivers
|
||||
*/
|
||||
#define CONFIG_CS8900 /* we have a CS8900 on-board */
|
||||
#define CONFIG_CS8900_BASE 0x15000300
|
||||
#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
|
||||
/* #define CONFIG_UART1 */
|
||||
/* #define CONFIG_UART2 1 */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_REGINFO
|
||||
#define CONFIG_CMD_ELF
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M"
|
||||
#define CONFIG_BOOTFILE "mx1ads"
|
||||
#define CONFIG_BOOTCOMMAND "tftp; bootm"
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER 1
|
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
|
||||
#ifdef CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT "MX1ADS$ " /* Monitor Command Prompt */
|
||||
#else
|
||||
#define CONFIG_SYS_PROMPT "MX1ADS=> " /* Monitor Command Prompt */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x09000000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x08800000 /* default load address */
|
||||
#define CONFIG_SYS_HZ 3686400
|
||||
#define CONFIG_SYS_CPUSPEED 0x141
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
|
||||
#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x10000000
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_GBL_DATA_OFFSET)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */
|
||||
#define CONFIG_SYS_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */
|
||||
#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
#define CONFIG_SYNCFLASH 1
|
||||
#define PHYS_FLASH_SIZE 0x01000000
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (16)
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x00ff8000)
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x100000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Enable passing ATAGS
|
||||
*/
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 16780000
|
||||
#define CONFIG_SYSPLL_CLK_FREQ 16000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@ -95,6 +95,28 @@
|
||||
#define CONFIG_LOADADDR 0x12000000
|
||||
#define CONFIG_SYS_TEXT_BASE 0x17800000
|
||||
|
||||
#ifdef CONFIG_SUPPORT_EMMC_BOOT
|
||||
#define EMMC_ENV \
|
||||
"emmcdev=2\0" \
|
||||
"update_emmc_firmware=" \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"if ${get_cmd} ${update_sd_firmware_filename}; then " \
|
||||
"if mmc dev ${emmcdev} && " \
|
||||
"mmc open ${emmcdev} 1; then " \
|
||||
"setexpr fw_sz ${filesize} / 0x200; " \
|
||||
"setexpr fw_sz ${fw_sz} + 1; " \
|
||||
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
|
||||
"mmc close ${emmcdev} 1; " \
|
||||
"fi; " \
|
||||
"fi\0"
|
||||
#else
|
||||
#define EMMC_ENV ""
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"uimage=uImage\0" \
|
||||
@ -121,6 +143,7 @@
|
||||
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
EMMC_ENV \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
|
||||
@ -23,6 +23,8 @@
|
||||
#endif
|
||||
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
||||
|
||||
#include "mx6sabre_common.h"
|
||||
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 3
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/sizes.h>
|
||||
#include "mx6_common.h"
|
||||
|
||||
#define CONFIG_MX6
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
|
||||
@ -108,7 +108,7 @@
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"uimage=uImage\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"splashpos=m,m\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
@ -140,22 +140,22 @@
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
@ -167,19 +167,19 @@
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${uimage}; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"bootz; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
@ -187,7 +187,7 @@
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
|
||||
@ -165,7 +165,7 @@ $(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin
|
||||
endif
|
||||
|
||||
$(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN)
|
||||
$(OBJCOPY) $(OBJCFLAGS) -O binary $< $@
|
||||
$(OBJCOPY) $(OBJCFLAGS) $(SPL_OBJCFLAGS) -O binary $< $@
|
||||
|
||||
GEN_UBOOT = \
|
||||
cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $(__START) \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user