arm:exynos4:trats: Correct SDRAM configuration for trats
SDRAM setup alike to ORIGEN Dev board. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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@ -189,12 +189,17 @@
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#define CONFIG_SYS_HZ 1000
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/* TRATS has 2 banks of DRAM */
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#define CONFIG_NR_DRAM_BANKS 2
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#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
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#define PHYS_SDRAM_1_SIZE (512 << 20) /* 512 MB in CS 0 */
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#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
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#define PHYS_SDRAM_2_SIZE (512 << 20) /* 512 MB in CS 0 */
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/* TRATS has 4 banks of DRAM */
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#define CONFIG_NR_DRAM_BANKS 4
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#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
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#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
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#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
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#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
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#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
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