ARM: imx: pico-imx8mq: Add support for Technexion Pico-iMX8MQ
Add initial support for Technexion Pico-iMX8MQ SoM on PicoPI carrier
board. Currently working is ethernet, serial, eMMC. DT is imported
from Linux 5.4.28 ("462afcd6e7ea") .
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Marek Vasut
Stefano Babic
parent
b77d0292ca
commit
b52fb0b0b5
@ -737,7 +737,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mn-ddr4-evk.dtb \
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imx8mq-evk.dtb \
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imx8mq-phanbell.dtb \
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imx8mp-evk.dtb
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imx8mp-evk.dtb \
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imx8mq-pico-pi.dtb
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dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
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imxrt1020-evk.dtb
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420
arch/arm/dts/imx8mq-pico-pi.dts
Normal file
420
arch/arm/dts/imx8mq-pico-pi.dts
Normal file
@ -0,0 +1,420 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 Wandboard, Org.
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* Copyright 2017 NXP
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*
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* Author: Richard Hu <hakahu@gmail.com>
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*/
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/dts-v1/;
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#include "imx8mq.dtsi"
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/ {
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model = "TechNexion PICO-PI-8M";
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compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq";
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chosen {
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stdout-path = &uart1;
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};
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pmic_osc: clock-pmic {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "pmic_osc";
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};
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reg_usb_otg_vbus: regulator-usb-otg-vbus {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_otg_vbus>;
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compatible = "regulator-fixed";
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio3 14 GPIO_ACTIVE_LOW>;
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};
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reg_eth_phy: eth_phy {
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compatible = "regulator-fixed";
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regulator-name = "eth_phy_pwr";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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phy-supply = <®_eth_phy>;
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phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <100>;
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phy-reset-post-delay = <100>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic: pmic@4b {
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reg = <0x4b>;
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compatible = "rohm,bd71837";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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clocks = <&pmic_osc>;
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clock-names = "osc";
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clock-output-names = "pmic_clk";
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interrupt-parent = <&gpio1>;
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interrupts = <3 GPIO_ACTIVE_LOW>;
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interrupt-names = "irq";
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regulators {
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buck1: BUCK1 {
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regulator-name = "buck1";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-ramp-delay = <1250>;
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rohm,dvs-run-voltage = <900000>;
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rohm,dvs-idle-voltage = <850000>;
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rohm,dvs-suspend-voltage = <800000>;
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};
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buck2: BUCK2 {
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regulator-name = "buck2";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-ramp-delay = <1250>;
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rohm,dvs-run-voltage = <1000000>;
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rohm,dvs-idle-voltage = <900000>;
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};
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buck3: BUCK3 {
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regulator-name = "buck3";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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rohm,dvs-run-voltage = <1000000>;
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};
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buck4: BUCK4 {
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regulator-name = "buck4";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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rohm,dvs-run-voltage = <1000000>;
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};
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buck5: BUCK5 {
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regulator-name = "buck5";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1350000>;
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regulator-boot-on;
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};
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buck6: BUCK6 {
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regulator-name = "buck6";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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buck7: BUCK7 {
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regulator-name = "buck7";
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regulator-min-microvolt = <1605000>;
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regulator-max-microvolt = <1995000>;
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regulator-boot-on;
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};
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buck8: BUCK8 {
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regulator-name = "buck8";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1400000>;
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regulator-boot-on;
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};
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ldo1: LDO1 {
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regulator-name = "ldo1";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo2: LDO2 {
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regulator-name = "ldo2";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo3: LDO3 {
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regulator-name = "ldo3";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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ldo4: LDO4 {
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regulator-name = "ldo4";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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};
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ldo5: LDO5 {
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regulator-name = "ldo5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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ldo6: LDO6 {
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regulator-name = "ldo6";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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};
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ldo7: LDO7 {
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regulator-name = "ldo7";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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};
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&uart1 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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bus-width = <4>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&usb3_phy0 {
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status = "okay";
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};
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&usb3_phy1 {
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status = "okay";
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};
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&usb_dwc3_1 {
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dr_mode = "host";
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
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MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
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MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
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>;
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};
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pinctrl_otg_vbus: otgvbusgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */
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>;
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};
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pinctrl_pmic: pmicirq {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
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MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
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MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
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MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
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MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -55,6 +55,11 @@ config TARGET_IMX8MP_EVK
|
||||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
|
||||
config TARGET_PICO_IMX8MQ
|
||||
bool "Support Technexion Pico iMX8MQ"
|
||||
select IMX8MQ
|
||||
select IMX8M_LPDDR4
|
||||
|
||||
config TARGET_VERDIN_IMX8MM
|
||||
bool "Support Toradex Verdin iMX8M Mini module"
|
||||
select IMX8MM
|
||||
@ -68,6 +73,7 @@ source "board/freescale/imx8mm_evk/Kconfig"
|
||||
source "board/freescale/imx8mn_evk/Kconfig"
|
||||
source "board/freescale/imx8mp_evk/Kconfig"
|
||||
source "board/google/imx8mq_phanbell/Kconfig"
|
||||
source "board/technexion/pico-imx8mq/Kconfig"
|
||||
source "board/toradex/verdin-imx8mm/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
12
board/technexion/pico-imx8mq/Kconfig
Normal file
12
board/technexion/pico-imx8mq/Kconfig
Normal file
@ -0,0 +1,12 @@
|
||||
if TARGET_PICO_IMX8MQ
|
||||
|
||||
config SYS_BOARD
|
||||
default "pico-imx8mq"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "technexion"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "pico-imx8mq"
|
||||
|
||||
endif
|
||||
6
board/technexion/pico-imx8mq/MAINTAINERS
Normal file
6
board/technexion/pico-imx8mq/MAINTAINERS
Normal file
@ -0,0 +1,6 @@
|
||||
PICOPI IMX8MQ BOARD
|
||||
M: Marek Vasut <marek.vasut@gmail.com>
|
||||
S: Maintained
|
||||
F: board/technexion/pico-imx8mq/
|
||||
F: include/configs/pico-imx8mq.h
|
||||
F: configs/pico-imx8mq_defconfig
|
||||
12
board/technexion/pico-imx8mq/Makefile
Normal file
12
board/technexion/pico-imx8mq/Makefile
Normal file
@ -0,0 +1,12 @@
|
||||
#
|
||||
# Copyright 2017 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += pico-imx8mq.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o
|
||||
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_1gb.o lpddr4_timing_2gb.o lpddr4_timing_3gb.o lpddr4_timing_4gb.o
|
||||
endif
|
||||
52
board/technexion/pico-imx8mq/README
Normal file
52
board/technexion/pico-imx8mq/README
Normal file
@ -0,0 +1,52 @@
|
||||
U-Boot for the Technexion Pico i.MX8MQ
|
||||
|
||||
Quick Start
|
||||
===========
|
||||
- Build the TFA binary
|
||||
- Get DDR and HDMI firmware
|
||||
- Build U-Boot
|
||||
- Boot
|
||||
|
||||
Get and Build the TFA blob
|
||||
==========================
|
||||
Note: srctree is U-Boot source directory
|
||||
Get ATF from: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
|
||||
branch: master
|
||||
$ CROSS_COMPILE=aarch64-linux-gnu- make PLAT=imx8mq bl31
|
||||
$ cp build/imx8mq/release/bl31.bin $(builddir)
|
||||
|
||||
Get the DDR and HDMI firmware
|
||||
=============================
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
|
||||
$ chmod +x firmware-imx-7.9.bin
|
||||
$ ./firmware-imx-7.9.bin
|
||||
# Or use this to avoid running random scripts from the internet,
|
||||
# but note that you must agree to the license the script displays:
|
||||
# $ dd if=firmware-imx-7.9.bin of=firmware-imx-7.9.tar.bz2 bs=38868 skip=1
|
||||
# $ tar -xf firmware-imx-7.9.tar.bz2
|
||||
$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir)
|
||||
$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
|
||||
|
||||
Build U-Boot
|
||||
============
|
||||
$ export CROSS_COMPILE=aarch64-poky-linux-
|
||||
$ make pico-imx8mq_defconfig
|
||||
$ make flash.bin
|
||||
|
||||
Burn the flash.bin to MicroSD card offset 33KB
|
||||
$ dd if=flash.bin of=/dev/mmcblkX bs=1024 seek=33
|
||||
Or into eMMC from a running system
|
||||
$ dhcp flash.bin && mmc write $loadaddr 0x42 0x800
|
||||
|
||||
Boot
|
||||
====
|
||||
"o" denotes a pin
|
||||
"[]" denotes two pins bridged by a jumper
|
||||
|
||||
eMMC boot:
|
||||
J1 o[] []o J2
|
||||
[]o o[]
|
||||
|
||||
USB upload via USB-C connector:
|
||||
J1 ooo ooo J2
|
||||
o[] []o
|
||||
14
board/technexion/pico-imx8mq/lpddr4_timing.h
Normal file
14
board/technexion/pico-imx8mq/lpddr4_timing.h
Normal file
@ -0,0 +1,14 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2020 Marek Vasut <marek.vasut@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef __LPDDR4_TIMING_H__
|
||||
#define __LPDDR4_TIMING_H__
|
||||
|
||||
extern struct dram_timing_info dram_timing_1gb;
|
||||
extern struct dram_timing_info dram_timing_2gb;
|
||||
extern struct dram_timing_info dram_timing_3gb;
|
||||
extern struct dram_timing_info dram_timing_4gb;
|
||||
|
||||
#endif /* __LPDDR4_TIMING_H__ */
|
||||
1734
board/technexion/pico-imx8mq/lpddr4_timing_1gb.c
Normal file
1734
board/technexion/pico-imx8mq/lpddr4_timing_1gb.c
Normal file
File diff suppressed because it is too large
Load Diff
1734
board/technexion/pico-imx8mq/lpddr4_timing_2gb.c
Normal file
1734
board/technexion/pico-imx8mq/lpddr4_timing_2gb.c
Normal file
File diff suppressed because it is too large
Load Diff
1734
board/technexion/pico-imx8mq/lpddr4_timing_3gb.c
Normal file
1734
board/technexion/pico-imx8mq/lpddr4_timing_3gb.c
Normal file
File diff suppressed because it is too large
Load Diff
1734
board/technexion/pico-imx8mq/lpddr4_timing_4gb.c
Normal file
1734
board/technexion/pico-imx8mq/lpddr4_timing_4gb.c
Normal file
File diff suppressed because it is too large
Load Diff
146
board/technexion/pico-imx8mq/pico-imx8mq.c
Normal file
146
board/technexion/pico-imx8mq/pico-imx8mq.c
Normal file
@ -0,0 +1,146 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <init.h>
|
||||
#include <malloc.h>
|
||||
#include <errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm-generic/gpio.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <mmc.h>
|
||||
#include <asm/arch/imx8mq_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/gpio.h>
|
||||
#include <asm/mach-imx/mxc_i2c.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <spl.h>
|
||||
#include <power/pmic.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
|
||||
|
||||
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
|
||||
|
||||
static iomux_v3_cfg_t const wdog_pads[] = {
|
||||
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const uart_pads[] = {
|
||||
IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
||||
set_wdog_reset(wdog);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
|
||||
|
||||
if (ddr_size == 0x4)
|
||||
gd->ram_size = 0x100000000;
|
||||
else if (ddr_size == 0x3)
|
||||
gd->ram_size = 0xc0000000;
|
||||
else if (ddr_size == 0x2)
|
||||
gd->ram_size = 0x80000000;
|
||||
else if (ddr_size == 0x1)
|
||||
gd->ram_size = 0x40000000;
|
||||
else
|
||||
printf("Unknown DDR type!!!\n");
|
||||
|
||||
/* rom_pointer[1] contains the size of TEE occupies */
|
||||
if (rom_pointer[1])
|
||||
gd->ram_size -= rom_pointer[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
|
||||
#define FEC_PWR_PAD IMX_GPIO_NR(1, 0)
|
||||
static iomux_v3_cfg_t const fec1_pads[] = {
|
||||
/* Reset */
|
||||
IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* Power */
|
||||
IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_fec(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
|
||||
|
||||
gpio_request(IMX_GPIO_NR(1, 0), "fec1_pwr");
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 0), 1);
|
||||
udelay(500);
|
||||
|
||||
gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
|
||||
udelay(500);
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
|
||||
}
|
||||
|
||||
static int setup_fec(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *gpr =
|
||||
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
|
||||
setup_iomux_fec();
|
||||
|
||||
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
|
||||
clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
|
||||
return set_clk_enet(ENET_125MHZ);
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
/* enable rgmii rxc skew and phy mode select to RGMII copper */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
|
||||
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
return devno;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
env_set("board_rev", "iMX8MQ");
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
223
board/technexion/pico-imx8mq/spl.c
Normal file
223
board/technexion/pico-imx8mq/spl.c
Normal file
@ -0,0 +1,223 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <hang.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
#include <asm/arch/imx8mq_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-imx/gpio.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/mach-imx/mxc_i2c.h>
|
||||
#include <errno.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <mmc.h>
|
||||
#include <spl.h>
|
||||
|
||||
#include "lpddr4_timing.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define DDR_DET_1 IMX_GPIO_NR(3, 11)
|
||||
#define DDR_DET_2 IMX_GPIO_NR(3, 12)
|
||||
#define DDR_DET_3 IMX_GPIO_NR(3, 13)
|
||||
|
||||
static iomux_v3_cfg_t const verdet_pads[] = {
|
||||
IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
/*
|
||||
* DDR_DET_1 DDR_DET_2 DDR_DET_3
|
||||
* 0 0 1 4G LPDDR4
|
||||
* 1 1 1 3G LPDDR4
|
||||
* 1 1 0 2G LPDDR4
|
||||
* 1 0 1 1G LPDDR4
|
||||
*/
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
struct dram_timing_info *dram_timing;
|
||||
u8 ddr = 0, size;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(verdet_pads, ARRAY_SIZE(verdet_pads));
|
||||
|
||||
gpio_request(DDR_DET_1, "ddr_det_1");
|
||||
gpio_direction_input(DDR_DET_1);
|
||||
gpio_request(DDR_DET_2, "ddr_det_2");
|
||||
gpio_direction_input(DDR_DET_2);
|
||||
gpio_request(DDR_DET_3, "ddr_det_3");
|
||||
gpio_direction_input(DDR_DET_3);
|
||||
|
||||
ddr |= !!gpio_get_value(DDR_DET_3) << 0;
|
||||
ddr |= !!gpio_get_value(DDR_DET_2) << 1;
|
||||
ddr |= !!gpio_get_value(DDR_DET_1) << 2;
|
||||
|
||||
switch (ddr) {
|
||||
case 0x1:
|
||||
size = 4;
|
||||
dram_timing = &dram_timing_4gb;
|
||||
break;
|
||||
case 0x7:
|
||||
size = 3;
|
||||
dram_timing = &dram_timing_3gb;
|
||||
break;
|
||||
case 0x6:
|
||||
size = 2;
|
||||
dram_timing = &dram_timing_2gb;
|
||||
break;
|
||||
case 0x5:
|
||||
size = 1;
|
||||
dram_timing = &dram_timing_1gb;
|
||||
break;
|
||||
default:
|
||||
puts("Unknown DDR type!!!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
printf("%s: LPDDR4 %d GiB\n", __func__, size);
|
||||
ddr_init(dram_timing);
|
||||
writel(size, M4_BOOTROM_BASE_ADDR);
|
||||
}
|
||||
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
|
||||
#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
|
||||
#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC1_BASE_ADDR:
|
||||
ret = 1;
|
||||
break;
|
||||
case USDHC2_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
|
||||
PAD_CTL_FSEL2)
|
||||
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
|
||||
|
||||
static iomux_v3_cfg_t const usdhc1_pads[] = {
|
||||
IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
||||
IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
||||
{USDHC1_BASE_ADDR, 0, 8},
|
||||
{USDHC2_BASE_ADDR, 0, 4},
|
||||
};
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-Boot device node) (Physical Port)
|
||||
* mmc0 USDHC1
|
||||
* mmc1 USDHC2
|
||||
*/
|
||||
init_clk_usdhc(0);
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
|
||||
gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
|
||||
gpio_direction_output(USDHC1_PWR_GPIO, 0);
|
||||
udelay(500);
|
||||
gpio_direction_output(USDHC1_PWR_GPIO, 1);
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
init_clk_usdhc(1);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
||||
gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
|
||||
gpio_direction_output(USDHC2_PWR_GPIO, 0);
|
||||
udelay(500);
|
||||
gpio_direction_output(USDHC2_PWR_GPIO, 1);
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
puts("Normal Boot\n");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_LOAD_FIT
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
/* Just empty function now - can't decide what to choose */
|
||||
debug("%s: %s\n", __func__, name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Clear global data */
|
||||
memset((void *)gd, 0, sizeof(gd_t));
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
init_uart_clk(0);
|
||||
|
||||
board_early_init_f();
|
||||
|
||||
timer_init();
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
ret = spl_init();
|
||||
if (ret) {
|
||||
debug("spl_init() failed: %d\n", ret);
|
||||
hang();
|
||||
}
|
||||
|
||||
enable_tzc380();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
47
configs/pico-imx8mq_defconfig
Normal file
47
configs/pico-imx8mq_defconfig
Normal file
@ -0,0 +1,47 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_IMX8M=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40200000
|
||||
CONFIG_ENV_SIZE=0x1000
|
||||
CONFIG_ENV_OFFSET=0x400000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_TARGET_PICO_IMX8MQ=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_CSF_SIZE=0x2000
|
||||
CONFIG_SPL_TEXT_BASE=0x7E1000
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-pico-pi"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_MXC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8M=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_IMX8M_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
199
include/configs/pico-imx8mq.h
Normal file
199
include/configs/pico-imx8mq.h
Normal file
@ -0,0 +1,199 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __IMX8M_PICOPI_H
|
||||
#define __IMX8M_PICOPI_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
|
||||
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
|
||||
#define CONFIG_SPL_WATCHDOG_SUPPORT
|
||||
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
|
||||
#define CONFIG_SPL_POWER_SUPPORT
|
||||
#define CONFIG_SPL_I2C_SUPPORT
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
|
||||
#define CONFIG_SPL_STACK 0x187FF0
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_GPIO_SUPPORT
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
|
||||
#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
|
||||
|
||||
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
|
||||
#define CONFIG_MALLOC_F_ADDR 0x182000
|
||||
/* For RAW image gives a error info not panic */
|
||||
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
|
||||
|
||||
#undef CONFIG_DM_MMC
|
||||
#undef CONFIG_DM_PMIC
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#endif
|
||||
|
||||
#define CONFIG_REMAKE_ELF
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
#undef CONFIG_CMD_EXPORTENV
|
||||
#undef CONFIG_CMD_IMPORTENV
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
#undef CONFIG_CMD_CRC32
|
||||
|
||||
/* ENET Config */
|
||||
/* ENET1 */
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_FEC_MXC_PHYADDR 1
|
||||
#define FEC_QUIRK_ENET_MAC
|
||||
|
||||
#define CONFIG_PHY_GIGE
|
||||
#define IMX_FEC_BASE 0x30BE0000
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
#endif
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=Image\0" \
|
||||
"console=ttymxc0,115200\0" \
|
||||
"fdt_addr=0x43000000\0" \
|
||||
"fdt_high=0xffffffffffffffff\0" \
|
||||
"fdt_file=imx8mq-pico-pi.dtb\0" \
|
||||
"initrd_addr=0x43800000\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"echo wait for boot; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${loadaddr} ${image}; " \
|
||||
"booti; "
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else booti ${loadaddr} - ${fdt_addr}; fi"
|
||||
|
||||
/* Link Definitions */
|
||||
#define CONFIG_LOADADDR 0x40480000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define PHYS_SDRAM 0x40000000
|
||||
#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
|
||||
(PHYS_SDRAM_SIZE >> 1))
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 1024
|
||||
#define CONFIG_SYS_MAXARGS 64
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
#define CONFIG_IMX_BOOTAUX
|
||||
|
||||
#define CONFIG_CMD_MMC
|
||||
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
#define CONFIG_MXC_GPIO
|
||||
|
||||
#define CONFIG_CMD_FUSE
|
||||
|
||||
/* I2C Configs */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
#define CONFIG_OF_SYSTEM_SETUP
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_DM_PMIC
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BOOTM_LEN SZ_128M
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user