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Merge tag 'xilinx-for-v2017.05' of git://www.denx.de/git/u-boot-microblaze

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Xilinx changes for v2017.05

- Move to DM clk driver
- Add clk support for zynq_sdhci
This commit is contained in:
Tom Rini
2017-03-16 16:44:23 -04:00
parent ce38ebb6f7 61e745d131
commit b504ff9f6b
18 changed files with 632 additions and 697 deletions
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29
drivers/net/zynq_gem.c
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@@ -175,16 +175,13 @@ struct zynq_gem_priv {
u32 rxbd_current;
u32 rx_first_buf;
int phyaddr;
u32 emio;
int init;
struct zynq_gem_regs *iobase;
phy_interface_t interface;
struct phy_device *phydev;
int phy_of_handle;
struct mii_dev *bus;
#ifdef CONFIG_CLK_ZYNQMP
struct clk clk;
#endif
};
static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
@@ -457,16 +454,17 @@ static int zynq_gem_init(struct udevice *dev)
break;
}
/* Change the rclk and clk only not using EMIO interface */
if (!priv->emio)
#ifndef CONFIG_CLK_ZYNQMP
zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
ZYNQ_GEM_BASEADDR0, clk_rate);
#else
ret = clk_set_rate(&priv->clk, clk_rate);
if (IS_ERR_VALUE(ret))
return -1;
#endif
ret = clk_set_rate(&priv->clk, clk_rate);
if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
dev_err(dev, "failed to set tx clock rate\n");
return ret;
}
ret = clk_enable(&priv->clk);
if (ret && ret != -ENOSYS) {
dev_err(dev, "failed to enable tx clock\n");
return ret;
}
setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);
@@ -639,13 +637,11 @@ static int zynq_gem_probe(struct udevice *dev)
priv->tx_bd = (struct emac_bd *)bd_space;
priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
#ifdef CONFIG_CLK_ZYNQMP
ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
if (ret < 0) {
dev_err(dev, "failed to get clock\n");
return -EINVAL;
}
#endif
priv->bus = mdio_alloc();
priv->bus->read = zynq_gem_miiphy_read;
@@ -690,7 +686,6 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
/* Hardcode for now */
priv->emio = 0;
priv->phyaddr = -1;
priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
@@ -708,8 +703,6 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
}
priv->interface = pdata->phy_interface;
priv->emio = fdtdec_get_bool(gd->fdt_blob, node, "xlnx,emio");
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));