leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

arm: Move MAX_CPUS to Kconfig

Browse Source 
Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This
option is used by Freescale Layerscape SoCs.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
York Sun 2016-10-04 14:45:01 -07:00
parent fb2bf8c2c6
commit b4b60d06c6
4 changed files with 24 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm/cpu/armv7/ls102xa/Kconfig
View File

@ -9,6 +9,17 @@ config LS1_DEEP_SLEEP
bool "Deep sleep"
depends on ARCH_LS1021A
config MAX_CPUS
int "Maximum number of CPUs permitted for LS102xA"
depends on ARCH_LS1021A
default 2
help
Set this number to the maximum number of possible CPUs in the SoC.
SoCs may have multiple clusters with each cluster may have multiple
ports. If some ports are reserved but higher ports are used for
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"

13
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -37,4 +37,17 @@ config SYS_FSL_ERRATUM_A010315
config SYS_FSL_ERRATUM_A010539
bool "Workaround for PIN MUX erratum A010539"
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 16 if ARCH_LS2080A
default 1
help
Set this number to the maximum number of possible CPUs in the SoC.
SoCs may have multiple clusters with each cluster may have multiple
ports. If some ports are reserved but higher ports are used for
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
endmenu

4
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -30,7 +30,6 @@
#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
#ifdef CONFIG_LS2080A
#define CONFIG_MAX_CPUS 16
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_NUM_DDR_CONTROLLERS 3
#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */
@ -171,7 +170,6 @@
/* SoC related */
#ifdef CONFIG_LS1043A
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 7
@ -206,13 +204,11 @@
#define CONFIG_SYS_FSL_ERRATUM_A009660
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_ARCH_LS1012A)
#define CONFIG_MAX_CPUS 1
#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
#elif defined(CONFIG_ARCH_LS1046A)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 8

1
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -123,7 +123,6 @@
#define CONFIG_SYS_FSL_SRDS_1
#ifdef CONFIG_LS102XA
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0