i2c: IHS I2C master driver
IHS I2C master support was merely a hack in the osd driver. Now it is a proper u-boot I2C framework driver, supporting the v2.00 master features. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
This commit is contained in:
Dirk Eibach
Tom Rini
parent
edfe9fea7c
commit
b46226bdb5
15
README
15
README
@ -2288,6 +2288,21 @@ CBFS (Coreboot Filesystem) support
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9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
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with a fix speed from 100000 and the slave addr 0!
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- drivers/i2c/ihs_i2c.c
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- activate this driver with CONFIG_SYS_I2C_IHS
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- CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0
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- CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0
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- CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0
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- CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1
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- CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1
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- CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1
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- CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2
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- CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2
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- CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2
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- CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
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- CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
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- CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3
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additional defines:
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CONFIG_SYS_NUM_I2C_BUSES
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@ -18,6 +18,7 @@ obj-$(CONFIG_SYS_I2C) += i2c_core.o
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obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
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obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
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obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
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obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
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obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
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obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
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obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
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204
drivers/i2c/ihs_i2c.c
Normal file
204
drivers/i2c/ihs_i2c.c
Normal file
@ -0,0 +1,204 @@
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/*
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* (C) Copyright 2013
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <gdsys_fpga.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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I2CINT_ERROR_EV = 1 << 13,
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I2CINT_TRANSMIT_EV = 1 << 14,
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I2CINT_RECEIVE_EV = 1 << 15,
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};
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enum {
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I2CMB_WRITE = 1 << 10,
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I2CMB_2BYTE = 1 << 11,
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I2CMB_HOLD_BUS = 1 << 13,
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I2CMB_NATIVE = 2 << 14,
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};
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static int wait_for_int(bool read)
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{
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u16 val;
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unsigned int ctr = 0;
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
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while (!(val & (I2CINT_ERROR_EV
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| (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
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udelay(10);
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if (ctr++ > 5000) {
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printf("I2C timeout\n");
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return 1;
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}
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
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}
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return (val & I2CINT_ERROR_EV) ? 1 : 0;
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}
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static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
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bool is_last)
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{
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u16 val;
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FPGA_SET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, I2CINT_ERROR_EV
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| I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV);
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
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if (!read && len) {
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val = buffer[0];
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if (len > 1)
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val |= buffer[1] << 8;
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FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox_ext, val);
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}
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FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox,
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I2CMB_NATIVE
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| (read ? 0 : I2CMB_WRITE)
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| (chip << 1)
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| ((len > 1) ? I2CMB_2BYTE : 0)
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| (is_last ? 0 : I2CMB_HOLD_BUS));
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if (wait_for_int(read))
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return 1;
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if (read) {
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c.read_mailbox_ext, &val);
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buffer[0] = val & 0xff;
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if (len > 1)
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buffer[1] = val >> 8;
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}
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return 0;
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}
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static int ihs_i2c_address(uchar chip, uint addr, int alen, bool hold_bus)
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{
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int shift = (alen-1) * 8;
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while (alen) {
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int transfer = MIN(alen, 2);
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uchar buf[2];
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bool is_last = alen <= transfer;
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buf[0] = addr >> shift;
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if (alen > 1)
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buf[1] = addr >> (shift - 8);
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if (ihs_i2c_transfer(chip, buf, transfer, false,
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hold_bus ? false : is_last))
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return 1;
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shift -= 16;
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alen -= transfer;
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}
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return 0;
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}
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static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buffer, int len, bool read)
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{
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if (len <= 0)
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return 1;
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if (ihs_i2c_address(chip, addr, alen, !read))
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return 1;
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while (len) {
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int transfer = MIN(len, 2);
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if (ihs_i2c_transfer(chip, buffer, transfer, read,
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len <= transfer))
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return 1;
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buffer += transfer;
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addr += transfer;
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len -= transfer;
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}
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return 0;
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}
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static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
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{
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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/*
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* Call board specific i2c bus reset routine before accessing the
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* environment, which might be in a chip on that bus. For details
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* about this problem see doc/I2C_Edge_Conditions.
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*/
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i2c_init_board();
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#endif
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}
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static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
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{
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uchar buffer[2];
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if (ihs_i2c_transfer(chip, buffer, 0, true, true))
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return 1;
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return 0;
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}
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static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buffer, int len)
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{
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return ihs_i2c_access(adap, chip, addr, alen, buffer, len, true);
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}
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static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buffer, int len)
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{
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return ihs_i2c_access(adap, chip, addr, alen, buffer, len, false);
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}
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static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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{
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if (speed != adap->speed)
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return 1;
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return speed;
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}
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/*
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* Register IHS i2c adapters
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*/
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#ifdef CONFIG_SYS_I2C_IHS_CH0
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U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_0,
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CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_CH1
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U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_1,
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CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_CH2
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U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_2,
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CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_CH3
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U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_3,
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CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
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#endif
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@ -99,7 +99,18 @@
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*/
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#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
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#define CONFIG_SYS_I2C_IHS
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#define CONFIG_SYS_I2C_IHS_CH0
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#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
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#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
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#define CONFIG_SYS_I2C_IHS_CH1
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#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
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#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
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#define CONFIG_SYS_SPD_BUS_NUM 2
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/* Temp sensor/hwmon/dtt */
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#define CONFIG_SYS_DTT_BUS_NUM 2
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#define CONFIG_DTT_LM63 1 /* National LM63 */
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#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
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#define CONFIG_DTT_PWM_LOOKUPTABLE \
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@ -99,12 +99,27 @@
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#define CONFIG_SYS_I2C_PPC4XX_CH0
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#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
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#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
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#define CONFIG_SYS_I2C_IHS
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#define CONFIG_SYS_I2C_SPEED 400000
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#define CONFIG_SYS_SPD_BUS_NUM 4
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#define CONFIG_PCA953X /* NXP PCA9554 */
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#define CONFIG_PCA9698 /* NXP PCA9698 */
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#define CONFIG_SYS_I2C_IHS_CH0
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#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
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#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
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#define CONFIG_SYS_I2C_IHS_CH1
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#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
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#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
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#define CONFIG_SYS_I2C_IHS_CH2
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#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
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#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
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#define CONFIG_SYS_I2C_IHS_CH3
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#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
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#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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@ -121,9 +136,9 @@
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#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
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#define CONFIG_SYS_ICS8N3QV01_I2C {1, 2, 3, 4}
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#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
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#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
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#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
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#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
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#define CONFIG_SYS_DP501_I2C {0, 1, 2, 3}
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#ifndef __ASSEMBLY__
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void fpga_gpio_set(unsigned int bus, int pin);
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@ -148,8 +163,6 @@ int fpga_gpio_get(unsigned int bus, int pin);
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fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
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else \
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fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
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while (!!fpga_gpio_get(I2C_ADAP_HWNR, 0x0020) != !!bit) \
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; \
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} while (0)
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#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
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@ -43,10 +43,12 @@ struct ihs_gpio {
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};
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struct ihs_i2c {
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u16 write_mailbox;
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u16 interrupt_status;
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u16 interrupt_enable;
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u16 write_mailbox_ext;
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u16 read_mailbox;
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u16 write_mailbox;
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u16 read_mailbox_ext;
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u16 read_mailbox;
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};
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struct ihs_osd {
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@ -84,7 +86,6 @@ struct ihs_fpga {
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#endif
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#ifdef CONFIG_IO64
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struct ihs_fpga_channel {
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u16 status_int;
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u16 config_int;
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@ -121,9 +122,9 @@ struct ihs_fpga {
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u16 reserved_0[6]; /* 0x0008 */
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struct ihs_gpio gpio; /* 0x0014 */
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u16 mpc3w_control; /* 0x001a */
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u16 reserved_1[19]; /* 0x001c */
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u16 videocontrol; /* 0x0042 */
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u16 reserved_2[14]; /* 0x0044 */
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u16 reserved_1[18]; /* 0x001c */
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struct ihs_i2c i2c; /* 0x0040 */
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u16 reserved_2[10]; /* 0x004c */
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u16 mc_int; /* 0x0060 */
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u16 mc_int_en; /* 0x0062 */
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u16 mc_status; /* 0x0064 */
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@ -150,15 +151,13 @@ struct ihs_fpga {
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u16 fpga_features; /* 0x0006 */
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u16 reserved_0[10]; /* 0x0008 */
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u16 extended_interrupt; /* 0x001c */
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u16 reserved_1[9]; /* 0x001e */
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struct ihs_i2c i2c; /* 0x0030 */
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u16 reserved_2[16]; /* 0x0038 */
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u16 reserved_1[29]; /* 0x001e */
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u16 mpc3w_control; /* 0x0058 */
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u16 reserved_3[34]; /* 0x005a */
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u16 videocontrol; /* 0x009e */
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u16 reserved_4[176]; /* 0x00a0 */
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u16 reserved_2[3]; /* 0x005a */
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struct ihs_i2c i2c; /* 0x0060 */
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u16 reserved_3[205]; /* 0x0066 */
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struct ihs_osd osd; /* 0x0200 */
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u16 reserved_5[761]; /* 0x020e */
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u16 reserved_4[761]; /* 0x020e */
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u16 videomem[31736]; /* 0x0800 */
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};
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#endif
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