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85xx: Add QE clk support

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Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <Timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Haiying Wang 2009-05-20 12:30:29 -04:00 committed by Kumar Gala
parent 71b358cc26
commit b3d7f20f43
4 changed files with 21 additions and 1 deletions
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4
cpu/mpc85xx/cpu.c
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@ -186,6 +186,10 @@ int checkcpu (void)
printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
#endif
#ifdef CONFIG_QE
printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
#endif
puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
return 0;

15
cpu/mpc85xx/speed.c
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@ -1,5 +1,5 @@
/*
* Copyright 2004 Freescale Semiconductor.
* Copyright 2004, 2007-2009 Freescale Semiconductor Inc.
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
@ -40,6 +40,9 @@ void get_sys_info (sys_info_t * sysInfo)
uint plat_ratio,e500_ratio,half_freqSystemBus;
uint lcrr_div;
int i;
#ifdef CONFIG_QE
u32 qe_ratio;
#endif
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
@ -65,6 +68,12 @@ void get_sys_info (sys_info_t * sysInfo)
}
#endif
#ifdef CONFIG_QE
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
#if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
@ -112,6 +121,10 @@ int get_clocks (void)
gd->mem_clk = sys_info.freqDDRBus;
gd->lbc_clk = sys_info.freqLocalBus;
#ifdef CONFIG_QE
gd->qe_clk = sys_info.freqQE;
gd->brg_clk = gd->qe_clk / 2;
#endif
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,
* there is no pattern that can be used to determine the frequency, so

2
include/asm-ppc/immap_85xx.h
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@ -1596,6 +1596,8 @@ typedef struct ccsr_gur {
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
#endif
#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
uint porbmsr; /* 0xe0004 - POR boot mode status register */
#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */

1
include/e500.h
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@ -18,6 +18,7 @@ typedef struct
unsigned long freqSystemBus;
unsigned long freqDDRBus;
unsigned long freqLocalBus;
unsigned long freqQE;
} MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */