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arm: dra7: Allow NAND to be enabled on DRA71x EVM.

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If SW 8 pins 0 and 1 indicate that NAND should be enabled then
the pins pinmux must be reconfigured for NAND mode.

Therefore, enable NAND by reconfiguring the pinmux.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
This commit is contained in:
Franklin S Cooper Jr 2019-02-27 13:29:36 +05:30 committed by Tom Rini
parent f072aff944
commit b3b2a9ea3e
1 changed files with 56 additions and 0 deletions
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56
board/ti/dra7xx/evm.c
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@ -27,6 +27,7 @@
#include <environment.h> #include <environment.h>
#include <dwc3-uboot.h> #include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h> #include <dwc3-omap-uboot.h>
#include <i2c.h>
#include <ti-usb-phy-uboot.h> #include <ti-usb-phy-uboot.h>
#include <miiphy.h> #include <miiphy.h>
@ -55,6 +56,10 @@ DECLARE_GLOBAL_DATA_PTR;
#define SYSINFO_BOARD_NAME_MAX_LEN 37 #define SYSINFO_BOARD_NAME_MAX_LEN 37
/* I2C I/O Expander */
#define NAND_PCF8575_ADDR 0x21
#define NAND_PCF8575_I2C_BUS_NUM 0
const struct omap_sysinfo sysinfo = { const struct omap_sysinfo sysinfo = {
"Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n" "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
}; };
@ -777,6 +782,44 @@ void set_muxconf_regs(void)
early_padconf, ARRAY_SIZE(early_padconf)); early_padconf, ARRAY_SIZE(early_padconf));
} }
#if defined(CONFIG_NAND)
static int nand_sw_detect(void)
{
int rc;
uchar data[2];
struct udevice *dev;
rc = i2c_get_chip_for_busnum(NAND_PCF8575_I2C_BUS_NUM,
NAND_PCF8575_ADDR, 0, &dev);
if (rc)
return -1;
rc = dm_i2c_read(dev, 0, (uint8_t *)&data, sizeof(data));
if (rc)
return -1;
/* We are only interested in P10 and P11 on PCF8575 which is equal to
* bits 8 and 9.
*/
data[1] = data[1] & 0x3;
/* Ensure only P11 is set and P10 is cleared. This ensures only
* NAND (P10) is configured and not NOR (P11) which are both low
* true signals. NAND and NOR settings should not be enabled at
* the same time.
*/
if (data[1] == 0x2)
return 0;
return -1;
}
#else
int nand_sw_detect(void)
{
return -1;
}
#endif
#ifdef CONFIG_IODELAY_RECALIBRATION #ifdef CONFIG_IODELAY_RECALIBRATION
void recalibrate_iodelay(void) void recalibrate_iodelay(void)
{ {
@ -796,6 +839,19 @@ void recalibrate_iodelay(void)
npads = ARRAY_SIZE(dra71x_core_padconf_array); npads = ARRAY_SIZE(dra71x_core_padconf_array);
iodelay = dra71_iodelay_cfg_array; iodelay = dra71_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array); niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
/* If SW8 on the EVM is set to enable NAND then
* overwrite the pins used by VOUT3 with NAND.
*/
if (!nand_sw_detect()) {
delta_pads = dra71x_nand_padconf_array;
delta_npads =
ARRAY_SIZE(dra71x_nand_padconf_array);
} else {
delta_pads = dra71x_vout3_padconf_array;
delta_npads =
ARRAY_SIZE(dra71x_vout3_padconf_array);
}
} else if (board_is_dra72x_revc_or_later()) { } else if (board_is_dra72x_revc_or_later()) {
delta_pads = dra72x_rgmii_padconf_array_revc; delta_pads = dra72x_rgmii_padconf_array_revc;
delta_npads = delta_npads =