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ARM: tegra: pinmux: partially handle varying register layouts

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Tegra210 moves some bits around in the pinmux registers. Update the code
to handle this.

This doesn't attempt to address the issues with the group-to-group varying
drive group register layout mentioned earlier. This patch handles the
SoC-to-SoC differences in the mux register layout.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren 2015-02-24 14:08:27 -07:00 committed by Tom Warren
parent bc13472867
commit b2cd3d8103
1 changed files with 12 additions and 0 deletions
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12
arch/arm/mach-tegra/pinmux-common.c
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@ -101,11 +101,23 @@
#define DRV_REG(group) _R(0x868 + ((group) * 4)) #define DRV_REG(group) _R(0x868 + ((group) * 4))
/*
* We could force arch-tegraNN/pinmux.h to define all of these. However,
* that's a lot of defines, and for now it's manageable to just put a
* special case here. It's possible this decision will change with future
* SoCs.
*/
#ifdef CONFIG_TEGRA210
#define IO_SHIFT 6
#define LOCK_SHIFT 7
#define OD_SHIFT 11
#else
#define IO_SHIFT 5 #define IO_SHIFT 5
#define OD_SHIFT 6 #define OD_SHIFT 6
#define LOCK_SHIFT 7 #define LOCK_SHIFT 7
#define IO_RESET_SHIFT 8 #define IO_RESET_SHIFT 8
#define RCV_SEL_SHIFT 9 #define RCV_SEL_SHIFT 9
#endif
#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
/* This register/field only exists on Tegra114 and later */ /* This register/field only exists on Tegra114 and later */