OMAP3: Add MMC support
Add MMC support. Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
This commit is contained in:
Dirk Behme
Jean-Christophe PLAGNIOL-VILLARD
parent
12201a1354
commit
b1c3bf99fb
@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
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LIB := $(obj)libmmc.a
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COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
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COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
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COBJS := $(COBJS-y)
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SRCS := $(COBJS:.o=.c)
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558
drivers/mmc/omap3_mmc.c
Normal file
558
drivers/mmc/omap3_mmc.c
Normal file
@ -0,0 +1,558 @@
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/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation's version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <fat.h>
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#include <mmc.h>
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#include <part.h>
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#include <i2c.h>
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const unsigned short mmc_transspeed_val[15][4] = {
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{CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)},
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{CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)},
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{CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)},
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{CLKD(15, 1), CLKD(15, 10), CLKD(15, 100), CLKD(15, 1000)},
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{CLKD(20, 1), CLKD(20, 10), CLKD(20, 100), CLKD(20, 1000)},
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{CLKD(26, 1), CLKD(26, 10), CLKD(26, 100), CLKD(26, 1000)},
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{CLKD(30, 1), CLKD(30, 10), CLKD(30, 100), CLKD(30, 1000)},
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{CLKD(35, 1), CLKD(35, 10), CLKD(35, 100), CLKD(35, 1000)},
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{CLKD(40, 1), CLKD(40, 10), CLKD(40, 100), CLKD(40, 1000)},
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{CLKD(45, 1), CLKD(45, 10), CLKD(45, 100), CLKD(45, 1000)},
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{CLKD(52, 1), CLKD(52, 10), CLKD(52, 100), CLKD(52, 1000)},
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{CLKD(55, 1), CLKD(55, 10), CLKD(55, 100), CLKD(55, 1000)},
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{CLKD(60, 1), CLKD(60, 10), CLKD(60, 100), CLKD(60, 1000)},
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{CLKD(70, 1), CLKD(70, 10), CLKD(70, 100), CLKD(70, 1000)},
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{CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)}
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};
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mmc_card_data cur_card_data;
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static block_dev_desc_t mmc_blk_dev;
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block_dev_desc_t *mmc_get_dev(int dev)
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{
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return (block_dev_desc_t *) &mmc_blk_dev;
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}
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void twl4030_mmc_config(void)
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{
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unsigned char data;
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data = 0x20;
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i2c_write(0x4B, 0x82, 1, &data, 1);
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data = 0x2;
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i2c_write(0x4B, 0x85, 1, &data, 1);
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}
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unsigned char mmc_board_init(void)
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{
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unsigned int value = 0;
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twl4030_mmc_config();
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value = CONTROL_PBIAS_LITE;
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CONTROL_PBIAS_LITE = value | (1 << 2) | (1 << 1) | (1 << 9);
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value = CONTROL_DEV_CONF0;
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CONTROL_DEV_CONF0 = value | (1 << 24);
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return 1;
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}
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void mmc_init_stream(void)
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{
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volatile unsigned int mmc_stat;
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OMAP_HSMMC_CON |= INIT_INITSTREAM;
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OMAP_HSMMC_CMD = MMC_CMD0;
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do {
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mmc_stat = OMAP_HSMMC_STAT;
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} while (!(mmc_stat & CC_MASK));
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OMAP_HSMMC_STAT = CC_MASK;
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OMAP_HSMMC_CMD = MMC_CMD0;
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do {
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mmc_stat = OMAP_HSMMC_STAT;
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} while (!(mmc_stat & CC_MASK));
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OMAP_HSMMC_STAT = OMAP_HSMMC_STAT;
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OMAP_HSMMC_CON &= ~INIT_INITSTREAM;
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}
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unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div)
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{
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unsigned int val;
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mmc_reg_out(OMAP_HSMMC_SYSCTL, (ICE_MASK | DTO_MASK | CEN_MASK),
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(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
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switch (iclk) {
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case CLK_INITSEQ:
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val = MMC_INIT_SEQ_CLK / 2;
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break;
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case CLK_400KHZ:
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val = MMC_400kHz_CLK;
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break;
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case CLK_MISC:
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val = clk_div;
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break;
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default:
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return 0;
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}
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mmc_reg_out(OMAP_HSMMC_SYSCTL,
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ICE_MASK | CLKD_MASK, (val << CLKD_OFFSET) | ICE_OSCILLATE);
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while ((OMAP_HSMMC_SYSCTL & ICS_MASK) == ICS_NOTREADY) ;
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OMAP_HSMMC_SYSCTL |= CEN_ENABLE;
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return 1;
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}
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unsigned char mmc_init_setup(void)
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{
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unsigned int reg_val;
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mmc_board_init();
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OMAP_HSMMC_SYSCONFIG |= MMC_SOFTRESET;
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while ((OMAP_HSMMC_SYSSTATUS & RESETDONE) == 0) ;
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OMAP_HSMMC_SYSCTL |= SOFTRESETALL;
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while ((OMAP_HSMMC_SYSCTL & SOFTRESETALL) != 0x0) ;
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OMAP_HSMMC_HCTL = DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0;
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OMAP_HSMMC_CAPA |= VS30_3V0SUP | VS18_1V8SUP;
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reg_val = OMAP_HSMMC_CON & RESERVED_MASK;
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OMAP_HSMMC_CON = CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH |
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CDP_ACTIVEHIGH | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC |
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STR_BLOCK | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN;
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mmc_clock_config(CLK_INITSEQ, 0);
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OMAP_HSMMC_HCTL |= SDBP_PWRON;
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OMAP_HSMMC_IE = 0x307f0033;
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mmc_init_stream();
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return 1;
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}
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unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg,
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unsigned int *response)
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{
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volatile unsigned int mmc_stat;
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while ((OMAP_HSMMC_PSTATE & DATI_MASK) == DATI_CMDDIS) ;
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OMAP_HSMMC_BLK = BLEN_512BYTESLEN | NBLK_STPCNT;
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OMAP_HSMMC_STAT = 0xFFFFFFFF;
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OMAP_HSMMC_ARG = arg;
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OMAP_HSMMC_CMD = cmd | CMD_TYPE_NORMAL | CICE_NOCHECK |
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CCCE_NOCHECK | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE |
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DE_DISABLE;
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while (1) {
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do {
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mmc_stat = OMAP_HSMMC_STAT;
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} while (mmc_stat == 0);
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if ((mmc_stat & ERRI_MASK) != 0)
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return (unsigned char) mmc_stat;
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if (mmc_stat & CC_MASK) {
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OMAP_HSMMC_STAT = CC_MASK;
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response[0] = OMAP_HSMMC_RSP10;
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if ((cmd & RSP_TYPE_MASK) == RSP_TYPE_LGHT136) {
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response[1] = OMAP_HSMMC_RSP32;
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response[2] = OMAP_HSMMC_RSP54;
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response[3] = OMAP_HSMMC_RSP76;
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}
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break;
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}
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}
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return 1;
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}
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unsigned char mmc_read_data(unsigned int *output_buf)
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{
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volatile unsigned int mmc_stat;
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unsigned int read_count = 0;
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/*
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* Start Polled Read
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*/
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while (1) {
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do {
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mmc_stat = OMAP_HSMMC_STAT;
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} while (mmc_stat == 0);
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if ((mmc_stat & ERRI_MASK) != 0)
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return (unsigned char) mmc_stat;
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if (mmc_stat & BRR_MASK) {
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unsigned int k;
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OMAP_HSMMC_STAT |= BRR_MASK;
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for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) {
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*output_buf = OMAP_HSMMC_DATA;
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output_buf++;
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read_count += 4;
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}
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}
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if (mmc_stat & BWR_MASK)
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OMAP_HSMMC_STAT |= BWR_MASK;
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if (mmc_stat & TC_MASK) {
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OMAP_HSMMC_STAT |= TC_MASK;
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break;
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}
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}
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return 1;
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}
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unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur)
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{
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unsigned char err;
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unsigned int argument = 0;
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unsigned int ocr_value, ocr_recvd, ret_cmd41, hcs_val;
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unsigned int resp[4];
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unsigned short retry_cnt = 2000;
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/* Set to Initialization Clock */
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err = mmc_clock_config(CLK_400KHZ, 0);
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if (err != 1)
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return err;
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mmc_card_cur->RCA = MMC_RELATIVE_CARD_ADDRESS;
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argument = 0x00000000;
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ocr_value = (0x1FF << 15);
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err = mmc_send_cmd(MMC_CMD0, argument, resp);
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if (err != 1)
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return err;
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argument = SD_CMD8_CHECK_PATTERN | SD_CMD8_2_7_3_6_V_RANGE;
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err = mmc_send_cmd(MMC_SDCMD8, argument, resp);
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hcs_val = (err == 1) ?
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MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR :
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MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE;
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argument = 0x0000 << 16;
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err = mmc_send_cmd(MMC_CMD55, argument, resp);
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if (err == 1) {
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mmc_card_cur->card_type = SD_CARD;
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ocr_value |= hcs_val;
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ret_cmd41 = MMC_ACMD41;
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} else {
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mmc_card_cur->card_type = MMC_CARD;
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ocr_value |= MMC_OCR_REG_ACCESS_MODE_SECTOR;
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ret_cmd41 = MMC_CMD1;
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OMAP_HSMMC_CON &= ~OD;
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OMAP_HSMMC_CON |= OPENDRAIN;
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}
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argument = ocr_value;
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err = mmc_send_cmd(ret_cmd41, argument, resp);
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if (err != 1)
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return err;
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ocr_recvd = ((mmc_resp_r3 *) resp)->ocr;
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while (!(ocr_recvd & (0x1 << 31)) && (retry_cnt > 0)) {
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retry_cnt--;
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if (mmc_card_cur->card_type == SD_CARD) {
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argument = 0x0000 << 16;
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err = mmc_send_cmd(MMC_CMD55, argument, resp);
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}
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argument = ocr_value;
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err = mmc_send_cmd(ret_cmd41, argument, resp);
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if (err != 1)
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return err;
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ocr_recvd = ((mmc_resp_r3 *) resp)->ocr;
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}
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if (!(ocr_recvd & (0x1 << 31)))
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return 0;
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if (mmc_card_cur->card_type == MMC_CARD) {
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if ((ocr_recvd & MMC_OCR_REG_ACCESS_MODE_MASK) ==
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MMC_OCR_REG_ACCESS_MODE_SECTOR) {
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mmc_card_cur->mode = SECTOR_MODE;
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} else {
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mmc_card_cur->mode = BYTE_MODE;
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}
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ocr_recvd &= ~MMC_OCR_REG_ACCESS_MODE_MASK;
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} else {
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if ((ocr_recvd & MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK)
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== MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR) {
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mmc_card_cur->mode = SECTOR_MODE;
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} else {
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mmc_card_cur->mode = BYTE_MODE;
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}
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ocr_recvd &= ~MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK;
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}
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ocr_recvd &= ~(0x1 << 31);
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if (!(ocr_recvd & ocr_value))
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return 0;
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err = mmc_send_cmd(MMC_CMD2, argument, resp);
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if (err != 1)
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return err;
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if (mmc_card_cur->card_type == MMC_CARD) {
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argument = mmc_card_cur->RCA << 16;
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err = mmc_send_cmd(MMC_CMD3, argument, resp);
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if (err != 1)
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return err;
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} else {
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argument = 0x00000000;
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err = mmc_send_cmd(MMC_SDCMD3, argument, resp);
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if (err != 1)
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return err;
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mmc_card_cur->RCA = ((mmc_resp_r6 *) resp)->newpublishedrca;
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}
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OMAP_HSMMC_CON &= ~OD;
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OMAP_HSMMC_CON |= NOOPENDRAIN;
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return 1;
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}
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unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data,
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mmc_csd_reg_t *cur_csd)
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{
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mmc_extended_csd_reg_t ext_csd;
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unsigned int size, count, blk_len, blk_no, card_size, argument;
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unsigned char err;
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unsigned int resp[4];
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if (mmc_dev_data->mode == SECTOR_MODE) {
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if (mmc_dev_data->card_type == SD_CARD) {
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card_size =
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(((mmc_sd2_csd_reg_t *) cur_csd)->
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c_size_lsb & MMC_SD2_CSD_C_SIZE_LSB_MASK) |
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((((mmc_sd2_csd_reg_t *) cur_csd)->
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c_size_msb & MMC_SD2_CSD_C_SIZE_MSB_MASK)
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<< MMC_SD2_CSD_C_SIZE_MSB_OFFSET);
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mmc_dev_data->size = card_size * 1024;
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if (mmc_dev_data->size == 0)
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return 0;
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} else {
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argument = 0x00000000;
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err = mmc_send_cmd(MMC_CMD8, argument, resp);
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if (err != 1)
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return err;
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err = mmc_read_data((unsigned int *) &ext_csd);
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if (err != 1)
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return err;
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mmc_dev_data->size = ext_csd.sectorcount;
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if (mmc_dev_data->size == 0)
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mmc_dev_data->size = 8388608;
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}
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} else {
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if (cur_csd->c_size_mult >= 8)
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return 0;
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if (cur_csd->read_bl_len >= 12)
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return 0;
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/* Compute size */
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count = 1 << (cur_csd->c_size_mult + 2);
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card_size = (cur_csd->c_size_lsb & MMC_CSD_C_SIZE_LSB_MASK) |
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((cur_csd->c_size_msb & MMC_CSD_C_SIZE_MSB_MASK)
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<< MMC_CSD_C_SIZE_MSB_OFFSET);
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blk_no = (card_size + 1) * count;
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blk_len = 1 << cur_csd->read_bl_len;
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size = blk_no * blk_len;
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mmc_dev_data->size = size / MMCSD_SECTOR_SIZE;
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if (mmc_dev_data->size == 0)
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return 0;
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}
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return 1;
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}
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unsigned char omap_mmc_read_sect(unsigned int start_sec, unsigned int num_bytes,
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mmc_card_data *mmc_c,
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unsigned long *output_buf)
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{
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unsigned char err;
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unsigned int argument;
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unsigned int resp[4];
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unsigned int num_sec_val =
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(num_bytes + (MMCSD_SECTOR_SIZE - 1)) / MMCSD_SECTOR_SIZE;
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unsigned int sec_inc_val;
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if (num_sec_val == 0)
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return 1;
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if (mmc_c->mode == SECTOR_MODE) {
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argument = start_sec;
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sec_inc_val = 1;
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} else {
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argument = start_sec * MMCSD_SECTOR_SIZE;
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sec_inc_val = MMCSD_SECTOR_SIZE;
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}
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while (num_sec_val) {
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err = mmc_send_cmd(MMC_CMD17, argument, resp);
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if (err != 1)
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return err;
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err = mmc_read_data((unsigned int *) output_buf);
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if (err != 1)
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return err;
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output_buf += (MMCSD_SECTOR_SIZE / 4);
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argument += sec_inc_val;
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num_sec_val--;
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}
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return 1;
|
||||
}
|
||||
|
||||
unsigned char configure_mmc(mmc_card_data *mmc_card_cur)
|
||||
{
|
||||
unsigned char ret_val;
|
||||
unsigned int argument;
|
||||
unsigned int resp[4];
|
||||
unsigned int trans_clk, trans_fact, trans_unit, retries = 2;
|
||||
mmc_csd_reg_t Card_CSD;
|
||||
unsigned char trans_speed;
|
||||
|
||||
ret_val = mmc_init_setup();
|
||||
|
||||
if (ret_val != 1)
|
||||
return ret_val;
|
||||
|
||||
do {
|
||||
ret_val = mmc_detect_card(mmc_card_cur);
|
||||
retries--;
|
||||
} while ((retries > 0) && (ret_val != 1));
|
||||
|
||||
argument = mmc_card_cur->RCA << 16;
|
||||
ret_val = mmc_send_cmd(MMC_CMD9, argument, resp);
|
||||
if (ret_val != 1)
|
||||
return ret_val;
|
||||
|
||||
((unsigned int *) &Card_CSD)[3] = resp[3];
|
||||
((unsigned int *) &Card_CSD)[2] = resp[2];
|
||||
((unsigned int *) &Card_CSD)[1] = resp[1];
|
||||
((unsigned int *) &Card_CSD)[0] = resp[0];
|
||||
|
||||
if (mmc_card_cur->card_type == MMC_CARD)
|
||||
mmc_card_cur->version = Card_CSD.spec_vers;
|
||||
|
||||
trans_speed = Card_CSD.tran_speed;
|
||||
|
||||
ret_val = mmc_send_cmd(MMC_CMD4, MMC_DSR_DEFAULT << 16, resp);
|
||||
if (ret_val != 1)
|
||||
return ret_val;
|
||||
|
||||
trans_unit = trans_speed & MMC_CSD_TRAN_SPEED_UNIT_MASK;
|
||||
trans_fact = trans_speed & MMC_CSD_TRAN_SPEED_FACTOR_MASK;
|
||||
|
||||
if (trans_unit > MMC_CSD_TRAN_SPEED_UNIT_100MHZ)
|
||||
return 0;
|
||||
|
||||
if ((trans_fact < MMC_CSD_TRAN_SPEED_FACTOR_1_0) ||
|
||||
(trans_fact > MMC_CSD_TRAN_SPEED_FACTOR_8_0))
|
||||
return 0;
|
||||
|
||||
trans_unit >>= 0;
|
||||
trans_fact >>= 3;
|
||||
|
||||
trans_clk = mmc_transspeed_val[trans_fact - 1][trans_unit] * 2;
|
||||
ret_val = mmc_clock_config(CLK_MISC, trans_clk);
|
||||
|
||||
if (ret_val != 1)
|
||||
return ret_val;
|
||||
|
||||
argument = mmc_card_cur->RCA << 16;
|
||||
ret_val = mmc_send_cmd(MMC_CMD7_SELECT, argument, resp);
|
||||
if (ret_val != 1)
|
||||
return ret_val;
|
||||
|
||||
/* Configure the block length to 512 bytes */
|
||||
argument = MMCSD_SECTOR_SIZE;
|
||||
ret_val = mmc_send_cmd(MMC_CMD16, argument, resp);
|
||||
if (ret_val != 1)
|
||||
return ret_val;
|
||||
|
||||
/* get the card size in sectors */
|
||||
ret_val = mmc_read_cardsize(mmc_card_cur, &Card_CSD);
|
||||
if (ret_val != 1)
|
||||
return ret_val;
|
||||
|
||||
return 1;
|
||||
}
|
||||
unsigned long mmc_bread(int dev_num, unsigned long blknr, lbaint_t blkcnt,
|
||||
void *dst)
|
||||
{
|
||||
omap_mmc_read_sect(blknr, (blkcnt * MMCSD_SECTOR_SIZE), &cur_card_data,
|
||||
(unsigned long *) dst);
|
||||
return 1;
|
||||
}
|
||||
|
||||
int mmc_init(int verbose)
|
||||
{
|
||||
if (configure_mmc(&cur_card_data) != 1)
|
||||
return 1;
|
||||
|
||||
mmc_blk_dev.if_type = IF_TYPE_MMC;
|
||||
mmc_blk_dev.part_type = PART_TYPE_DOS;
|
||||
mmc_blk_dev.dev = 0;
|
||||
mmc_blk_dev.lun = 0;
|
||||
mmc_blk_dev.type = 0;
|
||||
|
||||
/* FIXME fill in the correct size (is set to 32MByte) */
|
||||
mmc_blk_dev.blksz = MMCSD_SECTOR_SIZE;
|
||||
mmc_blk_dev.lba = 0x10000;
|
||||
mmc_blk_dev.removable = 0;
|
||||
mmc_blk_dev.block_read = mmc_bread;
|
||||
|
||||
fat_register_device(&mmc_blk_dev, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmc_read(ulong src, uchar *dst, int size)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmc_write(uchar *src, ulong dst, int size)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmc2info(ulong addr)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
235
include/asm-arm/arch-omap3/mmc.h
Normal file
235
include/asm-arm/arch-omap3/mmc.h
Normal file
@ -0,0 +1,235 @@
|
||||
/*
|
||||
* (C) Copyright 2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation's version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef MMC_H
|
||||
#define MMC_H
|
||||
|
||||
#include "mmc_host_def.h"
|
||||
|
||||
/* Responses */
|
||||
#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
|
||||
#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
|
||||
#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK)
|
||||
#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK)
|
||||
#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK)
|
||||
#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK)
|
||||
#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
|
||||
#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
|
||||
#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
|
||||
|
||||
/* All supported commands */
|
||||
#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_CMD7_DESELECT (INDEX(7)| RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
|
||||
#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
|
||||
#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE)
|
||||
#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE)
|
||||
#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
|
||||
#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
|
||||
|
||||
#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16)
|
||||
#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16)
|
||||
#define MMC_DSR_DEFAULT 0x0404
|
||||
#define SD_CMD8_CHECK_PATTERN 0xAA
|
||||
#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8)
|
||||
|
||||
/* Clock Configurations and Macros */
|
||||
|
||||
#define MMC_CLOCK_REFERENCE 96
|
||||
#define MMC_RELATIVE_CARD_ADDRESS 0x1234
|
||||
#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80)
|
||||
#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400)
|
||||
#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1)
|
||||
#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u))
|
||||
|
||||
#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29)
|
||||
#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29)
|
||||
#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29)
|
||||
|
||||
#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30)
|
||||
#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30)
|
||||
#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30)
|
||||
|
||||
#define MMC_SD2_CSD_C_SIZE_LSB_MASK 0xFFFF
|
||||
#define MMC_SD2_CSD_C_SIZE_MSB_MASK 0x003F
|
||||
#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET 16
|
||||
#define MMC_CSD_C_SIZE_LSB_MASK 0x0003
|
||||
#define MMC_CSD_C_SIZE_MSB_MASK 0x03FF
|
||||
#define MMC_CSD_C_SIZE_MSB_OFFSET 2
|
||||
|
||||
#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0)
|
||||
#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3)
|
||||
#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0)
|
||||
#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3)
|
||||
#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3)
|
||||
|
||||
typedef struct {
|
||||
unsigned not_used:1;
|
||||
unsigned crc:7;
|
||||
unsigned ecc:2;
|
||||
unsigned file_format:2;
|
||||
unsigned tmp_write_protect:1;
|
||||
unsigned perm_write_protect:1;
|
||||
unsigned copy:1;
|
||||
unsigned file_format_grp:1;
|
||||
unsigned content_prot_app:1;
|
||||
unsigned reserved_1:4;
|
||||
unsigned write_bl_partial:1;
|
||||
unsigned write_bl_len:4;
|
||||
unsigned r2w_factor:3;
|
||||
unsigned default_ecc:2;
|
||||
unsigned wp_grp_enable:1;
|
||||
unsigned wp_grp_size:5;
|
||||
unsigned erase_grp_mult:5;
|
||||
unsigned erase_grp_size:5;
|
||||
unsigned c_size_mult:3;
|
||||
unsigned vdd_w_curr_max:3;
|
||||
unsigned vdd_w_curr_min:3;
|
||||
unsigned vdd_r_curr_max:3;
|
||||
unsigned vdd_r_curr_min:3;
|
||||
unsigned c_size_lsb:2;
|
||||
unsigned c_size_msb:10;
|
||||
unsigned reserved_2:2;
|
||||
unsigned dsr_imp:1;
|
||||
unsigned read_blk_misalign:1;
|
||||
unsigned write_blk_misalign:1;
|
||||
unsigned read_bl_partial:1;
|
||||
unsigned read_bl_len:4;
|
||||
unsigned ccc:12;
|
||||
unsigned tran_speed:8;
|
||||
unsigned nsac:8;
|
||||
unsigned taac:8;
|
||||
unsigned reserved_3:2;
|
||||
unsigned spec_vers:4;
|
||||
unsigned csd_structure:2;
|
||||
} mmc_csd_reg_t;
|
||||
|
||||
/* csd for sd2.0 */
|
||||
typedef struct {
|
||||
unsigned not_used:1;
|
||||
unsigned crc:7;
|
||||
unsigned reserved_1:2;
|
||||
unsigned file_format:2;
|
||||
unsigned tmp_write_protect:1;
|
||||
unsigned perm_write_protect:1;
|
||||
unsigned copy:1;
|
||||
unsigned file_format_grp:1;
|
||||
unsigned reserved_2:5;
|
||||
unsigned write_bl_partial:1;
|
||||
unsigned write_bl_len:4;
|
||||
unsigned r2w_factor:3;
|
||||
unsigned reserved_3:2;
|
||||
unsigned wp_grp_enable:1;
|
||||
unsigned wp_grp_size:7;
|
||||
unsigned sector_size:7;
|
||||
unsigned erase_blk_len:1;
|
||||
unsigned reserved_4:1;
|
||||
unsigned c_size_lsb:16;
|
||||
unsigned c_size_msb:6;
|
||||
unsigned reserved_5:6;
|
||||
unsigned dsr_imp:1;
|
||||
unsigned read_blk_misalign:1;
|
||||
unsigned write_blk_misalign:1;
|
||||
unsigned read_bl_partial:1;
|
||||
unsigned read_bl_len:4;
|
||||
unsigned ccc:12;
|
||||
unsigned tran_speed:8;
|
||||
unsigned nsac:8;
|
||||
unsigned taac:8;
|
||||
unsigned reserved_6:6;
|
||||
unsigned csd_structure:2;
|
||||
} mmc_sd2_csd_reg_t;
|
||||
|
||||
/* extended csd - 512 bytes long */
|
||||
typedef struct {
|
||||
unsigned char reserved_1[181];
|
||||
unsigned char erasedmemorycontent;
|
||||
unsigned char reserved_2;
|
||||
unsigned char buswidthmode;
|
||||
unsigned char reserved_3;
|
||||
unsigned char highspeedinterfacetiming;
|
||||
unsigned char reserved_4;
|
||||
unsigned char powerclass;
|
||||
unsigned char reserved_5;
|
||||
unsigned char commandsetrevision;
|
||||
unsigned char reserved_6;
|
||||
unsigned char commandset;
|
||||
unsigned char extendedcsdrevision;
|
||||
unsigned char reserved_7;
|
||||
unsigned char csdstructureversion;
|
||||
unsigned char reserved_8;
|
||||
unsigned char cardtype;
|
||||
unsigned char reserved_9[3];
|
||||
unsigned char powerclass_52mhz_1_95v;
|
||||
unsigned char powerclass_26mhz_1_95v;
|
||||
unsigned char powerclass_52mhz_3_6v;
|
||||
unsigned char powerclass_26mhz_3_6v;
|
||||
unsigned char reserved_10;
|
||||
unsigned char minreadperf_4b_26mhz;
|
||||
unsigned char minwriteperf_4b_26mhz;
|
||||
unsigned char minreadperf_8b_26mhz_4b_52mhz;
|
||||
unsigned char minwriteperf_8b_26mhz_4b_52mhz;
|
||||
unsigned char minreadperf_8b_52mhz;
|
||||
unsigned char minwriteperf_8b_52mhz;
|
||||
unsigned char reserved_11;
|
||||
unsigned int sectorcount;
|
||||
unsigned char reserved_12[288];
|
||||
unsigned char supportedcommandsets;
|
||||
unsigned char reserved_13[7];
|
||||
} mmc_extended_csd_reg_t;
|
||||
|
||||
/* mmc sd responce */
|
||||
typedef struct {
|
||||
unsigned int ocr;
|
||||
} mmc_resp_r3;
|
||||
|
||||
typedef struct {
|
||||
unsigned short cardstatus;
|
||||
unsigned short newpublishedrca;
|
||||
} mmc_resp_r6;
|
||||
|
||||
extern mmc_card_data mmc_dev;
|
||||
|
||||
unsigned char mmc_lowlevel_init(void);
|
||||
unsigned char mmc_send_command(unsigned int cmd, unsigned int arg,
|
||||
unsigned int *response);
|
||||
unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd);
|
||||
unsigned char mmc_set_opendrain(unsigned char state);
|
||||
unsigned char mmc_read_data(unsigned int *output_buf);
|
||||
|
||||
#endif /* MMC_H */
|
||||
166
include/asm-arm/arch-omap3/mmc_host_def.h
Normal file
166
include/asm-arm/arch-omap3/mmc_host_def.h
Normal file
@ -0,0 +1,166 @@
|
||||
/*
|
||||
* (C) Copyright 2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation's version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef MMC_HOST_DEF_H
|
||||
#define MMC_HOST_DEF_H
|
||||
|
||||
/*
|
||||
* OMAP HSMMC register definitions
|
||||
*/
|
||||
#define OMAP_HSMMC_SYSCONFIG (*(unsigned int *) 0x4809C010)
|
||||
#define OMAP_HSMMC_SYSSTATUS (*(unsigned int *) 0x4809C014)
|
||||
#define OMAP_HSMMC_CON (*(unsigned int *) 0x4809C02C)
|
||||
#define OMAP_HSMMC_BLK (*(unsigned int *) 0x4809C104)
|
||||
#define OMAP_HSMMC_ARG (*(unsigned int *) 0x4809C108)
|
||||
#define OMAP_HSMMC_CMD (*(unsigned int *) 0x4809C10C)
|
||||
#define OMAP_HSMMC_RSP10 (*(unsigned int *) 0x4809C110)
|
||||
#define OMAP_HSMMC_RSP32 (*(unsigned int *) 0x4809C114)
|
||||
#define OMAP_HSMMC_RSP54 (*(unsigned int *) 0x4809C118)
|
||||
#define OMAP_HSMMC_RSP76 (*(unsigned int *) 0x4809C11C)
|
||||
#define OMAP_HSMMC_DATA (*(unsigned int *) 0x4809C120)
|
||||
#define OMAP_HSMMC_PSTATE (*(unsigned int *) 0x4809C124)
|
||||
#define OMAP_HSMMC_HCTL (*(unsigned int *) 0x4809C128)
|
||||
#define OMAP_HSMMC_SYSCTL (*(unsigned int *) 0x4809C12C)
|
||||
#define OMAP_HSMMC_STAT (*(unsigned int *) 0x4809C130)
|
||||
#define OMAP_HSMMC_IE (*(unsigned int *) 0x4809C134)
|
||||
#define OMAP_HSMMC_CAPA (*(unsigned int *) 0x4809C140)
|
||||
|
||||
/* T2 Register definitions */
|
||||
#define CONTROL_DEV_CONF0 (*(unsigned int *) 0x48002274)
|
||||
#define CONTROL_PBIAS_LITE (*(unsigned int *) 0x48002520)
|
||||
|
||||
/*
|
||||
* OMAP HS MMC Bit definitions
|
||||
*/
|
||||
#define MMC_SOFTRESET (0x1 << 1)
|
||||
#define RESETDONE (0x1 << 0)
|
||||
#define NOOPENDRAIN (0x0 << 0)
|
||||
#define OPENDRAIN (0x1 << 0)
|
||||
#define OD (0x1 << 0)
|
||||
#define INIT_NOINIT (0x0 << 1)
|
||||
#define INIT_INITSTREAM (0x1 << 1)
|
||||
#define HR_NOHOSTRESP (0x0 << 2)
|
||||
#define STR_BLOCK (0x0 << 3)
|
||||
#define MODE_FUNC (0x0 << 4)
|
||||
#define DW8_1_4BITMODE (0x0 << 5)
|
||||
#define MIT_CTO (0x0 << 6)
|
||||
#define CDP_ACTIVEHIGH (0x0 << 7)
|
||||
#define WPP_ACTIVEHIGH (0x0 << 8)
|
||||
#define RESERVED_MASK (0x3 << 9)
|
||||
#define CTPL_MMC_SD (0x0 << 11)
|
||||
#define BLEN_512BYTESLEN (0x200 << 0)
|
||||
#define NBLK_STPCNT (0x0 << 16)
|
||||
#define DE_DISABLE (0x0 << 0)
|
||||
#define BCE_DISABLE (0x0 << 1)
|
||||
#define ACEN_DISABLE (0x0 << 2)
|
||||
#define DDIR_OFFSET (4)
|
||||
#define DDIR_MASK (0x1 << 4)
|
||||
#define DDIR_WRITE (0x0 << 4)
|
||||
#define DDIR_READ (0x1 << 4)
|
||||
#define MSBS_SGLEBLK (0x0 << 5)
|
||||
#define RSP_TYPE_OFFSET (16)
|
||||
#define RSP_TYPE_MASK (0x3 << 16)
|
||||
#define RSP_TYPE_NORSP (0x0 << 16)
|
||||
#define RSP_TYPE_LGHT136 (0x1 << 16)
|
||||
#define RSP_TYPE_LGHT48 (0x2 << 16)
|
||||
#define RSP_TYPE_LGHT48B (0x3 << 16)
|
||||
#define CCCE_NOCHECK (0x0 << 19)
|
||||
#define CCCE_CHECK (0x1 << 19)
|
||||
#define CICE_NOCHECK (0x0 << 20)
|
||||
#define CICE_CHECK (0x1 << 20)
|
||||
#define DP_OFFSET (21)
|
||||
#define DP_MASK (0x1 << 21)
|
||||
#define DP_NO_DATA (0x0 << 21)
|
||||
#define DP_DATA (0x1 << 21)
|
||||
#define CMD_TYPE_NORMAL (0x0 << 22)
|
||||
#define INDEX_OFFSET (24)
|
||||
#define INDEX_MASK (0x3f << 24)
|
||||
#define INDEX(i) (i << 24)
|
||||
#define DATI_MASK (0x1 << 1)
|
||||
#define DATI_CMDDIS (0x1 << 1)
|
||||
#define DTW_1_BITMODE (0x0 << 1)
|
||||
#define DTW_4_BITMODE (0x1 << 1)
|
||||
#define SDBP_PWROFF (0x0 << 8)
|
||||
#define SDBP_PWRON (0x1 << 8)
|
||||
#define SDVS_1V8 (0x5 << 9)
|
||||
#define SDVS_3V0 (0x6 << 9)
|
||||
#define ICE_MASK (0x1 << 0)
|
||||
#define ICE_STOP (0x0 << 0)
|
||||
#define ICS_MASK (0x1 << 1)
|
||||
#define ICS_NOTREADY (0x0 << 1)
|
||||
#define ICE_OSCILLATE (0x1 << 0)
|
||||
#define CEN_MASK (0x1 << 2)
|
||||
#define CEN_DISABLE (0x0 << 2)
|
||||
#define CEN_ENABLE (0x1 << 2)
|
||||
#define CLKD_OFFSET (6)
|
||||
#define CLKD_MASK (0x3FF << 6)
|
||||
#define DTO_MASK (0xF << 16)
|
||||
#define DTO_15THDTO (0xE << 16)
|
||||
#define SOFTRESETALL (0x1 << 24)
|
||||
#define CC_MASK (0x1 << 0)
|
||||
#define TC_MASK (0x1 << 1)
|
||||
#define BWR_MASK (0x1 << 4)
|
||||
#define BRR_MASK (0x1 << 5)
|
||||
#define ERRI_MASK (0x1 << 15)
|
||||
#define IE_CC (0x01 << 0)
|
||||
#define IE_TC (0x01 << 1)
|
||||
#define IE_BWR (0x01 << 4)
|
||||
#define IE_BRR (0x01 << 5)
|
||||
#define IE_CTO (0x01 << 16)
|
||||
#define IE_CCRC (0x01 << 17)
|
||||
#define IE_CEB (0x01 << 18)
|
||||
#define IE_CIE (0x01 << 19)
|
||||
#define IE_DTO (0x01 << 20)
|
||||
#define IE_DCRC (0x01 << 21)
|
||||
#define IE_DEB (0x01 << 22)
|
||||
#define IE_CERR (0x01 << 28)
|
||||
#define IE_BADA (0x01 << 29)
|
||||
|
||||
#define VS30_3V0SUP (1 << 25)
|
||||
#define VS18_1V8SUP (1 << 26)
|
||||
|
||||
/* Driver definitions */
|
||||
#define MMCSD_SECTOR_SIZE 512
|
||||
#define MMC_CARD 0
|
||||
#define SD_CARD 1
|
||||
#define BYTE_MODE 0
|
||||
#define SECTOR_MODE 1
|
||||
#define CLK_INITSEQ 0
|
||||
#define CLK_400KHZ 1
|
||||
#define CLK_MISC 2
|
||||
|
||||
typedef struct {
|
||||
unsigned int card_type;
|
||||
unsigned int version;
|
||||
unsigned int mode;
|
||||
unsigned int size;
|
||||
unsigned int RCA;
|
||||
} mmc_card_data;
|
||||
|
||||
#define mmc_reg_out(addr, mask, val)\
|
||||
(addr) = (((addr)) & (~(mask))) | ((val) & (mask));
|
||||
#define mmc_reg_out(addr, mask, val)\
|
||||
(addr) = (((addr)) & (~(mask))) | ((val) & (mask));
|
||||
|
||||
#endif /* MMC_HOST_DEF_H */
|
||||
Loading…
Reference in New Issue
Block a user