Merge git://git.denx.de/u-boot-net

arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -612,6 +612,29 @@ int setup_chip_volt(void)
 	return 0;
 }
 
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void)
+{
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	u32 ecccr2;
+
+	out_be32(&scfg->pfeasbcr,
+		 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
+	out_be32(&scfg->pfebsbcr,
+		 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
+
+	/* CCI-400 QoS settings for PFE */
+	out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
+		 | SCFG_WR_QOS1_PFE2_QOS));
+	out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
+		 | SCFG_RD_QOS1_PFE2_QOS));
+
+	ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
+	out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
+		 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
+}
+#endif
+
 void fsl_lsch2_early_init_f(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h

@@ -82,6 +82,11 @@
 #define QSPI0_BASE_ADDR				(CONFIG_SYS_IMMR + 0x00550000)
 #define DSPI1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01100000)
 
+#define GPIO1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1300000)
+#define GPIO2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1310000)
+#define GPIO3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1320000)
+#define GPIO4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1330000)
+
 #define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
 
 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
@@ -200,6 +205,8 @@ struct sys_info {
 
 /* Device Configuration and Pin Control */
 #define DCFG_DCSR_PORCR1		0x0
+#define DCFG_DCSR_ECCCR2		0x524
+#define DISABLE_PFE_ECC			BIT(13)
 
 struct ccsr_gur {
 	u32     porsr1;         /* POR status 1 */
@@ -390,6 +397,29 @@ struct ccsr_gur {
 #define SCFG_SNPCNFGCR_SATARDSNP	0x00800000
 #define SCFG_SNPCNFGCR_SATAWRSNP	0x00400000
 
+/* RGMIIPCR bit definitions*/
+#define SCFG_RGMIIPCR_EN_AUTO		BIT(3)
+#define SCFG_RGMIIPCR_SETSP_1000M	BIT(2)
+#define SCFG_RGMIIPCR_SETSP_100M	0
+#define SCFG_RGMIIPCR_SETSP_10M		BIT(1)
+#define SCFG_RGMIIPCR_SETFD		BIT(0)
+
+/* PFEASBCR bit definitions */
+#define SCFG_PFEASBCR_ARCACHE0		BIT(31)
+#define SCFG_PFEASBCR_AWCACHE0		BIT(30)
+#define SCFG_PFEASBCR_ARCACHE1		BIT(29)
+#define SCFG_PFEASBCR_AWCACHE1		BIT(28)
+#define SCFG_PFEASBCR_ARSNP		BIT(27)
+#define SCFG_PFEASBCR_AWSNP		BIT(26)
+
+/* WR_QoS1 PFE bit definitions */
+#define SCFG_WR_QOS1_PFE1_QOS		GENMASK(27, 24)
+#define SCFG_WR_QOS1_PFE2_QOS		GENMASK(23, 20)
+
+/* RD_QoS1 PFE bit definitions */
+#define SCFG_RD_QOS1_PFE1_QOS		GENMASK(27, 24)
+#define SCFG_RD_QOS1_PFE2_QOS		GENMASK(23, 20)
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
 	u8 res_000[0x100-0x000];
@@ -407,7 +437,12 @@ struct ccsr_scfg {
 	u8 res_140[0x158-0x140];
 	u32 altcbar;
 	u32 qspi_cfg;
-	u8 res_160[0x180-0x160];
+	u8 res_160[0x164 - 0x160];
+	u32 wr_qos1;
+	u32 wr_qos2;
+	u32 rd_qos1;
+	u32 rd_qos2;
+	u8 res_174[0x180 - 0x174];
 	u32 dmamcr;
 	u8 res_184[0x188-0x184];
 	u32 gic_align;
@@ -438,7 +473,21 @@ struct ccsr_scfg {
 	u32 usb_refclk_selcr1;
 	u32 usb_refclk_selcr2;
 	u32 usb_refclk_selcr3;
-	u8 res_424[0x600-0x424];
+	u8 res_424[0x434 - 0x424];
+	u32 rgmiipcr;
+	u32 res_438;
+	u32 rgmiipsr;
+	u32 pfepfcssr1;
+	u32 pfeintencr1;
+	u32 pfepfcssr2;
+	u32 pfeintencr2;
+	u32 pfeerrcr;
+	u32 pfeeerrintencr;
+	u32 pfeasbcr;
+	u32 pfebsbcr;
+	u8 res_460[0x484 - 0x460];
+	u32 mdioselcr;
+	u8 res_468[0x600 - 0x488];
 	u32 scratchrw[4];
 	u8 res_610[0x680-0x610];
 	u32 corebcr;
@@ -591,6 +640,16 @@ struct ccsr_serdes {
 	u8	res_19a0[0x2000-0x19a0];	/* from 0x19a0 to 0x1fff */
 };
 
+struct ccsr_gpio {
+	u32	gpdir;
+	u32	gpodr;
+	u32	gpdat;
+	u32	gpier;
+	u32	gpimr;
+	u32	gpicr;
+	u32	gpibe;
+};
+
 /* MMU 500 */
 #define SMMU_SCR0			(SMMU_BASE + 0x0)
 #define SMMU_SCR1			(SMMU_BASE + 0x4)

arch/arm/include/asm/arch-fsl-layerscape/ns_access.h

@@ -26,6 +26,7 @@ enum csu_cslx_ind {
 	CSU_CSLX_PCIE3_IO,
 	CSU_CSLX_USB3 = 20,
 	CSU_CSLX_USB2,
+	CSU_CSLX_PFE = 23,
 	CSU_CSLX_SERDES = 32,
 	CSU_CSLX_QDMA,
 	CSU_CSLX_LPUART2,
@@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = {
 	 {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
 	 {CSU_CSLX_USB3, CSU_ALL_RW},
 	 {CSU_CSLX_USB2, CSU_ALL_RW},
+	 {CSU_CSLX_PFE, CSU_ALL_RW},
 	 {CSU_CSLX_SERDES, CSU_ALL_RW},
 	 {CSU_CSLX_QDMA, CSU_ALL_RW},
 	 {CSU_CSLX_LPUART2, CSU_ALL_RW},

arch/arm/include/asm/arch-fsl-layerscape/soc.h

@@ -127,6 +127,9 @@ void fsl_lsch2_early_init_f(void);
 int setup_chip_volt(void);
 /* Setup core vdd in unit mV */
 int board_setup_core_volt(u32 vdd);
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void);
+#endif
 #endif
 
 void cpu_name(char *name);