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odroid: fix g2d sclk rate

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G2D core should be provided 200MHz clock rate.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Joonyoung Shim
2015-01-23 17:30:07 +09:00
committed by Minkyu Kang
parent de3b251870
commit b00f8edb5a
1 changed files with 2 additions and 2 deletions
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4
board/samsung/odroid/odroid.c
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@@ -248,12 +248,12 @@ static void board_clock_init(void)
* MOUTc2c = 800 Mhz * MOUTc2c = 800 Mhz
* MOUTpwi = 108 MHz * MOUTpwi = 108 MHz
* *
* sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3)
* sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
* aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
* sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
*/ */
set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) |
C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
clrsetbits_le32(&clk->div_dmc1, clr, set); clrsetbits_le32(&clk->div_dmc1, clr, set);