Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
This commit is contained in:
Wolfgang Denk
commit
afe3848b79
@ -2249,17 +2249,26 @@ static void program_memory_queue(unsigned long *dimm_populated,
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}
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}
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_460SX)
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/*
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* Enable high bandwidth access on 460EX/GT.
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* This should/could probably be done on other
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* PPC's too, like 440SPe.
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* Enable high bandwidth access
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* This is currently not used, but with this setup
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* it is possible to use it later on in e.g. the Linux
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* EMAC driver for performance gain.
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*/
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mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
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mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
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/*
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* Set optimal value for Memory Queue HB/LL Configuration registers
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*/
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mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
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SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
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mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
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SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
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mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
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#endif
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}
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@ -638,7 +638,7 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
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switch (port) {
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case 0:
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SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230);
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SDR_WRITE(PESDR0_L0DRV, 0x00000136);
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SDR_WRITE(PESDR0_L0DRV, 0x00000130);
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SDR_WRITE(PESDR0_L0CLK, 0x00000006);
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SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000);
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@ -649,10 +649,10 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
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SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230);
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SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230);
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SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230);
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SDR_WRITE(PESDR1_L0DRV, 0x00000136);
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SDR_WRITE(PESDR1_L1DRV, 0x00000136);
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SDR_WRITE(PESDR1_L2DRV, 0x00000136);
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SDR_WRITE(PESDR1_L3DRV, 0x00000136);
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SDR_WRITE(PESDR1_L0DRV, 0x00000130);
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SDR_WRITE(PESDR1_L1DRV, 0x00000130);
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SDR_WRITE(PESDR1_L2DRV, 0x00000130);
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SDR_WRITE(PESDR1_L3DRV, 0x00000130);
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SDR_WRITE(PESDR1_L0CLK, 0x00000006);
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SDR_WRITE(PESDR1_L1CLK, 0x00000006);
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SDR_WRITE(PESDR1_L2CLK, 0x00000006);
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@ -301,6 +301,19 @@ cpu_init_f (void)
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val |= 0x400;
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mtsdr(SDR0_USB2HOST_CFG, val);
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#endif /* CONFIG_460EX */
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#if defined(CONFIG_405EX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_460SX)
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/*
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* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
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*/
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mtdcr(plb0_acr, (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) |
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plb0_acr_rdp_4deep);
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mtdcr(plb1_acr, (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) |
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plb1_acr_rdp_4deep);
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#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
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}
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/*
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@ -259,23 +259,39 @@
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/*
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* Memory queue defines
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*/
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#define SDRAMQ_DCR_BASE 0x040
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#define SDRAMQ_DCR_BASE 0x040
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#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */
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#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */
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#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */
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#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */
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#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */
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#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
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#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
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#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
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#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */
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#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */
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#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
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#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
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#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */
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#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */
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#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
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#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */
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#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */
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#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */
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#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */
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#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */
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#define SDRAM_CONF1HB_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */
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#define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */
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#define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */
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#define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */
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#define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */
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#define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */
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#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
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#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
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#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
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#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */
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#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */
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#define SDRAM_CONF1LL_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */
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#define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */
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#define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */
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#define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */
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#define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */
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#define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */
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#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
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#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
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#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */
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#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */
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#define SDRAM_CONFPATHB_TPEN 0x08000000 /* Transaction Passing Enable - Bit 4 */
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#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
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#if !defined(CONFIG_405EX)
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/*
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@ -341,53 +341,6 @@
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#define PLB4_ACR_WRP (0x80000000 >> 7)
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/* Nebula PLB4 Arbiter - PowerPC440EP */
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#define PLB_ARBITER_BASE 0x80
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#define plb0_revid (PLB_ARBITER_BASE+ 0x00)
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#define plb0_acr (PLB_ARBITER_BASE+ 0x01)
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#define plb0_acr_ppm_mask 0xF0000000
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#define plb0_acr_ppm_fixed 0x00000000
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#define plb0_acr_ppm_fair 0xD0000000
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#define plb0_acr_hbu_mask 0x08000000
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#define plb0_acr_hbu_disabled 0x00000000
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#define plb0_acr_hbu_enabled 0x08000000
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#define plb0_acr_rdp_mask 0x06000000
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#define plb0_acr_rdp_disabled 0x00000000
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#define plb0_acr_rdp_2deep 0x02000000
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#define plb0_acr_rdp_3deep 0x04000000
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#define plb0_acr_rdp_4deep 0x06000000
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#define plb0_acr_wrp_mask 0x01000000
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#define plb0_acr_wrp_disabled 0x00000000
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#define plb0_acr_wrp_2deep 0x01000000
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#define plb0_besrl (PLB_ARBITER_BASE+ 0x02)
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#define plb0_besrh (PLB_ARBITER_BASE+ 0x03)
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#define plb0_bearl (PLB_ARBITER_BASE+ 0x04)
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#define plb0_bearh (PLB_ARBITER_BASE+ 0x05)
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#define plb0_ccr (PLB_ARBITER_BASE+ 0x08)
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#define plb1_acr (PLB_ARBITER_BASE+ 0x09)
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#define plb1_acr_ppm_mask 0xF0000000
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#define plb1_acr_ppm_fixed 0x00000000
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#define plb1_acr_ppm_fair 0xD0000000
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#define plb1_acr_hbu_mask 0x08000000
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#define plb1_acr_hbu_disabled 0x00000000
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#define plb1_acr_hbu_enabled 0x08000000
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#define plb1_acr_rdp_mask 0x06000000
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#define plb1_acr_rdp_disabled 0x00000000
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#define plb1_acr_rdp_2deep 0x02000000
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#define plb1_acr_rdp_3deep 0x04000000
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#define plb1_acr_rdp_4deep 0x06000000
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#define plb1_acr_wrp_mask 0x01000000
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#define plb1_acr_wrp_disabled 0x00000000
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#define plb1_acr_wrp_2deep 0x01000000
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#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A)
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#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B)
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#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
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#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
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/* Pin Function Control Register 1 */
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#define SDR0_PFC1 0x4101
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#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
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@ -46,6 +46,62 @@
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#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
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#endif
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/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
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#if defined(CONFIG_405EX) || \
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defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
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defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_460SX)
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#define PLB_ARBITER_BASE 0x80
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#define plb0_revid (PLB_ARBITER_BASE + 0x00)
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#define plb0_acr (PLB_ARBITER_BASE + 0x01)
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#define plb0_acr_ppm_mask 0xF0000000
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#define plb0_acr_ppm_fixed 0x00000000
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#define plb0_acr_ppm_fair 0xD0000000
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#define plb0_acr_hbu_mask 0x08000000
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#define plb0_acr_hbu_disabled 0x00000000
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#define plb0_acr_hbu_enabled 0x08000000
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#define plb0_acr_rdp_mask 0x06000000
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#define plb0_acr_rdp_disabled 0x00000000
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#define plb0_acr_rdp_2deep 0x02000000
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#define plb0_acr_rdp_3deep 0x04000000
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#define plb0_acr_rdp_4deep 0x06000000
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#define plb0_acr_wrp_mask 0x01000000
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#define plb0_acr_wrp_disabled 0x00000000
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#define plb0_acr_wrp_2deep 0x01000000
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#define plb0_besrl (PLB_ARBITER_BASE + 0x02)
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#define plb0_besrh (PLB_ARBITER_BASE + 0x03)
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#define plb0_bearl (PLB_ARBITER_BASE + 0x04)
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#define plb0_bearh (PLB_ARBITER_BASE + 0x05)
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#define plb0_ccr (PLB_ARBITER_BASE + 0x08)
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#define plb1_acr (PLB_ARBITER_BASE + 0x09)
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#define plb1_acr_ppm_mask 0xF0000000
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#define plb1_acr_ppm_fixed 0x00000000
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#define plb1_acr_ppm_fair 0xD0000000
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#define plb1_acr_hbu_mask 0x08000000
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#define plb1_acr_hbu_disabled 0x00000000
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#define plb1_acr_hbu_enabled 0x08000000
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#define plb1_acr_rdp_mask 0x06000000
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#define plb1_acr_rdp_disabled 0x00000000
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#define plb1_acr_rdp_2deep 0x02000000
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#define plb1_acr_rdp_3deep 0x04000000
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#define plb1_acr_rdp_4deep 0x06000000
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#define plb1_acr_wrp_mask 0x01000000
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#define plb1_acr_wrp_disabled 0x00000000
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#define plb1_acr_wrp_2deep 0x01000000
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#define plb1_besrl (PLB_ARBITER_BASE + 0x0A)
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#define plb1_besrh (PLB_ARBITER_BASE + 0x0B)
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#define plb1_bearl (PLB_ARBITER_BASE + 0x0C)
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#define plb1_bearh (PLB_ARBITER_BASE + 0x0D)
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#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
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#if defined(CONFIG_440)
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/*
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* Enable long long (%ll ...) printf format on 440 PPC's since most of
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