ARM: s3c44b0: remove remainders of dead board
Because commit 5dc5f36 removed B2 board support, arch/arm/cpu/s3c44b0/* and arch/arm/include/asm/arch-s3c44b0/* are not necessary anymore. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Andrea Scian <andrea.scian@dave-tech.it>
This commit is contained in:
Masahiro Yamada
Albert ARIBAUD
parent
771f74c3d3
commit
aeef2b090d
1
README
1
README
@ -144,7 +144,6 @@ Directory Hierarchy:
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/arm1136 Files specific to ARM 1136 CPUs
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/ixp Files specific to Intel XScale IXP CPUs
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/pxa Files specific to Intel XScale PXA CPUs
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/s3c44b0 Files specific to Samsung S3C44B0 CPUs
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/sa1100 Files specific to Intel StrongARM SA1100 CPUs
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/lib Architecture specific library files
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/avr32 Files generic to AVR32 architecture
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@ -1,34 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(CPU).o
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START = start.o
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COBJS += cache.o
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COBJS += cpu.o
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COBJS += timer.o
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SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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START := $(addprefix $(obj),$(START))
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all: $(obj).depend $(START) $(LIB)
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$(LIB): $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1,74 +0,0 @@
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/*
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* (C) Copyright 2004
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* DAVE Srl
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* http://www.dave-tech.it
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* http://www.wawnet.biz
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* mailto:info@wawnet.biz
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/hardware.h>
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static void s3c44b0_flush_cache(void)
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{
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volatile int i;
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/* flush cycle */
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for(i=0x10002000;i<0x10004800;i+=16)
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{
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*((int *)i)=0x0;
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}
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}
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void icache_enable (void)
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{
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ulong reg;
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s3c44b0_flush_cache();
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/*
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Init cache
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Non-cacheable area (everything outside RAM)
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0x0000:0000 - 0x0C00:0000
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*/
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NCACHBE0 = 0xC0000000;
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NCACHBE1 = 0x00000000;
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/*
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Enable chache
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*/
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reg = SYSCFG;
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reg |= 0x00000006; /* 8kB */
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SYSCFG = reg;
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}
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void icache_disable (void)
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{
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ulong reg;
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reg = SYSCFG;
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reg &= ~0x00000006; /* 8kB */
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SYSCFG = reg;
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}
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int icache_status (void)
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{
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return 0;
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}
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void dcache_enable (void)
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{
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icache_enable();
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}
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void dcache_disable (void)
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{
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icache_disable();
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}
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int dcache_status (void)
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{
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return dcache_status();
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}
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@ -1,18 +0,0 @@
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#
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# (C) Copyright 2002
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# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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# Marius Groeger <mgroeger@sysgo.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
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PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float
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# =========================================================================
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#
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# Supply options according to compiler version
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#
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# ========================================================================
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PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
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PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
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@ -1,58 +0,0 @@
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/*
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* (C) Copyright 2004
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* DAVE Srl
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* http://www.dave-tech.it
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* http://www.wawnet.biz
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* mailto:info@wawnet.biz
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* S3C44B0 CPU specific code
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/hardware.h>
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int arch_cpu_init (void)
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{
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icache_enable();
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return 0;
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}
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int cleanup_before_linux (void)
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{
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/*
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cache memory should be enabled before calling
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Linux to make the kernel uncompression faster
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*/
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icache_enable();
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disable_interrupts ();
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return 0;
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}
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void reset_cpu (ulong addr)
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{
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/*
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reset the cpu using watchdog
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*/
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/* Disable the watchdog.*/
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WTCON&=~(1<<5);
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/* set the timeout value to a short time... */
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WTCNT = 0x1;
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/* Enable the watchdog. */
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WTCON|=1;
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WTCON|=(1<<5);
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while(1) {
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/*NOP*/
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}
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}
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@ -1,228 +0,0 @@
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/*
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* Startup Code for S3C44B0 CPU-core
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*
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* (C) Copyright 2004
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* DAVE Srl
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*
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* http://www.dave-tech.it
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* http://www.wawnet.biz
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* mailto:info@wawnet.biz
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <version.h>
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/*
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* Jump vector table
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*/
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.globl _start
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_start: b reset
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add pc, pc, #0x0c000000
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add pc, pc, #0x0c000000
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add pc, pc, #0x0c000000
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add pc, pc, #0x0c000000
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add pc, pc, #0x0c000000
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add pc, pc, #0x0c000000
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add pc, pc, #0x0c000000
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* relocate u-boot to ram
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* setup stack
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* jump to second stage
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*
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*************************************************************************
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*/
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.globl _TEXT_BASE
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_TEXT_BASE:
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
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.word CONFIG_SPL_TEXT_BASE
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#else
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.word CONFIG_SYS_TEXT_BASE
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#endif
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/*
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* These are defined in the board-specific linker script.
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* Subtracting _start from them lets the linker put their
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* relative position in the executable instead of leaving
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* them null.
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*/
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.globl _bss_start_ofs
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_bss_start_ofs:
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.word __bss_start - _start
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.globl _bss_end_ofs
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_bss_end_ofs:
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.word __bss_end - _start
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.globl _end_ofs
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_end_ofs:
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.word _end - _start
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#ifdef CONFIG_USE_IRQ
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/* IRQ stack memory (calculated at run-time) */
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.globl IRQ_STACK_START
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IRQ_STACK_START:
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.word 0x0badc0de
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/* IRQ stack memory (calculated at run-time) */
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.globl FIQ_STACK_START
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FIQ_STACK_START:
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.word 0x0badc0de
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#endif
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/* IRQ stack memory (calculated at run-time) + 8 bytes */
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.globl IRQ_STACK_START_IN
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IRQ_STACK_START_IN:
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.word 0x0badc0de
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/*
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* the actual reset code
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*/
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0,cpsr
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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/*
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit
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/*
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* before relocating, we have to setup RAM timing
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* because memory timing is board-dependend, you will
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* find a lowlevel_init.S in your board directory.
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*/
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bl lowlevel_init
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#endif
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bl _main
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/*------------------------------------------------------------------------------*/
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.globl c_runtime_cpu_setup
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c_runtime_cpu_setup:
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bx lr
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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#define INTCON (0x01c00000+0x200000)
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#define INTMSK (0x01c00000+0x20000c)
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#define LOCKTIME (0x01c00000+0x18000c)
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#define PLLCON (0x01c00000+0x180000)
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#define CLKCON (0x01c00000+0x180004)
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#define WTCON (0x01c00000+0x130000)
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cpu_init_crit:
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/* disable watch dog */
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ldr r0, =WTCON
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ldr r1, =0x0
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str r1, [r0]
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/*
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* mask all IRQs by clearing all bits in the INTMRs
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*/
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ldr r1,=INTMSK
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ldr r0, =0x03fffeff
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str r0, [r1]
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ldr r1, =INTCON
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ldr r0, =0x05
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str r0, [r1]
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/* Set Clock Control Register */
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ldr r1, =LOCKTIME
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ldrb r0, =800
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strb r0, [r1]
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ldr r1, =PLLCON
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#if CONFIG_S3C44B0_CLOCK_SPEED==66
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ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
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#elif CONFIG_S3C44B0_CLOCK_SPEED==75
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ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
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#else
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# error CONFIG_S3C44B0_CLOCK_SPEED undefined
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#endif
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str r0, [r1]
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ldr r1,=CLKCON
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ldr r0, =0x7ff8
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str r0, [r1]
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mov pc, lr
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/*************************************************/
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/* interrupt vectors */
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/*************************************************/
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real_vectors:
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b reset
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b undefined_instruction
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b software_interrupt
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b prefetch_abort
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b data_abort
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b not_used
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b irq
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b fiq
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/*************************************************/
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undefined_instruction:
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mov r6, #3
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b reset
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software_interrupt:
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mov r6, #4
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b reset
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prefetch_abort:
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mov r6, #5
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b reset
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data_abort:
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mov r6, #6
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b reset
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not_used:
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/* we *should* never reach this */
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mov r6, #7
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b reset
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irq:
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mov r6, #8
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b reset
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fiq:
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mov r6, #9
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b reset
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@ -1,102 +0,0 @@
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/*
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* (C) Copyright 2004
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* DAVE Srl
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* http://www.dave-tech.it
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* http://www.wawnet.biz
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* mailto:info@wawnet.biz
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/hardware.h>
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/* we always count down the max. */
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#define TIMER_LOAD_VAL 0xffff
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/* macro to read the 16 bit timer */
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#define READ_TIMER (TCNTO1 & 0xffff)
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#ifdef CONFIG_USE_IRQ
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#error CONFIG_USE_IRQ NOT supported
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#endif
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static ulong timestamp;
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static ulong lastdec;
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int timer_init (void)
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{
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TCFG0 = 0x000000E9;
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TCFG1 = 0x00000004;
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TCON = 0x00000900;
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TCNTB1 = TIMER_LOAD_VAL;
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TCMPB1 = 0;
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TCON = 0x00000B00;
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TCON = 0x00000900;
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lastdec = TCNTB1 = TIMER_LOAD_VAL;
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timestamp = 0;
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return 0;
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}
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/*
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* timer without interrupts
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*/
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ulong get_timer (ulong base)
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{
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return get_timer_masked () - base;
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}
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void __udelay (unsigned long usec)
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{
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ulong tmo;
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tmo = usec / 1000;
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tmo *= CONFIG_SYS_HZ;
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tmo /= 8;
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tmo += get_timer (0);
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while (get_timer_masked () < tmo)
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/*NOP*/;
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}
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ulong get_timer_masked (void)
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{
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ulong now = READ_TIMER;
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if (lastdec >= now) {
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/* normal mode */
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timestamp += lastdec - now;
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} else {
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/* we have an overflow ... */
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timestamp += lastdec + TIMER_LOAD_VAL - now;
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}
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lastdec = now;
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return timestamp;
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}
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void udelay_masked (unsigned long usec)
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{
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ulong tmo;
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ulong endtime;
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signed long diff;
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if (usec >= 1000) {
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tmo = usec / 1000;
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tmo *= CONFIG_SYS_HZ;
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tmo /= 8;
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} else {
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tmo = usec * CONFIG_SYS_HZ;
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tmo /= (1000*8);
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}
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endtime = get_timer(0) + tmo;
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do {
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ulong now = get_timer_masked ();
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diff = endtime - now;
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} while (diff >= 0);
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}
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@ -1,281 +0,0 @@
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/********************************************************/
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/* */
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/* Samsung S3C44B0 */
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/* tpu <tapu@371.net> */
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/* */
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/********************************************************/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#define REGBASE 0x01c00000
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#define REGL(addr) (*(volatile unsigned int *)(REGBASE+addr))
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#define REGW(addr) (*(volatile unsigned short *)(REGBASE+addr))
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#define REGB(addr) (*(volatile unsigned char *)(REGBASE+addr))
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/*****************************/
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/* CPU Wrapper Registers */
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/*****************************/
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#define SYSCFG REGL(0x000000)
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#define NCACHBE0 REGL(0x000004)
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#define NCACHBE1 REGL(0x000008)
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#define SBUSCON REGL(0x040000)
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/************************************/
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/* Memory Controller Registers */
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/************************************/
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#define BWSCON REGL(0x080000)
|
||||
#define BANKCON0 REGL(0x080004)
|
||||
#define BANKCON1 REGL(0x080008)
|
||||
#define BANKCON2 REGL(0x08000c)
|
||||
#define BANKCON3 REGL(0x080010)
|
||||
#define BANKCON4 REGL(0x080014)
|
||||
#define BANKCON5 REGL(0x080018)
|
||||
#define BANKCON6 REGL(0x08001c)
|
||||
#define BANKCON7 REGL(0x080020)
|
||||
#define REFRESH REGL(0x080024)
|
||||
#define BANKSIZE REGL(0x080028)
|
||||
#define MRSRB6 REGL(0x08002c)
|
||||
#define MRSRB7 REGL(0x080030)
|
||||
|
||||
/*********************/
|
||||
/* UART Registers */
|
||||
/*********************/
|
||||
|
||||
#define ULCON0 REGL(0x100000)
|
||||
#define ULCON1 REGL(0x104000)
|
||||
#define UCON0 REGL(0x100004)
|
||||
#define UCON1 REGL(0x104004)
|
||||
#define UFCON0 REGL(0x100008)
|
||||
#define UFCON1 REGL(0x104008)
|
||||
#define UMCON0 REGL(0x10000c)
|
||||
#define UMCON1 REGL(0x10400c)
|
||||
#define UTRSTAT0 REGL(0x100010)
|
||||
#define UTRSTAT1 REGL(0x104010)
|
||||
#define UERSTAT0 REGL(0x100014)
|
||||
#define UERSTAT1 REGL(0x104014)
|
||||
#define UFSTAT0 REGL(0x100018)
|
||||
#define UFSTAT1 REGL(0x104018)
|
||||
#define UMSTAT0 REGL(0x10001c)
|
||||
#define UMSTAT1 REGL(0x10401c)
|
||||
#define UTXH0 REGB(0x100020)
|
||||
#define UTXH1 REGB(0x104020)
|
||||
#define URXH0 REGB(0x100024)
|
||||
#define URXH1 REGB(0x104024)
|
||||
#define UBRDIV0 REGL(0x100028)
|
||||
#define UBRDIV1 REGL(0x104028)
|
||||
|
||||
/*******************/
|
||||
/* SIO Registers */
|
||||
/*******************/
|
||||
|
||||
#define SIOCON REGL(0x114000)
|
||||
#define SIODAT REGL(0x114004)
|
||||
#define SBRDR REGL(0x114008)
|
||||
#define ITVCNT REGL(0x11400c)
|
||||
#define DCNTZ REGL(0x114010)
|
||||
|
||||
/********************/
|
||||
/* IIS Registers */
|
||||
/********************/
|
||||
|
||||
#define IISCON REGL(0x118000)
|
||||
#define IISMOD REGL(0x118004)
|
||||
#define IISPSR REGL(0x118008)
|
||||
#define IISFIFCON REGL(0x11800c)
|
||||
#define IISFIF REGW(0x118010)
|
||||
|
||||
/**************************/
|
||||
/* I/O Ports Registers */
|
||||
/**************************/
|
||||
|
||||
#define PCONA REGL(0x120000)
|
||||
#define PDATA REGL(0x120004)
|
||||
#define PCONB REGL(0x120008)
|
||||
#define PDATB REGL(0x12000c)
|
||||
#define PCONC REGL(0x120010)
|
||||
#define PDATC REGL(0x120014)
|
||||
#define PUPC REGL(0x120018)
|
||||
#define PCOND REGL(0x12001c)
|
||||
#define PDATD REGL(0x120020)
|
||||
#define PUPD REGL(0x120024)
|
||||
#define PCONE REGL(0x120028)
|
||||
#define PDATE REGL(0x12002c)
|
||||
#define PUPE REGL(0x120030)
|
||||
#define PCONF REGL(0x120034)
|
||||
#define PDATF REGL(0x120038)
|
||||
#define PUPF REGL(0x12003c)
|
||||
#define PCONG REGL(0x120040)
|
||||
#define PDATG REGL(0x120044)
|
||||
#define PUPG REGL(0x120048)
|
||||
#define SPUCR REGL(0x12004c)
|
||||
#define EXTINT REGL(0x120050)
|
||||
#define EXTINTPND REGL(0x120054)
|
||||
|
||||
/*********************************/
|
||||
/* WatchDog Timers Registers */
|
||||
/*********************************/
|
||||
|
||||
#define WTCON REGL(0x130000)
|
||||
#define WTDAT REGL(0x130004)
|
||||
#define WTCNT REGL(0x130008)
|
||||
|
||||
/*********************************/
|
||||
/* A/D Converter Registers */
|
||||
/*********************************/
|
||||
|
||||
#define ADCCON REGL(0x140000)
|
||||
#define ADCPSR REGL(0x140004)
|
||||
#define ADCDAT REGL(0x140008)
|
||||
|
||||
/***************************/
|
||||
/* PWM Timer Registers */
|
||||
/***************************/
|
||||
|
||||
#define TCFG0 REGL(0x150000)
|
||||
#define TCFG1 REGL(0x150004)
|
||||
#define TCON REGL(0x150008)
|
||||
#define TCNTB0 REGL(0x15000c)
|
||||
#define TCMPB0 REGL(0x150010)
|
||||
#define TCNTO0 REGL(0x150014)
|
||||
#define TCNTB1 REGL(0x150018)
|
||||
#define TCMPB1 REGL(0x15001c)
|
||||
#define TCNTO1 REGL(0x150020)
|
||||
#define TCNTB2 REGL(0x150024)
|
||||
#define TCMPB2 REGL(0x150028)
|
||||
#define TCNTO2 REGL(0x15002c)
|
||||
#define TCNTB3 REGL(0x150030)
|
||||
#define TCMPB3 REGL(0x150034)
|
||||
#define TCNTO3 REGL(0x150038)
|
||||
#define TCNTB4 REGL(0x15003c)
|
||||
#define TCMPB4 REGL(0x150040)
|
||||
#define TCNTO4 REGL(0x150044)
|
||||
#define TCNTB5 REGL(0x150048)
|
||||
#define TCNTO5 REGL(0x15004c)
|
||||
|
||||
/*********************/
|
||||
/* IIC Registers */
|
||||
/*********************/
|
||||
|
||||
#define IICCON REGL(0x160000)
|
||||
#define IICSTAT REGL(0x160004)
|
||||
#define IICADD REGL(0x160008)
|
||||
#define IICDS REGL(0x16000c)
|
||||
|
||||
/*********************/
|
||||
/* RTC Registers */
|
||||
/*********************/
|
||||
|
||||
#define RTCCON REGB(0x170040)
|
||||
#define RTCALM REGB(0x170050)
|
||||
#define ALMSEC REGB(0x170054)
|
||||
#define ALMMIN REGB(0x170058)
|
||||
#define ALMHOUR REGB(0x17005c)
|
||||
#define ALMDAY REGB(0x170060)
|
||||
#define ALMMON REGB(0x170064)
|
||||
#define ALMYEAR REGB(0x170068)
|
||||
#define RTCRST REGB(0x17006c)
|
||||
#define BCDSEC REGB(0x170070)
|
||||
#define BCDMIN REGB(0x170074)
|
||||
#define BCDHOUR REGB(0x170078)
|
||||
#define BCDDAY REGB(0x17007c)
|
||||
#define BCDDATE REGB(0x170080)
|
||||
#define BCDMON REGB(0x170084)
|
||||
#define BCDYEAR REGB(0x170088)
|
||||
#define TICINT REGB(0x17008c)
|
||||
|
||||
/*********************************/
|
||||
/* Clock & Power Registers */
|
||||
/*********************************/
|
||||
|
||||
#define PLLCON REGL(0x180000)
|
||||
#define CLKCON REGL(0x180004)
|
||||
#define CLKSLOW REGL(0x180008)
|
||||
#define LOCKTIME REGL(0x18000c)
|
||||
|
||||
/**************************************/
|
||||
/* Interrupt Controller Registers */
|
||||
/**************************************/
|
||||
|
||||
#define INTCON REGL(0x200000)
|
||||
#define INTPND REGL(0x200004)
|
||||
#define INTMOD REGL(0x200008)
|
||||
#define INTMSK REGL(0x20000c)
|
||||
#define I_PSLV REGL(0x200010)
|
||||
#define I_PMST REGL(0x200014)
|
||||
#define I_CSLV REGL(0x200018)
|
||||
#define I_CMST REGL(0x20001c)
|
||||
#define I_ISPR REGL(0x200020)
|
||||
#define I_ISPC REGL(0x200024)
|
||||
#define F_ISPR REGL(0x200038)
|
||||
#define F_ISPC REGL(0x20003c)
|
||||
|
||||
/********************************/
|
||||
/* LCD Controller Registers */
|
||||
/********************************/
|
||||
|
||||
#define LCDCON1 REGL(0x300000)
|
||||
#define LCDCON2 REGL(0x300004)
|
||||
#define LCDSADDR1 REGL(0x300008)
|
||||
#define LCDSADDR2 REGL(0x30000c)
|
||||
#define LCDSADDR3 REGL(0x300010)
|
||||
#define REDLUT REGL(0x300014)
|
||||
#define GREENLUT REGL(0x300018)
|
||||
#define BLUELUT REGL(0x30001c)
|
||||
#define DP1_2 REGL(0x300020)
|
||||
#define DP4_7 REGL(0x300024)
|
||||
#define DP3_5 REGL(0x300028)
|
||||
#define DP2_3 REGL(0x30002c)
|
||||
#define DP5_7 REGL(0x300030)
|
||||
#define DP3_4 REGL(0x300034)
|
||||
#define DP4_5 REGL(0x300038)
|
||||
#define DP6_7 REGL(0x30003c)
|
||||
#define LCDCON3 REGL(0x300040)
|
||||
#define DITHMODE REGL(0x300044)
|
||||
|
||||
/*********************/
|
||||
/* DMA Registers */
|
||||
/*********************/
|
||||
|
||||
#define ZDCON0 REGL(0x280000)
|
||||
#define ZDISRC0 REGL(0x280004)
|
||||
#define ZDIDES0 REGL(0x280008)
|
||||
#define ZDICNT0 REGL(0x28000c)
|
||||
#define ZDCSRC0 REGL(0x280010)
|
||||
#define ZDCDES0 REGL(0x280014)
|
||||
#define ZDCCNT0 REGL(0x280018)
|
||||
|
||||
#define ZDCON1 REGL(0x280020)
|
||||
#define ZDISRC1 REGL(0x280024)
|
||||
#define ZDIDES1 REGL(0x280028)
|
||||
#define ZDICNT1 REGL(0x28002c)
|
||||
#define ZDCSRC1 REGL(0x280030)
|
||||
#define ZDCDES1 REGL(0x280034)
|
||||
#define ZDCCNT1 REGL(0x280038)
|
||||
|
||||
#define BDCON0 REGL(0x380000)
|
||||
#define BDISRC0 REGL(0x380004)
|
||||
#define BDIDES0 REGL(0x380008)
|
||||
#define BDICNT0 REGL(0x38000c)
|
||||
#define BDCSRC0 REGL(0x380010)
|
||||
#define BDCDES0 REGL(0x380014)
|
||||
#define BDCCNT0 REGL(0x380018)
|
||||
|
||||
#define BDCON1 REGL(0x380020)
|
||||
#define BDISRC1 REGL(0x380024)
|
||||
#define BDIDES1 REGL(0x380028)
|
||||
#define BDICNT1 REGL(0x38002c)
|
||||
#define BDCSRC1 REGL(0x380030)
|
||||
#define BDCDES1 REGL(0x380034)
|
||||
#define BDCCNT1 REGL(0x380038)
|
||||
|
||||
|
||||
#define CLEAR_PEND_INT(n) I_ISPC = (1<<(n))
|
||||
#define INT_ENABLE(n) INTMSK &= ~(1<<(n))
|
||||
#define INT_DISABLE(n) INTMSK |= (1<<(n))
|
||||
|
||||
#define HARD_RESET_NOW()
|
||||
|
||||
#endif /* __ASM_ARCH_HARDWARE_H */
|
||||
Loading…
Reference in New Issue
Block a user