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ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platforms

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- Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE
- Cleanup of the 4xx GPIO functions
- Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-11-15 14:23:55 +01:00
parent 8ada0ebf38
commit aee747f19b
7 changed files with 99 additions and 106 deletions
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6
cpu/ppc4xx/cpu_init.c
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@ -112,7 +112,7 @@ cpu_init_f (void)
unsigned long val; unsigned long val;
#endif #endif
#if defined(CONFIG_405EP) || defined (CONFIG_405EX) #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
/* /*
* GPIO0 setup (select GPIO or alternate function) * GPIO0 setup (select GPIO or alternate function)
*/ */
@ -144,9 +144,9 @@ cpu_init_f (void)
#endif /* CONFIG_405EP */ #endif /* CONFIG_405EP */
#endif /* CONFIG_405EP */ #endif /* CONFIG_405EP */
#if defined(CFG_440_GPIO_TABLE) #if defined(CFG_4xx_GPIO_TABLE)
gpio_set_chip_configuration(); gpio_set_chip_configuration();
#endif /* CFG_440_GPIO_TABLE */ #endif /* CFG_4xx_GPIO_TABLE */
/* /*
* External Bus Controller (EBC) Setup * External Bus Controller (EBC) Setup

130
cpu/ppc4xx/gpio.c
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@ -26,8 +26,8 @@
#include <asm/io.h> #include <asm/io.h>
#include <asm/gpio.h> #include <asm/gpio.h>
#if defined(CFG_440_GPIO_TABLE) #if defined(CFG_4xx_GPIO_TABLE)
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE; gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE;
#endif #endif
#if defined(GPIO0_OSRL) #if defined(GPIO0_OSRL)
@ -55,10 +55,10 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
mask2 = 0xc0000000 >> (pin2 << 1); mask2 = 0xc0000000 >> (pin2 << 1);
/* first set TCR to 0 */ /* first set TCR to 0 */
out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) & ~mask); out_be32((void *)GPIO0_TCR + offs, in_be32((void *)GPIO0_TCR + offs) & ~mask);
if (in_out == GPIO_OUT) { if (in_out == GPIO_OUT) {
val = in32(GPIO0_OSRL + offs + offs2) & ~mask2; val = in_be32((void *)GPIO0_OSRL + offs + offs2) & ~mask2;
switch (gpio_alt) { switch (gpio_alt) {
case GPIO_ALT1: case GPIO_ALT1:
val |= GPIO_ALT1_SEL >> pin2; val |= GPIO_ALT1_SEL >> pin2;
@ -70,20 +70,23 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
val |= GPIO_ALT3_SEL >> pin2; val |= GPIO_ALT3_SEL >> pin2;
break; break;
} }
out32(GPIO0_OSRL + offs + offs2, val); out_be32((void *)GPIO0_OSRL + offs + offs2, val);
/* setup requested output value */ /* setup requested output value */
if (out_val == GPIO_OUT_0) if (out_val == GPIO_OUT_0)
out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~mask); out_be32((void *)GPIO0_OR + offs,
in_be32((void *)GPIO0_OR + offs) & ~mask);
else if (out_val == GPIO_OUT_1) else if (out_val == GPIO_OUT_1)
out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | mask); out_be32((void *)GPIO0_OR + offs,
in_be32((void *)GPIO0_OR + offs) | mask);
/* now configure TCR to drive output if selected */ /* now configure TCR to drive output if selected */
out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) | mask); out_be32((void *)GPIO0_TCR + offs,
in_be32((void *)GPIO0_TCR + offs) | mask);
} else { } else {
val = in32(GPIO0_ISR1L + offs + offs2) & ~mask2; val = in_be32((void *)GPIO0_ISR1L + offs + offs2) & ~mask2;
val |= GPIO_IN_SEL >> pin2; val |= GPIO_IN_SEL >> pin2;
out32(GPIO0_ISR1L + offs + offs2, val); out_be32((void *)GPIO0_ISR1L + offs + offs2, val);
} }
} }
#endif /* GPIO_OSRL */ #endif /* GPIO_OSRL */
@ -98,9 +101,11 @@ void gpio_write_bit(int pin, int val)
} }
if (val) if (val)
out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | GPIO_VAL(pin)); out_be32((void *)GPIO0_OR + offs,
in_be32((void *)GPIO0_OR + offs) | GPIO_VAL(pin));
else else
out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin)); out_be32((void *)GPIO0_OR + offs,
in_be32((void *)GPIO0_OR + offs) & ~GPIO_VAL(pin));
} }
int gpio_read_out_bit(int pin) int gpio_read_out_bit(int pin)
@ -112,10 +117,10 @@ int gpio_read_out_bit(int pin)
pin -= GPIO_MAX; pin -= GPIO_MAX;
} }
return (in32(GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0); return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
} }
#if defined(CFG_440_GPIO_TABLE) #if defined(CFG_4xx_GPIO_TABLE)
void gpio_set_chip_configuration(void) void gpio_set_chip_configuration(void)
{ {
unsigned char i=0, j=0, offs=0, gpio_core; unsigned char i=0, j=0, offs=0, gpio_core;
@ -141,24 +146,24 @@ void gpio_set_chip_configuration(void)
break; break;
case GPIO_ALT1: case GPIO_ALT1:
reg = in32(GPIO_IS1(core_add+offs)) reg = in_be32((void *)GPIO_IS1(core_add+offs))
& ~(GPIO_MASK >> (j*2)); & ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_IN_SEL >> (j*2)); reg = reg | (GPIO_IN_SEL >> (j*2));
out32(GPIO_IS1(core_add+offs), reg); out_be32((void *)GPIO_IS1(core_add+offs), reg);
break; break;
case GPIO_ALT2: case GPIO_ALT2:
reg = in32(GPIO_IS2(core_add+offs)) reg = in_be32((void *)GPIO_IS2(core_add+offs))
& ~(GPIO_MASK >> (j*2)); & ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_IN_SEL >> (j*2)); reg = reg | (GPIO_IN_SEL >> (j*2));
out32(GPIO_IS2(core_add+offs), reg); out_be32((void *)GPIO_IS2(core_add+offs), reg);
break; break;
case GPIO_ALT3: case GPIO_ALT3:
reg = in32(GPIO_IS3(core_add+offs)) reg = in_be32((void *)GPIO_IS3(core_add+offs))
& ~(GPIO_MASK >> (j*2)); & ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_IN_SEL >> (j*2)); reg = reg | (GPIO_IN_SEL >> (j*2));
out32(GPIO_IS3(core_add+offs), reg); out_be32((void *)GPIO_IS3(core_add+offs), reg);
break; break;
} }
} }
@ -168,87 +173,66 @@ void gpio_set_chip_configuration(void)
switch (gpio_tab[gpio_core][i].alt_nb) { switch (gpio_tab[gpio_core][i].alt_nb) {
case GPIO_SEL: case GPIO_SEL:
if (gpio_core == GPIO0) { /*
/* * Setup output value
* Setup output value * 1 -> high level
* 1 -> high level * 0 -> low level
* 0 -> low level * else -> don't touch
* else -> don't touch */
*/ reg = in_be32((void *)GPIO_OR(core_add));
reg = in32(GPIO0_OR); if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) reg |= (0x80000000 >> (i));
reg |= (0x80000000 >> (i)); else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0) reg &= ~(0x80000000 >> (i));
reg &= ~(0x80000000 >> (i)); out_be32((void *)GPIO_OR(core_add), reg);
out32(GPIO0_OR, reg);
reg = in32(GPIO0_TCR) | (0x80000000 >> (i)); reg = in_be32((void *)GPIO_TCR(core_add)) |
out32(GPIO0_TCR, reg); (0x80000000 >> (i));
} out_be32((void *)GPIO_TCR(core_add), reg);
#ifdef GPIO1 reg = in_be32((void *)GPIO_OS(core_add+offs))
if (gpio_core == GPIO1) {
/*
* Setup output value
* 1 -> high level
* 0 -> low level
* else -> don't touch
*/
reg = in32(GPIO1_OR);
if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
reg |= (0x80000000 >> (i));
else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
reg &= ~(0x80000000 >> (i));
out32(GPIO1_OR, reg);
reg = in32(GPIO1_TCR) | (0x80000000 >> (i));
out32(GPIO1_TCR, reg);
}
#endif /* GPIO1 */
reg = in32(GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2)); & ~(GPIO_MASK >> (j*2));
out32(GPIO_OS(core_add+offs), reg); out_be32((void *)GPIO_OS(core_add+offs), reg);
reg = in32(GPIO_TS(core_add+offs)) reg = in_be32((void *)GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2)); & ~(GPIO_MASK >> (j*2));
out32(GPIO_TS(core_add+offs), reg); out_be32((void *)GPIO_TS(core_add+offs), reg);
break; break;
case GPIO_ALT1: case GPIO_ALT1:
reg = in32(GPIO_OS(core_add+offs)) reg = in_be32((void *)GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2)); & ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT1_SEL >> (j*2)); reg = reg | (GPIO_ALT1_SEL >> (j*2));
out32(GPIO_OS(core_add+offs), reg); out_be32((void *)GPIO_OS(core_add+offs), reg);
reg = in32(GPIO_TS(core_add+offs)) reg = in_be32((void *)GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2)); & ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT1_SEL >> (j*2)); reg = reg | (GPIO_ALT1_SEL >> (j*2));
out32(GPIO_TS(core_add+offs), reg); out_be32((void *)GPIO_TS(core_add+offs), reg);
break; break;
case GPIO_ALT2: case GPIO_ALT2:
reg = in32(GPIO_OS(core_add+offs)) reg = in_be32((void *)GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2)); & ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT2_SEL >> (j*2)); reg = reg | (GPIO_ALT2_SEL >> (j*2));
out32(GPIO_OS(core_add+offs), reg); out_be32((void *)GPIO_OS(core_add+offs), reg);
reg = in32(GPIO_TS(core_add+offs)) reg = in_be32((void *)GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2)); & ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT2_SEL >> (j*2)); reg = reg | (GPIO_ALT2_SEL >> (j*2));
out32(GPIO_TS(core_add+offs), reg); out_be32((void *)GPIO_TS(core_add+offs), reg);
break; break;
case GPIO_ALT3: case GPIO_ALT3:
reg = in32(GPIO_OS(core_add+offs)) reg = in_be32((void *)GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2)); & ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT3_SEL >> (j*2)); reg = reg | (GPIO_ALT3_SEL >> (j*2));
out32(GPIO_OS(core_add+offs), reg); out_be32((void *)GPIO_OS(core_add+offs), reg);
reg = in32(GPIO_TS(core_add+offs)) reg = in_be32((void *)GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2)); & ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT3_SEL >> (j*2)); reg = reg | (GPIO_ALT3_SEL >> (j*2));
out32(GPIO_TS(core_add+offs), reg); out_be32((void *)GPIO_TS(core_add+offs), reg);
break; break;
} }
} }
} }
} }
} }
#endif /* CFG_440_GPIO_TABLE */ #endif /* CFG_4xx_GPIO_TABLE */

35
include/asm-ppc/gpio.h
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@ -21,6 +21,9 @@
* MA 02111-1307 USA * MA 02111-1307 USA
*/ */
#ifndef __ASM_PPC_GPIO_H
#define __ASM_PPC_GPIO_H
/* 4xx PPC's have 2 GPIO controllers */ /* 4xx PPC's have 2 GPIO controllers */
#if defined(CONFIG_405EZ) || \ #if defined(CONFIG_405EZ) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
@ -30,6 +33,36 @@
#define GPIO_GROUP_MAX 1 #define GPIO_GROUP_MAX 1
#endif #endif
/* Offsets */
#define GPIOx_OR 0x00 /* GPIO Output Register */
#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
#define GPIOx_IR 0x1C /* GPIO Input Register */
#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
#define GPIO_OR(x) (x+GPIOx_OR) /* GPIO Output Register */
#define GPIO_TCR(x) (x+GPIOx_TCR) /* GPIO Three-State Control Register */
#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Select Register High or Low */
#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
#define GPIO0 0
#define GPIO1 1
#define GPIO_MAX 32 #define GPIO_MAX 32
#define GPIO_ALT1_SEL 0x40000000 #define GPIO_ALT1_SEL 0x40000000
#define GPIO_ALT2_SEL 0x80000000 #define GPIO_ALT2_SEL 0x80000000
@ -56,3 +89,5 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
void gpio_write_bit(int pin, int val); void gpio_write_bit(int pin, int val);
int gpio_read_out_bit(int pin); int gpio_read_out_bit(int pin);
void gpio_set_chip_configuration(void); void gpio_set_chip_configuration(void);
#endif /* __ASM_PPC_GPIO_H */

2
include/configs/lwmon5.h
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@ -414,7 +414,7 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* PPC440 GPIO Configuration * PPC440 GPIO Configuration
*/ */
#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ #define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
{ \ { \
/* GPIO Core 0 */ \ /* GPIO Core 0 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \

2
include/configs/pcs440ep.h
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@ -365,7 +365,7 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* PPC440 GPIO Configuration * PPC440 GPIO Configuration
*/ */
#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ #define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
{ \ { \
/* GPIO Core 0 */ \ /* GPIO Core 0 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \

2
include/ppc405.h
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@ -1135,6 +1135,8 @@
#endif /* CONFIG_405EZ */ #endif /* CONFIG_405EZ */
#define GPIO0_BASE GPIO_BASE
#if defined(CONFIG_405EX) #if defined(CONFIG_405EX)
#define SDR0_SRST 0x0200 #define SDR0_SRST 0x0200

28
include/ppc440.h
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@ -3187,9 +3187,6 @@
/****************************************************************************** /******************************************************************************
* GPIO macro register defines * GPIO macro register defines
******************************************************************************/ ******************************************************************************/
#define GPIO0 0
#define GPIO1 1
#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700) #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)
@ -3205,31 +3202,6 @@
#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00) #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00)
#define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00) #define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00)
/* Offsets */
#define GPIOx_OR 0x00 /* GPIO Output Register */
#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
#define GPIOx_IR 0x1C /* GPIO Input Register */
#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
#define GPIO0_OR (GPIO0_BASE+0x0) #define GPIO0_OR (GPIO0_BASE+0x0)
#define GPIO0_TCR (GPIO0_BASE+0x4) #define GPIO0_TCR (GPIO0_BASE+0x4)
#define GPIO0_OSRL (GPIO0_BASE+0x8) #define GPIO0_OSRL (GPIO0_BASE+0x8)