ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention

This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
    psci_version,
    psci_features,
    psci_cpu_suspend,
    psci_affinity_info,
    psci_system_reset,
    psci_system_off.

Tested on LS1021aQDS, LS1021aTWR.

Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

board/freescale/ls1021aqds/Makefile

@@ -8,3 +8,4 @@ obj-y += ls1021aqds.o
 obj-y += ddr.o
 obj-y += eth.o
 obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_ARMV7_PSCI) += psci.o

board/freescale/ls1021aqds/psci.S

@@ -0,0 +1,33 @@
+/*
+ * Copyright 2016 NXP Semiconductor.
+ * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/psci.h>
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension sec
+
+	.align	5
+
+.globl	psci_system_off
+psci_system_off:
+	@ Get QIXIS base address
+	movw	r1, #(QIXIS_BASE & 0xffff)
+	movt	r1, #(QIXIS_BASE >> 16)
+
+	ldrb	r2, [r1, #QIXIS_PWR_CTL]
+	orr	r2, r2, #QIXIS_PWR_CTL_POWEROFF
+	strb	r2, [r1, #QIXIS_PWR_CTL]
+
+1:	wfi
+	b	1b
+
+	.popsection

board/freescale/ls1021atwr/Makefile

@@ -6,3 +6,4 @@
 
 obj-y += ls1021atwr.o
 obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_ARMV7_PSCI) += psci.o

board/freescale/ls1021atwr/psci.S

@@ -0,0 +1,25 @@
+/*
+ * Copyright 2016 NXP Semiconductor.
+ * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/psci.h>
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension sec
+
+	.align	5
+
+.globl	psci_system_off
+psci_system_off:
+1:	wfi
+	b	1b
+
+	.popsection