From 757c8387be4e406dc8ceb05672b7f1601c42fcde Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 6 Dec 2021 21:58:08 +0100 Subject: [PATCH 01/11] arm: stm32mp: Fix USB boot device report In case the SoC reports the boot device type is USB, it means the SPL was loaded via BootROM DFU mode. Currently the spl_boot_device() returns boot device as USB host, change it to DFU instead, so the SPL can continue the DFU boot and load U-Boot via DFU. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c index 405eff68a3..51fe0698fa 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/spl.c @@ -43,7 +43,7 @@ u32 spl_boot_device(void) case BOOT_SERIAL_UART_8: return BOOT_DEVICE_UART; case BOOT_SERIAL_USB_OTG: - return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; case BOOT_FLASH_NAND_FMC: return BOOT_DEVICE_NAND; case BOOT_FLASH_NOR_QSPI: From 3919aa1722a2b01683a8747e1eab1ec9f6de0f40 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 6 Dec 2021 21:58:09 +0100 Subject: [PATCH 02/11] ARM: dts: stm32: Add DFU support for DHCOR recovery This patch configures U-Boot SPL for DHCOR SoM to permit DFU upload of SPL and subsequent u-boot.itb for recovery or commissioning purposes. To start U-Boot on DHCOR based board, e.g. Avenger96, proceed as follows: - Install dfu-util on the host PC (in debian this is package 'dfu-util') - Power off the Avenger96 board. - Connect both USB-serial console and USB-OTG microB ports to host PC. - Switch Avenger96 to USB boot mode -- BOOT0..2 switches all set to 0. - Power on the Avenger96 board. - Verify using '$ dmesg' that a new device has been detected as follows: New USB device found, idVendor=0483, idProduct=df11, bcdDevice= 2.00 New USB device strings: Mfr=1, Product=2, SerialNumber=3 Product: DFU in HS Mode @Device ID /0x500, @Revision ID /0x0000 Manufacturer: STMicroelectronics - Upload U-Boot SPL: $ dfu-util -a 1 -D u-boot-spl.stm32 - Upload U-Boot proper: $ dfu-util -a 0 -D u-boot.itb - At this point, SPL will wait for user to press "Ctrl-C" on serial console. When ready to interact with U-Boot, press Ctrl-C to start the bootloader. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 42 ++++++++++++++++++++++ configs/stm32mp15_dhcor_basic_defconfig | 14 ++++++-- include/configs/stm32mp15_dh_dhsom.h | 7 ++++ 3 files changed, 61 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 502cd95da0..71375510b4 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -27,6 +27,7 @@ &i2c4 { u-boot,dm-pre-reloc; + u-boot,dm-spl; }; &i2c4_pins_a { @@ -38,6 +39,15 @@ &pmic { u-boot,dm-pre-reloc; + u-boot,dm-spl; + + regulators { + u-boot,dm-spl; + }; +}; + +&pwr_regulators { + u-boot,dm-spl; }; &qspi { @@ -152,3 +162,35 @@ u-boot,dm-pre-reloc; }; }; + +®11 { + u-boot,dm-spl; +}; + +®18 { + u-boot,dm-spl; +}; + +&usbotg_hs { + u-boot,dm-spl; +}; + +&usbphyc { + u-boot,dm-spl; +}; + +&usbphyc_port0 { + u-boot,dm-spl; +}; + +&usbphyc_port1 { + u-boot,dm-spl; +}; + +&vdd_io { + u-boot,dm-spl; +}; + +&vdd_usb { + u-boot,dm-spl; +}; diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 38b050f667..847f80ef4c 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -16,6 +16,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000 CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its" # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_BOOTDELAY=1 @@ -25,12 +26,17 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 +CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y CONFIG_SYS_PROMPT="STM32MP> " # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set @@ -68,6 +74,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended inter CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_ENV_IS_NOWHERE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=1536 @@ -76,7 +83,6 @@ CONFIG_SPL_BLOCK_CACHE=y CONFIG_DFU_MMC=y CONFIG_DFU_MTD=y CONFIG_DFU_RAM=y -CONFIG_DFU_VIRT=y CONFIG_GPIO_HOG=y CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y @@ -103,18 +109,20 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_DWC_ETH_QOS=y CONFIG_PHY=y +CONFIG_SPL_PHY=y CONFIG_PHY_STM32_USBPHYC=y CONFIG_PINCONF=y # CONFIG_SPL_PINCTRL_FULL is not set CONFIG_PINCTRL_STMFX=y CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_STPMIC1=y CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_STM32_VREFBUF=y CONFIG_DM_REGULATOR_STPMIC1=y +CONFIG_SPL_DM_REGULATOR_STPMIC1=y CONFIG_REMOTEPROC_STM32_COPRO=y CONFIG_DM_RTC=y CONFIG_RTC_STM32=y @@ -126,8 +134,10 @@ CONFIG_STM32_SPI=y CONFIG_SYSRESET_SYSCON=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC2=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_GADGET=y diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h index c79f0272cb..bb95480eeb 100644 --- a/include/configs/stm32mp15_dh_dhsom.h +++ b/include/configs/stm32mp15_dh_dhsom.h @@ -11,6 +11,13 @@ /* PHY needs a longer autoneg timeout */ #define PHY_ANEG_TIMEOUT 20000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "dfu_alt_info_ram=u-boot.itb ram " \ + __stringify(CONFIG_SPL_LOAD_FIT_ADDRESS) \ + " 0x800000\0" +#endif + #define STM32MP_BOARD_EXTRA_ENV \ "usb_pgood_delay=1000\0" \ "update_sf=" /* Erase SPI NOR and install U-Boot from SD */ \ From d5e8119baed0dda4bd38984c1a16a8409f9219af Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 7 Dec 2021 10:05:58 +0100 Subject: [PATCH 03/11] stm32mp: remove the bootcount activation Today the bootcount is not managed by the Linux kernel for STM32MP15 as we don't have driver to update the used backup register in TAMP and the recovery command still executes the normal bootcmd with 'altbootcmd=run bootcmd'. So the bootcount feature is never used, the config CONFIG_BOOTCOUNT_LIMIT and the associated environment variable 'altbootcmd' can be removed to reduce the U-Boot size. Each boards can re-enable this feature later in their defconfig, if it is needed, with the expected backend, for example CONFIG_BOOTCOUNT_GENERIC or CONFIG_BOOTCOUNT_ENV. CC: Marek Vasut Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/Kconfig | 8 -------- include/configs/stm32mp15_common.h | 1 - 2 files changed, 9 deletions(-) diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 06ac349e2e..1ed2aad63e 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -68,9 +68,7 @@ choice config TARGET_ST_STM32MP15x bool "STMicroelectronics STM32MP15x boards" select STM32MP15x - imply BOOTCOUNT_LIMIT imply BOOTSTAGE - imply CMD_BOOTCOUNT imply CMD_BOOTSTAGE imply CMD_CLS if CMD_BMP imply DISABLE_CONSOLE @@ -85,9 +83,7 @@ config TARGET_ST_STM32MP15x config TARGET_MICROGEA_STM32MP1 bool "Engicam MicroGEA STM32MP1 SOM" select STM32MP15x - imply BOOTCOUNT_LIMIT imply BOOTSTAGE - imply CMD_BOOTCOUNT imply CMD_BOOTSTAGE imply CMD_CLS if CMD_BMP imply DISABLE_CONSOLE @@ -112,9 +108,7 @@ config TARGET_MICROGEA_STM32MP1 config TARGET_ICORE_STM32MP1 bool "Engicam i.Core STM32MP1 SOM" select STM32MP15x - imply BOOTCOUNT_LIMIT imply BOOTSTAGE - imply CMD_BOOTCOUNT imply CMD_BOOTSTAGE imply CMD_CLS if CMD_BMP imply DISABLE_CONSOLE @@ -136,8 +130,6 @@ config TARGET_ICORE_STM32MP1 config TARGET_DH_STM32MP1_PDK2 bool "DH STM32MP1 PDK2" select STM32MP15x - imply BOOTCOUNT_LIMIT - imply CMD_BOOTCOUNT help Target the DH PDK2 development kit with STM32MP15x SoM. diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index 2bbc8def82..175d546a15 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -137,7 +137,6 @@ #endif #define STM32MP_EXTRA \ - "altbootcmd=run bootcmd\0" \ "env_check=if env info -p -d -q; then env save; fi\0" \ "boot_net_usb_start=true\0" From 5c68904fe1890c00baaa455bcd336fa9c92ec243 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 7 Dec 2021 10:05:59 +0100 Subject: [PATCH 04/11] stm32mp: correct the dependency for bootcount configs Default value for CONFIG_SYS_BOOTCOUNT_SINGLEWORD and CONFIG_SYS_BOOTCOUNT_ADDR are only needed when CONFIG_BOOTCOUNT_GENERIC is used. This patch avoids to define these configs when an other bootcount backend is activated, for example for CONFIG_BOOTCOUNT_ENV. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 1ed2aad63e..811c0fc261 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -195,7 +195,7 @@ config PRE_CON_BUF_SZ config BOOTSTAGE_STASH_ADDR default 0xC3000000 -if BOOTCOUNT_LIMIT +if BOOTCOUNT_GENERIC config SYS_BOOTCOUNT_SINGLEWORD default y From bd485f9bccc5e0a9d81c400858d1b8c8549b97aa Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 17 Dec 2021 16:30:22 +0100 Subject: [PATCH 05/11] arm: dts: stm32mp15: alignment with v5.16 Device tree alignment with Linux kernel v5.16-rc5 - ARM: dts: stm32: set otg-rev on stm32mp151 - ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151 - ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15 - ARM: dts: stm32: fix SAI sub nodes register range - ARM: dts: stm32: fix STUSB1600 Type-C irq level on stm32mp15xx-dkx Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp15-pinctrl.dtsi | 8 ++++---- arch/arm/dts/stm32mp151.dtsi | 19 ++++++++++--------- arch/arm/dts/stm32mp15xx-dkx.dtsi | 2 +- 3 files changed, 15 insertions(+), 14 deletions(-) diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index 5b60ecbd71..d3553e0f01 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -1179,7 +1179,7 @@ }; }; - sai2a_pins_c: sai2a-4 { + sai2a_pins_c: sai2a-2 { pins { pinmux = , /* SAI2_SCK_A */ , /* SAI2_SD_A */ @@ -1190,7 +1190,7 @@ }; }; - sai2a_sleep_pins_c: sai2a-5 { + sai2a_sleep_pins_c: sai2a-sleep-2 { pins { pinmux = , /* SAI2_SCK_A */ , /* SAI2_SD_A */ @@ -1235,14 +1235,14 @@ }; }; - sai2b_pins_c: sai2a-4 { + sai2b_pins_c: sai2b-2 { pins1 { pinmux = ; /* SAI2_SD_B */ bias-disable; }; }; - sai2b_sleep_pins_c: sai2a-sleep-5 { + sai2b_sleep_pins_c: sai2b-sleep-2 { pins { pinmux = ; /* SAI2_SD_B */ }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 8e0a0bc1dd..5a2be00758 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -842,7 +842,7 @@ #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x1c>; + reg = <0x4 0x20>; clocks = <&rcc SAI1_K>; clock-names = "sai_ck"; dmas = <&dmamux1 87 0x400 0x01>; @@ -852,7 +852,7 @@ sai1b: audio-controller@4400a024 { #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x1c>; + reg = <0x24 0x20>; clocks = <&rcc SAI1_K>; clock-names = "sai_ck"; dmas = <&dmamux1 88 0x400 0x01>; @@ -873,7 +873,7 @@ sai2a: audio-controller@4400b004 { #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x1c>; + reg = <0x4 0x20>; clocks = <&rcc SAI2_K>; clock-names = "sai_ck"; dmas = <&dmamux1 89 0x400 0x01>; @@ -883,7 +883,7 @@ sai2b: audio-controller@4400b024 { #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x1c>; + reg = <0x24 0x20>; clocks = <&rcc SAI2_K>; clock-names = "sai_ck"; dmas = <&dmamux1 90 0x400 0x01>; @@ -904,7 +904,7 @@ sai3a: audio-controller@4400c004 { #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x1c>; + reg = <0x04 0x20>; clocks = <&rcc SAI3_K>; clock-names = "sai_ck"; dmas = <&dmamux1 113 0x400 0x01>; @@ -914,7 +914,7 @@ sai3b: audio-controller@4400c024 { #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x1c>; + reg = <0x24 0x20>; clocks = <&rcc SAI3_K>; clock-names = "sai_ck"; dmas = <&dmamux1 114 0x400 0x01>; @@ -1103,6 +1103,7 @@ g-np-tx-fifo-size = <32>; g-tx-fifo-size = <256 16 16 16 16 16 16 16>; dr_mode = "otg"; + otg-rev = <0x200>; usb33d-supply = <&usb33>; status = "disabled"; }; @@ -1301,7 +1302,7 @@ sai4a: audio-controller@50027004 { #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x1c>; + reg = <0x04 0x20>; clocks = <&rcc SAI4_K>; clock-names = "sai_ck"; dmas = <&dmamux1 99 0x400 0x01>; @@ -1311,7 +1312,7 @@ sai4b: audio-controller@50027024 { #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x1c>; + reg = <0x24 0x20>; clocks = <&rcc SAI4_K>; clock-names = "sai_ck"; dmas = <&dmamux1 100 0x400 0x01>; @@ -1482,7 +1483,7 @@ usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; - clocks = <&rcc USBH>; + clocks = <&rcc USBH>, <&usbphyc>; resets = <&rcc USBH_R>; interrupts = ; status = "disabled"; diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 8fc93b0f94..5502eec94b 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -257,7 +257,7 @@ stusb1600@28 { compatible = "st,stusb1600"; reg = <0x28>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpioi>; pinctrl-names = "default"; pinctrl-0 = <&stusb1600_pins_a>; From 6b8bd7090485bfaa52356ec7d5518b95cc49c3d1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 30 Dec 2021 23:46:46 +0100 Subject: [PATCH 06/11] ARM: dts: stm32: Synchronize DHCOR DTs with Linux 5.15.12 Synchronize DH DHCOR DTs with Linux commit 25960cafa06e ("Linux 5.15.12"). There is no functional change to the resulting DTs. The eeprom0 alias is now reinstated in SoM u-boot dtsi, the PHY reset GPIO is reinstated in AV96 u-boot dtsi. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrick Delaunay --- arch/arm/dts/Makefile | 1 - arch/arm/dts/stm32mp157a-avenger96.dts | 8 - arch/arm/dts/stm32mp157a-dhcor-avenger96.dts | 38 ++ .../stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 2 + arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 202 +------- arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi | 431 ++++++++++++++++++ arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi | 7 +- ...-io3v3.dtsi => stm32mp15xx-dhcor-som.dtsi} | 30 +- arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 8 + 9 files changed, 503 insertions(+), 224 deletions(-) delete mode 100644 arch/arm/dts/stm32mp157a-avenger96.dts create mode 100644 arch/arm/dts/stm32mp157a-dhcor-avenger96.dts create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi rename arch/arm/dts/{stm32mp15xx-dhcor-io3v3.dtsi => stm32mp15xx-dhcor-som.dtsi} (91%) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1b65e65eb8..ce332021d8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1107,7 +1107,6 @@ dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb dtb-$(CONFIG_STM32MP15x) += \ stm32mp157a-dk1.dtb \ - stm32mp157a-avenger96.dtb \ stm32mp157a-icore-stm32mp1-ctouch2.dtb \ stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts deleted file mode 100644 index 9c165104fb..0000000000 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) Linaro Ltd 2019 - All Rights Reserved - * Author: Manivannan Sadhasivam - */ - -/* This is kept for backward compatibility and will be removed */ -#include "stm32mp15xx-dhcor-avenger96.dts" diff --git a/arch/arm/dts/stm32mp157a-dhcor-avenger96.dts b/arch/arm/dts/stm32mp157a-dhcor-avenger96.dts new file mode 100644 index 0000000000..2e3c9fbb4e --- /dev/null +++ b/arch/arm/dts/stm32mp157a-dhcor-avenger96.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + * + * DHCOR STM32MP1 variant: + * DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG + * DHCOR PCB number: 586-100 or newer + * Avenger96 PCB number: 588-200 or newer + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" +#include "stm32mp15xx-dhcor-avenger96.dtsi" + +/ { + model = "Arrow Electronics STM32MP157A Avenger96 board"; + compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som", + "st,stm32mp157"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_b>; + pinctrl-1 = <&m_can1_sleep_pins_b>; + status = "disabled"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "disabled"; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi index c96eba99c5..6e6543b5e4 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -21,6 +21,8 @@ ðernet0 { + phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + mdio0 { ethernet-phy@7 { reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts index 0e860e5cf8..76ac5a873c 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts @@ -7,206 +7,12 @@ /dts-v1/; -#include "stm32mp15xx-dhcor-io1v8.dtsi" -#include "stm32mp15xx-dhcor-avenger96-u-boot.dtsi" +#include "stm32mp151.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" +#include "stm32mp15xx-dhcor-avenger96.dtsi" / { model = "Arrow Electronics STM32MP15xx Avenger96 board"; compatible = "arrow,stm32mp15xx-avenger96", "st,stm32mp15x"; - - aliases { - eeprom0 = &eeprom0; - ethernet0 = ðernet0; - mmc0 = &sdmmc1; - serial0 = &uart4; - serial1 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - led { - compatible = "gpio-leds"; - led1 { - label = "green:user0"; - gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led2 { - label = "green:user1"; - gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "green:user2"; - gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led4 { - label = "green:user3"; - gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - panic-indicator; - }; - - led5 { - label = "yellow:wifi"; - gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - led6 { - label = "blue:bt"; - gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; - }; - - sd_switch: regulator-sd_switch { - compatible = "regulator-gpio"; - regulator-name = "sd_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - regulator-always-on; - - gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1>, - <2900000 0x0>; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_c>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; - max-speed = <1000>; - phy-handle = <&phy0>; - phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@7 { - reg = <7>; - }; - }; -}; - -&i2c1 { /* X6 I2C1 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c2 { /* X6 I2C2 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_c>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c4 { - eeprom0: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; - disable-wp; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - vqmmc-supply = <&sd_switch>; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; - non-removable; - no-sd; - no-sdio; - st,neg-edge; - bus-width = <8>; - vmmc-supply = <&v3v3>; - mmc-ddr-3_3v; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; -}; - -&uart4 { - /* On Low speed expansion header */ - label = "LS-UART1"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_b>; - status = "okay"; -}; - -&uart7 { - /* On Low speed expansion header */ - label = "LS-UART0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - phy-names = "usb"; - status = "okay"; -}; - -&usbotg_hs { - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi new file mode 100644 index 0000000000..6885948f30 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + */ + +/* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */ +#include "stm32mp15xx-dhcor-io1v8.dtsi" + +/ { + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + serial2 = &usart2; + spi0 = &qspi; + }; + + /* XTal Q1 */ + cec_clock: clk-cec-fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7513_out>; + }; + }; + }; + + led { + compatible = "gpio-leds"; + led1 { + label = "green:user0"; + gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user1"; + gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user2"; + gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user3"; + gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP1-AV96-HDMI"; + dais = <&sai2a_port>; + status = "okay"; + }; + + wlan_pwr: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 6>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 2>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "AV96-K", + "AV96-I", "", "AV96-A", ""; +}; + +&gpiob { + gpio-line-names = "", "", "", "", + "", "AV96-J", "", "", + "", "", "", "AV96-B", + "", "AV96-L", "", ""; +}; + +&gpioc { + gpio-line-names = "", "", "", "AV96-C", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "", "", + "AV96-D", "", "", "", + "", "", "AV96-E", "AV96-F"; +}; + +&gpiof { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "AV96-G", "AV96-H", "", ""; +}; + +&i2c1 { /* X6 I2C1 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c2 { /* X6 I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_c>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + hdmi-transmitter@3d { + compatible = "adi,adv7513"; + reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>; + reg-names = "main", "edid", "cec", "packet"; + clocks = <&cec_clock>; + clock-names = "cec"; + + avdd-supply = <&v3v3>; + dvdd-supply = <&v3v3>; + pvdd-supply = <&v3v3>; + dvdd-3v-supply = <&v3v3>; + bgvdd-supply = <&v3v3>; + + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpiog>; + + status = "okay"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7513_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7513_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + + port@2 { + reg = <2>; + adv7513_i2s0: endpoint { + remote-endpoint = <&sai2a_endpoint>; + }; + }; + }; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_d>; + pinctrl-1 = <<dc_sleep_pins_d>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&adv7513_in>; + }; + }; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_c>; + pinctrl-1 = <&sai2a_sleep_pins_c>; + clock-names = "pclk", "x8k", "x11k"; + status = "okay"; + + sai2a: audio-controller@4400b004 { + #clock-cells = <0>; + dma-names = "tx"; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + status = "okay"; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&adv7513_i2s0>; + format = "i2s"; + mclk-fs = <256>; + }; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; + bus-width = <8>; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd_io>; + status = "okay"; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_b>; + pinctrl-1 = <&sdmmc3_b4_od_pins_b>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; + broken-cd; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&wlan_pwr>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + cs-gpios = <&gpioi 0 0>; + status = "disabled"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&uart4 { + /* On Low speed expansion header */ + label = "LS-UART1"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + status = "okay"; +}; + +&uart7 { + /* On Low speed expansion header */ + label = "LS-UART0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +/* Bluetooth */ +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + st,hw-flow-ctrl; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + status = "okay"; + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi index 75435424d6..75172314d7 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi @@ -1,12 +1,12 @@ // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) /* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam * Copyright (C) 2020 Marek Vasut */ -#include "stm32mp15xx-dhcor-io3v3.dtsi" - / { - /* Enpirion EP3A8LQI U2 on the 1V8 IO DHCOR */ + /* Enpirion EP3A8LQI U2 on the DHCOR */ vdd_io: regulator-buck-io { compatible = "regulator-fixed"; regulator-name = "buck-io"; @@ -20,5 +20,4 @@ &pwr_regulators { vdd-supply = <&vdd_io>; - vdd_3v3_usbfs-supply = <&vdd_usb>; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi similarity index 91% rename from arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi rename to arch/arm/dts/stm32mp15xx-dhcor-som.dtsi index 94cf80dbed..44ecc47085 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi @@ -4,9 +4,7 @@ * Author: Manivannan Sadhasivam * Copyright (C) 2020 Marek Vasut */ -/dts-v1/; -#include "stm32mp157.dtsi" #include "stm32mp15-pinctrl.dtsi" #include "stm32mp15xxac-pinctrl.dtsi" #include @@ -23,6 +21,14 @@ }; }; +&crc1 { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; @@ -35,7 +41,7 @@ pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>; - interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; status = "okay"; @@ -53,7 +59,7 @@ vddcore: buck1 { regulator-name = "vddcore"; - regulator-min-microvolt = <800000>; + regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>; @@ -92,7 +98,6 @@ regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; interrupts = ; - interrupt-parent = <&pmic>; }; v2v8: ldo2 { @@ -100,7 +105,6 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; interrupts = ; - interrupt-parent = <&pmic>; }; vtt_ddr: ldo3 { @@ -114,7 +118,6 @@ vdd_usb: ldo4 { regulator-name = "vdd_usb"; interrupts = ; - interrupt-parent = <&pmic>; }; vdd_sd: ldo5 { @@ -122,7 +125,6 @@ regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; interrupts = ; - interrupt-parent = <&pmic>; regulator-boot-on; }; @@ -131,7 +133,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; interrupts = ; - interrupt-parent = <&pmic>; regulator-enable-ramp-delay = <300000>; }; @@ -143,20 +144,17 @@ bst_out: boost { regulator-name = "bst_out"; interrupts = ; - interrupt-parent = <&pmic>; }; vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = ; - interrupt-parent = <&pmic>; regulator-active-discharge = <1>; }; vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; - interrupt-parent = <&pmic>; regulator-active-discharge = <1>; }; }; @@ -173,6 +171,12 @@ status = "disabled"; }; }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; }; &iwdg2 { @@ -194,7 +198,7 @@ #size-cells = <0>; status = "okay"; - flash0: spi-flash@0 { + flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 71375510b4..338b674368 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -15,6 +15,11 @@ / { u-boot,dm-pre-reloc; + + aliases { + eeprom0 = &eeprom0; + }; + config { dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>; dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>; @@ -28,6 +33,9 @@ &i2c4 { u-boot,dm-pre-reloc; u-boot,dm-spl; + + eeprom0: eeprom@53 { + }; }; &i2c4_pins_a { From 332facce6f5669fc1bb8d150c08cee2ebdae6d2b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 30 Dec 2021 23:46:47 +0100 Subject: [PATCH 07/11] ARM: dts: stm32: Synchronize DHCOM DTs with Linux 5.15.12 Synchronize DH DHCOM DTs with Linux commit 25960cafa06e ("Linux 5.15.12"). There is no functional change to the resulting DTs. The eeprom0 alias and PHY reset GPIO are now reinstated in SoM u-boot dtsi. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcom-drc02.dts | 162 +------- arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi | 165 ++++++++ .../dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi | 4 + arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts | 14 +- arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi | 325 +++++++++++++++ .../dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi | 6 +- arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts | 88 +--- arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi | 147 +++++++ ...-dhcom.dtsi => stm32mp15xx-dhcom-som.dtsi} | 387 +++++++++++------- arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 43 +- 10 files changed, 917 insertions(+), 424 deletions(-) create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi rename arch/arm/dts/{stm32mp15xx-dhcom.dtsi => stm32mp15xx-dhcom-som.dtsi} (56%) diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts index 4948ccd401..1ef9ac29ce 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts @@ -2,166 +2,14 @@ /* * Copyright (C) 2020 Marek Vasut */ +/dts-v1/; -#include "stm32mp15xx-dhcom.dtsi" +#include "stm32mp151.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcom-som.dtsi" +#include "stm32mp15xx-dhcom-drc02.dtsi" / { model = "DH Electronics STM32MP15xx DHCOM DRC02"; compatible = "dh,stm32mp15xx-dhcom-drc02", "st,stm32mp1xx"; - - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&adc { - status = "disabled"; -}; - -&dac { - status = "disabled"; -}; - -&gpiob { - /* - * NOTE: On DRC02, the RS485_RX_En is controlled by a separate - * GPIO line, however the STM32 UART driver assumes RX happens - * during TX anyway and that it only controls drive enable DE - * line. Hence, the RX is always enabled here. - */ - usb-hub { - gpio-hog; - gpios = <8 0>; - output-high; - line-name = "rs485-rx-en"; - }; -}; - -&gpiod { - gpio-line-names = "", "", "", "", - "", "", "", "", - "", "", "", "Out1", - "Out2", "", "", ""; -}; - -&gpioi { - gpio-line-names = "In1", "", "", "", - "", "", "", "", - "In2", "", "", "", - "", "", "", ""; - - /* - * NOTE: The USB Hub on the DRC02 needs a reset signal to be - * pulled high in order to be detected by the USB Controller. - * This signal should be handled by USB power sequencing in - * order to reset the Hub when USB bus is powered down, but - * so far there is no such functionality. - */ - usb-hub { - gpio-hog; - gpios = <2 0>; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c5 { /* TP7/TP8 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; -}; - -&sdmmc3 { - /* - * On DRC02, the SoM does not have SDIO WiFi. The pins - * are used for on-board microSD slot instead. - */ - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_a>; - pinctrl-1 = <&sdmmc3_b4_od_pins_a>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; - cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; - disable-wp; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; - mmc-ddr-3_3v; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - cs-gpios = <&gpioz 3 0>; - /* Use PIO for the display */ - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; /* Enable once there is display driver */ - /* - * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are - * also connected to the display board connector. - */ -}; - -&usart3 { - pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins_a>; - status = "okay"; -}; - -/* - * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1), - * however the STM32MP1 pinmux cannot map them to UART4 . - */ - -&uart8 { /* RS485 */ - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a>; - rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi new file mode 100644 index 0000000000..4b10b013ff --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut + */ + +#include +#include + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&adc { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&gpiob { + /* + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate + * GPIO line, however the STM32 UART driver assumes RX happens + * during TX anyway and that it only controls drive enable DE + * line. Hence, the RX is always enabled here. + */ + rs485-rx-en-hog { + gpio-hog; + gpios = <8 0>; + output-low; + line-name = "rs485-rx-en"; + }; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "DHCOM-B", "", + "", "", "", "DRC02-Out1", + "DRC02-Out2", "", "", ""; +}; + +&gpioi { + gpio-line-names = "DRC02-In1", "DHCOM-O", "DHCOM-H", "DHCOM-I", + "DHCOM-R", "DHCOM-M", "", "", + "DRC02-In2", "", "", "", + "", "", "", ""; + + /* + * NOTE: The USB Hub on the DRC02 needs a reset signal to be + * pulled high in order to be detected by the USB Controller. + * This signal should be handled by USB power sequencing in + * order to reset the Hub when USB bus is powered down, but + * so far there is no such functionality. + */ + usb-hub-hog { + gpio-hog; + gpios = <2 0>; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c4 { + touchscreen@49 { + status = "disabled"; + }; +}; + +&i2c5 { /* TP7/TP8 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&sdmmc3 { + /* + * On DRC02, the SoM does not have SDIO WiFi. The pins + * are used for on-board microSD slot instead. + */ + /delete-property/broken-cd; + cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; + disable-wp; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + cs-gpios = <&gpioz 3 0>; + /* Use PIO for the display */ + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; /* Enable once there is display driver */ + /* + * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are + * also connected to the display board connector. + */ +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + status = "okay"; +}; + +/* + * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1), + * however the STM32MP1 pinmux cannot map them to UART4 . + */ + +&uart8 { /* RS485 */ + linux,rs485-enabled-at-boot-time; + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi index 12f89b3398..2324926f9d 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi @@ -4,3 +4,7 @@ */ #include "stm32mp15xx-dhcom-u-boot.dtsi" + +&usbotg_hs { + dr_mode = "peripheral"; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts index 52a77c4123..e2e01e2146 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts @@ -2,18 +2,14 @@ /* * Copyright (C) 2019 Marek Vasut */ +/dts-v1/; -#include "stm32mp15xx-dhcom.dtsi" +#include "stm32mp151.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcom-som.dtsi" +#include "stm32mp15xx-dhcom-pdk2.dtsi" / { model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)"; compatible = "dh,stm32mp15xx-dhcom-pdk2", "st,stm32mp15x"; - - aliases { - serial0 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi new file mode 100644 index 0000000000..fbf3826933 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019-2020 Marek Vasut + */ + +#include +#include + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clk_ext_audio_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + display_bl: display-bl { + compatible = "pwm-backlight"; + pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + default-brightness-level = <8>; + enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; + power-supply = <®_panel_bl>; + status = "okay"; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + /* + * The EXTi IRQ line 3 is shared with ethernet, + * so mark this as polled GPIO key. + */ + button-0 { + label = "TA1-GPIO-A"; + linux,code = ; + gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; + }; + + /* + * The EXTi IRQ line 6 is shared with touchscreen, + * so mark this as polled GPIO key. + */ + button-1 { + label = "TA2-GPIO-B"; + linux,code = ; + gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; + }; + + /* + * The EXTi IRQ line 0 is shared with PMIC, + * so mark this as polled GPIO key. + */ + button-2 { + label = "TA3-GPIO-C"; + linux,code = ; + gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-3 { + label = "TA4-GPIO-D"; + linux,code = ; + gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + label = "green:led5"; + gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + status = "disabled"; + }; + + led-1 { + label = "green:led6"; + gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + label = "green:led7"; + gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + label = "green:led8"; + gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + panel { + compatible = "edt,etm0700g0edh6"; + backlight = <&display_bl>; + power-supply = <®_panel_bl>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_panel_bl: regulator-panel-bl { + compatible = "regulator-fixed"; + regulator-name = "panel_backlight"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_panel_supply>; + }; + + reg_panel_supply: regulator-panel-supply { + compatible = "regulator-fixed"; + regulator-name = "panel_supply"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + }; + + sound { + compatible = "audio-graph-card"; + routing = + "MIC_IN", "Capture", + "Capture", "Mic Bias", + "Playback", "HP_OUT"; + dais = <&sai2a_port &sai2b_port>; + status = "okay"; + }; +}; + +&cec { + pinctrl-names = "default"; + pinctrl-0 = <&cec_pins_a>; + status = "okay"; +}; + +&i2c2 { /* Header X22 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&i2c5 { /* Header X21 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_ext_audio_codec>; + VDDA-supply = <&v3v3>; + VDDIO-supply = <&vdd>; + + sgtl5000_port: port { + #address-cells = <1>; + #size-cells = <0>; + + sgtl5000_tx_endpoint: endpoint@0 { + reg = <0>; + remote-endpoint = <&sai2a_endpoint>; + frame-master = <&sgtl5000_tx_endpoint>; + bitclock-master = <&sgtl5000_tx_endpoint>; + }; + + sgtl5000_rx_endpoint: endpoint@1 { + reg = <1>; + remote-endpoint = <&sai2b_endpoint>; + frame-master = <&sgtl5000_rx_endpoint>; + bitclock-master = <&sgtl5000_rx_endpoint>; + }; + }; + + }; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&gpioc>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_b>; + pinctrl-1 = <<dc_sleep_pins_b>; + status = "okay"; + + port { + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>; + pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>; + status = "okay"; + + sai2a: audio-controller@4400b004 { + #clock-cells = <0>; + dma-names = "tx"; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + status = "okay"; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&sgtl5000_tx_endpoint>; + format = "i2s"; + mclk-fs = <512>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; + }; + + sai2b: audio-controller@4400b024 { + dma-names = "rx"; + st,sync = <&sai2a 2>; + clocks = <&rcc SAI2_K>, <&sai2a>; + clock-names = "sai_ck", "MCLK"; + status = "okay"; + + sai2b_port: port { + sai2b_endpoint: endpoint { + remote-endpoint = <&sgtl5000_rx_endpoint>; + format = "i2s"; + mclk-fs = <512>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; + }; +}; + +&timers2 { + /* spare dmas for other usage (un-delete to enable pwm capture) */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + pwm2: pwm { + pinctrl-0 = <&pwm2_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + timer@1 { + status = "okay"; + }; +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi index 3cac663d98..5bc6698f87 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi @@ -11,4 +11,8 @@ }; }; -/delete-node/ &ksz8851; +/delete-node/ &ks8851; + +&usbotg_hs { + dr_mode = "peripheral"; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts index 59d13713d8..06770b4787 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts @@ -2,92 +2,14 @@ /* * Copyright (C) 2020 Marek Vasut */ +/dts-v1/; -#include "stm32mp15xx-dhcom.dtsi" +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcom-som.dtsi" +#include "stm32mp15xx-dhcom-picoitx.dtsi" / { model = "DH Electronics STM32MP15xx DHCOM PicoITX"; compatible = "dh,stm32mp15xx-dhcom-picoitx", "st,stm32mp1xx"; - - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&adc { - status = "disabled"; -}; - -&dac { - status = "disabled"; -}; - -&gpioa { - /* - * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable - * port power. This signal should be handled by USB power sequencing - * in order to turn on port power when USB bus is powered up, but so - * far there is no such functionality. - */ - usb-port-power { - gpio-hog; - gpios = <13 0>; - output-low; - line-name = "usb-port-power"; - }; -}; - -&i2c2 { /* On board-to-board connector (optional) */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c5 { /* On board-to-board connector */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; -}; - -&usart3 { - pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins_a>; - status = "okay"; -}; - -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a>; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi new file mode 100644 index 0000000000..ba816ef8b9 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut + */ + +#include +#include + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + label = "yellow:led"; + gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&adc { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&fmc { + status = "disabled"; +}; + +&gpioa { + /* + * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable + * port power. This signal should be handled by USB power sequencing + * in order to turn on port power when USB bus is powered up, but so + * far there is no such functionality. + */ + usb-port-power-hog { + gpio-hog; + gpios = <13 0>; + output-low; + line-name = "usb-port-power"; + }; +}; + +&gpioc { + gpio-line-names = "", "", "", "", + "", "", "PicoITX-In1", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "DHCOM-B", "", + "", "", "", "PicoITX-Out1", + "PicoITX-Out2", "", "", ""; +}; + +&gpiog { + gpio-line-names = "PicoITX-In2", "", "", "", + "", "", "", "", + "DHCOM-L", "", "", "", + "", "", "", ""; +}; + +&i2c2 { /* On board-to-board connector (optional) */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c5 { /* On board-to-board connector */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&ksz8851 { + status = "disabled"; +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi similarity index 56% rename from arch/arm/dts/stm32mp15xx-dhcom.dtsi rename to arch/arm/dts/stm32mp15xx-dhcom-som.dtsi index a1d1b8dec7..8c41f819f7 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi @@ -1,11 +1,8 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) 2019 Marek Vasut + * Copyright (C) 2019-2020 Marek Vasut */ -/dts-v1/; -#include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" #include "stm32mp15-pinctrl.dtsi" #include "stm32mp15xxaa-pinctrl.dtsi" #include @@ -13,8 +10,10 @@ / { aliases { - eeprom0 = &eeprom0; ethernet0 = ðernet0; + ethernet1 = &ksz8851; + rtc0 = &hwrtc; + rtc1 = &rtc; }; memory@c0000000 { @@ -22,6 +21,48 @@ reg = <0xC0000000 0x40000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + ethernet_vio: vioregulator { compatible = "regulator-fixed"; regulator-name = "vio"; @@ -30,20 +71,45 @@ gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; regulator-always-on; regulator-boot-on; + vin-supply = <&vdd>; }; }; -&cec { - pinctrl-names = "default"; - pinctrl-0 = <&cec_pins_a>; +&adc { + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,min-sample-time-nsecs = <5000>; + st,adc-channels = <0>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <1>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +&crc1 { status = "okay"; }; -&dcmi { +&dac { + pinctrl-names = "default"; + pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; + vref-supply = <&vdda>; status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dcmi_pins_a>; - pinctrl-1 = <&dcmi_sleep_pins_a>; + + dac1: dac@1 { + status = "okay"; + }; + dac2: dac@2 { + status = "okay"; + }; }; &dts { @@ -53,12 +119,12 @@ ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_pins_sleep_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rmii"; max-speed = <100>; phy-handle = <&phy0>; - phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; + st,eth-ref-clk-sel; mdio0 { #address-cells = <1>; @@ -67,16 +133,112 @@ phy0: ethernet-phy@1 { reg = <1>; + /* LAN8710Ai */ + compatible = "ethernet-phy-id0007.c0f0", + "ethernet-phy-ieee802.3-c22"; + clocks = <&rcc ETHCK_K>; + reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <500>; + reset-deassert-us = <500>; + smsc,disable-energy-detect; + interrupt-parent = <&gpioi>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; }; }; }; -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; +&fmc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&fmc_pins_b>; + pinctrl-1 = <&fmc_sleep_pins_b>; status = "okay"; + + ksz8851: ethernet@1,0 { + compatible = "micrel,ks8851-mll"; + reg = <1 0x0 0x2>, <1 0x2 0x20000>; + interrupt-parent = <&gpioc>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + bank-width = <2>; + + /* Timing values are in nS */ + st,fmc2-ebi-cs-mux-enable; + st,fmc2-ebi-cs-transaction-type = <4>; + st,fmc2-ebi-cs-buswidth = <16>; + st,fmc2-ebi-cs-address-setup-ns = <5>; + st,fmc2-ebi-cs-address-hold-ns = <5>; + st,fmc2-ebi-cs-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-data-setup-ns = <45>; + st,fmc2-ebi-cs-data-hold-ns = <1>; + st,fmc2-ebi-cs-write-address-setup-ns = <5>; + st,fmc2-ebi-cs-write-address-hold-ns = <5>; + st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-write-data-setup-ns = <45>; + st,fmc2-ebi-cs-write-data-hold-ns = <1>; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", + "", "", "DHCOM-K", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiob { + gpio-line-names = "", "", "", "", + "", "", "", "", + "DHCOM-Q", "", "", "", + "", "", "", ""; +}; + +&gpioc { + gpio-line-names = "", "", "", "", + "", "", "DHCOM-E", "", + "", "", "", "", + "", "", "", ""; + status = "okay"; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "DHCOM-B", "", + "", "", "", "DHCOM-F", + "DHCOM-D", "", "", ""; +}; + +&gpioe { + gpio-line-names = "", "", "", "", + "", "", "DHCOM-P", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiof { + gpio-line-names = "", "", "", "DHCOM-A", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiog { + gpio-line-names = "DHCOM-C", "", "", "", + "", "", "", "", + "DHCOM-L", "", "", "", + "", "", "", ""; +}; + +&gpioh { + gpio-line-names = "", "", "", "", + "", "", "", "DHCOM-N", + "DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U", + "DHCOM-T", "", "DHCOM-S", ""; +}; + +&gpioi { + gpio-line-names = "DHCOM-G", "DHCOM-O", "DHCOM-H", "DHCOM-I", + "DHCOM-R", "DHCOM-M", "", "", + "", "", "", "", + "", "", "", ""; }; &i2c4 { @@ -89,6 +251,11 @@ /delete-property/dmas; /delete-property/dma-names; + hwrtc: rtc@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>; @@ -146,6 +313,7 @@ vdda: ldo1 { regulator-name = "vdda"; + regulator-always-on; regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; interrupts = ; @@ -168,8 +336,6 @@ vdd_usb: ldo4 { regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; interrupts = ; }; @@ -191,24 +357,23 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; - bst_out: boost { + bst_out: boost { regulator-name = "bst_out"; interrupts = ; - }; + }; vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = ; - }; + }; - vbus_sw: pwr_sw2 { + vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; - regulator-active-discharge; - }; + regulator-active-discharge = <1>; + }; }; onkey { @@ -225,21 +390,20 @@ }; }; - eeprom0: eeprom@50 { + touchscreen@49 { + compatible = "ti,tsc2004"; + reg = <0x49>; + vio-supply = <&v3v3>; + interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>; + }; + + eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; pagesize = <16>; }; }; -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - &ipcc { status = "okay"; }; @@ -250,8 +414,12 @@ }; &m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; status = "okay"; }; @@ -260,42 +428,6 @@ vdd_3v3_usbfs-supply = <&vdd_usb>; }; -&pinctrl { - ethernet0_rmii_pins_a: rmii-0 { - pins1 { - pinmux = , /* ETH1_RMII_TXD0 */ - , /* ETH1_RMII_TXD1 */ - , /* ETH1_RMII_TX_EN */ - , /* ETH1_RMII_REF_CLK */ - , /* ETH1_MDIO */ - ; /* ETH1_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = , /* ETH1_RMII_RXD0 */ - , /* ETH1_RMII_RXD1 */ - ; /* ETH1_RMII_CRS_DV */ - bias-disable; - }; - }; - - ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { - pins1 { - pinmux = , /* ETH1_RMII_TXD0 */ - , /* ETH1_RMII_TXD1 */ - , /* ETH1_RMII_TX_EN */ - , /* ETH1_MDIO */ - , /* ETH1_MDC */ - , /* ETH1_RMII_RXD0 */ - , /* ETH1_RMII_RXD1 */ - , /* ETH1_RMII_REF_CLK */ - ; /* ETH1_RMII_CRS_DV */ - }; - }; -}; - &qspi { pinctrl-names = "default", "sleep"; pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; @@ -305,7 +437,7 @@ #size-cells = <0>; status = "okay"; - flash0: mx66l51235l@0 { + flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; @@ -324,14 +456,19 @@ }; &sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-names = "default", "opendrain", "sleep", "init"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; + pinctrl-3 = <&sdmmc1_b4_init_pins_a &sdmmc1_dir_init_pins_a>; cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; disable-wp; st,sig-dir; st,neg-edge; + st,use-ckin; + st,cmd-gpios = <&gpiod 2 0>; + st,ck-gpios = <&gpioc 12 0>; + st,ckin-gpios = <&gpioe 4 0>; bus-width = <4>; vmmc-supply = <&vdd_sd>; status = "okay"; @@ -352,75 +489,33 @@ }; &sdmmc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; non-removable; no-sd; no-sdio; - st,sig-dir; st,neg-edge; bus-width = <8>; vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; status = "okay"; }; -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - status = "disabled"; -}; - -&timers2 { - /* spare dmas for other usage (un-delete to enable pwm capture) */ - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm2_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - timer@1 { - status = "okay"; - }; -}; - -&timers6 { +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - timer@5 { - status = "okay"; - }; -}; - -&timers8 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm8_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - timer@7 { - status = "okay"; - }; -}; - -&timers12 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm12_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - timer@11 { - status = "okay"; - }; }; &uart4 { @@ -428,29 +523,3 @@ pinctrl-0 = <&uart4_pins_a>; status = "okay"; }; - -&usbh_ehci { - phys = <&usbphyc_port0>; - phy-names = "usb"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "peripheral"; - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - vbus-supply = <&vbus_otg>; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 5b2b09bcfb..f09f4290f6 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -9,6 +9,8 @@ #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi" #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi" +/delete-node/ &ksz8851; + / { aliases { i2c1 = &i2c2; @@ -18,7 +20,8 @@ mmc1 = &sdmmc2; spi0 = &qspi; usb0 = &usbotg_hs; - ethernet1 = &ksz8851; + eeprom0 = &eeprom0; + ethernet1 = &ks8851; }; config { @@ -30,28 +33,34 @@ dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>; }; - led { - red { - label = "error"; - gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - status = "okay"; - }; - - blue { - default-state = "on"; - }; - }; - /* This is actually on FMC2, but we do not have bus driver for that */ - ksz8851: ks8851mll@64000000 { + ks8851: ks8851mll@64000000 { compatible = "micrel,ks8851-mll"; reg = <0x64000000 0x20000>; }; }; +ðernet0 { + phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + /delete-property/ st,eth-ref-clk-sel; +}; + +ðernet0_rmii_pins_a { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_REF_CLK */ + , /* ETH1_MDIO */ + ; /* ETH1_MDC */ + }; +}; + &i2c4 { u-boot,dm-pre-reloc; + + eeprom0: eeprom@50 { + }; }; &i2c4_pins_a { @@ -61,6 +70,10 @@ }; }; +&phy0 { + /delete-property/ reset-gpios; +}; + &pinctrl { /* These should bound to FMC2 bus driver, but we do not have one */ pinctrl-0 = <&fmc_pins_b &mco2_pins_a>; From 6ddc71c13e1b78560d3869bc394144e91972e44f Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 11 Jan 2022 15:58:08 +0100 Subject: [PATCH 08/11] stm32mp: fix board_get_alt_info_mmc() MAX_SEARCH_PARTITIONS is the highest possible partition number. Do not skip the last partition in board_get_alt_info_mmc(). Signed-off-by: Heinrich Schuchardt Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- board/st/common/stm32mp_dfu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c index a3f0da5b5b..fa48b2a35e 100644 --- a/board/st/common/stm32mp_dfu.c +++ b/board/st/common/stm32mp_dfu.c @@ -57,7 +57,7 @@ static void board_get_alt_info_mmc(struct udevice *dev, char *buf) first = false; } - for (p = 1; p < MAX_SEARCH_PARTITIONS; p++) { + for (p = 1; p <= MAX_SEARCH_PARTITIONS; p++) { if (part_get_info(desc, p, &info)) continue; if (!first) From 046bdb806407976cabce77eb304bb29fa70180f0 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 11 Jan 2022 16:37:21 +0100 Subject: [PATCH 09/11] board: stm32mp1: solve compilation issue when ENV_IS_IN_MMC is deactivated Solve compilation issue on undefined CONFIG_SYS_MMC_ENV_DEV when CONFIG_ENV_IS_IN_MMC is deactivated on STMicroelectronics boards defconfig Fixes: 9f97193616f1 ("board: stm32mp1: use CONFIG_SYS_MMC_ENV_DEV when available") Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- board/st/stm32mp1/stm32mp1.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 45f2ca81a6..fff1880e5b 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -890,8 +890,10 @@ const char *env_ext4_get_dev_part(void) int mmc_get_env_dev(void) { - if (CONFIG_SYS_MMC_ENV_DEV >= 0) - return CONFIG_SYS_MMC_ENV_DEV; + const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_SYS_MMC_ENV_DEV), (-1)); + + if (mmc_env_dev >= 0) + return mmc_env_dev; /* use boot instance to select the correct mmc device identifier */ return mmc_get_boot(); From 94e561f84af579dacdfccfd44aedb7c0dcc26081 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 18 Jan 2022 10:33:14 +0100 Subject: [PATCH 10/11] stm32prog: add partition name in treat_partition_list error messages Add the partition name and remove the line number in error messages of treat_partition_list() to provide correct information to user of STM32CubeProgrammer. The "line number" value was confusing because it is incorrect here; the index in part_array[] is not aligned with the line number in the parsed Layout file, because the empty lines and the lines beginning by '#' are skipped during the first parsing in parse_flash_layout(). Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 3b6ca4e773..61cba157fd 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -835,8 +835,8 @@ static int treat_partition_list(struct stm32prog_data *data) /* skip partition with IP="none" */ if (part->target == STM32PROG_NONE) { if (IS_SELECT(part)) { - stm32prog_err("Layout: selected none phase = 0x%x", - part->id); + stm32prog_err("Layout: selected none phase = 0x%x for part %s", + part->id, part->name); return -EINVAL; } continue; @@ -844,14 +844,14 @@ static int treat_partition_list(struct stm32prog_data *data) if (part->id == PHASE_FLASHLAYOUT || part->id > PHASE_LAST_USER) { - stm32prog_err("Layout: invalid phase = 0x%x", - part->id); + stm32prog_err("Layout: invalid phase = 0x%x for part %s", + part->id, part->name); return -EINVAL; } for (j = i + 1; j < data->part_nb; j++) { if (part->id == data->part_array[j].id) { - stm32prog_err("Layout: duplicated phase 0x%x at line %d and %d", - part->id, i, j); + stm32prog_err("Layout: duplicated phase 0x%x for part %s and %s", + part->id, part->name, data->part_array[j].name); return -EINVAL; } } From 22c0815ecaa538de51a5204caceec850d5965126 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 20 Jan 2022 08:19:15 +0100 Subject: [PATCH 11/11] configs: stm32mp15: Enable OF_BOARD flag Since commit 985503439762 ("fdt: Don't call board_fdt_blob_setup() without OF_BOARD") board_fdt_blob_setup() is no more called on STM32MP platforms in trusted boot which hangs during boot process. Enable OF_BOARD flag to fix this issue. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/mach-stm32mp/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 811c0fc261..e48f98ba29 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -40,6 +40,7 @@ config STM32MP15x select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT + select OF_BOARD if TFABOOT select OF_BOARD_SETUP select PINCTRL_STM32 select STM32_RCC