sh: Add support 32-Bit Extended Address Mode to sh7785lcr
We can built 'make sh7785lcr_32bit_config'. And add new command "pmb" for this mode. This command changes PMB for using 512MB system memory. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Yoshihiro Shimoda
Nobuhiro Iwamatsu
parent
06b18163b5
commit
ada9318252
15
Makefile
15
Makefile
@ -3398,10 +3398,23 @@ sh7763rdp_config : unconfig
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@echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h
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@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7763rdp renesas
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xtract_sh7785lcr = $(subst _32bit,,$(subst _config,,$1))
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sh7785lcr_32bit_config \
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sh7785lcr_config : unconfig
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@ >include/config.h
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@echo "#define CONFIG_SH7785LCR 1" >> include/config.h
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@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7785lcr renesas
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@if [ "$(findstring 32bit, $@)" ] ; then \
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echo "#define CONFIG_SH_32BIT 1" >> $(obj)include/config.h ; \
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cp $(obj)board/renesas/sh7785lcr/u-boot_32bit \
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$(obj)board/renesas/sh7785lcr/u-boot.lds ; \
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echo "TEXT_BASE = 0x8ff80000" > \
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$(obj)board/renesas/sh7785lcr/config.tmp ; \
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$(XECHO) " ... enable 32-Bit Address Extended Mode" ; \
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else \
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cp $(obj)board/renesas/sh7785lcr/u-boot_29bit \
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$(obj)board/renesas/sh7785lcr/u-boot.lds ; \
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fi
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@$(MKCONFIG) -a $(call xtract_sh7785lcr,$@) sh sh4 sh7785lcr renesas
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ap325rxa_config : unconfig
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@mkdir -p $(obj)include
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@ -22,4 +22,8 @@
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#
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# NOTE: Must match value used in u-boot.lds (in this directory).
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#
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sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
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ifndef TEXT_BASE
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TEXT_BASE = 0x0ff80000
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endif
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@ -130,6 +130,46 @@ lbsc_29bit:
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write32 CS6WCR_A, CS_SD_WCR_D
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lbsc_end:
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#if defined(CONFIG_SH_32BIT)
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/*------- set PMB -------*/
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write32 PASCR_A, PASCR_29BIT_D
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write32 MMUCR_A, MMUCR_D
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/*****************************************************************
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* ent virt phys v sz c wt
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* 0 0xa0000000 0x00000000 1 64M 0 0
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* 1 0xa4000000 0x04000000 1 16M 0 0
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* 2 0xa6000000 0x08000000 1 16M 0 0
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* 9 0x88000000 0x48000000 1 128M 1 1
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* 10 0x90000000 0x50000000 1 128M 1 1
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* 11 0x98000000 0x58000000 1 128M 1 1
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* 13 0xa8000000 0x48000000 1 128M 0 0
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* 14 0xb0000000 0x50000000 1 128M 0 0
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* 15 0xb8000000 0x58000000 1 128M 0 0
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*/
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write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D
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write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D
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write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D
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write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D
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write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D
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write32 PMB_DATA_USB_A, PMB_DATA_USB_D
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write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
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write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
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write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D
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write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D
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write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D
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write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D
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write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
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write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
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write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D
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write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D
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write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D
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write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D
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write32 PASCR_A, PASCR_INIT
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mov.l DUMMY_ADDR, r0
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icbi @r0
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#endif
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write32 CCR_A, CCR_D
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@ -140,7 +180,11 @@ lbsc_end:
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/*------- LBSC -------*/
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MMSELR_A: .long 0xfc400020
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#if defined(CONFIG_SH_32BIT)
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MMSELR_D: .long 0xa5a50005
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#else
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MMSELR_D: .long 0xa5a50002
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#endif
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/*------- DBSC2 -------*/
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#define DBSC2_BASE 0xfe800000
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@ -287,5 +331,55 @@ CS_SD_WCR_D: .long 0x00030108
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CS_I2C_BCR_D: .long 0x11111100
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CS_I2C_WCR_D: .long 0x00000003
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#if defined(CONFIG_SH_32BIT)
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/*------- set PMB -------*/
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PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0)
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PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1)
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PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2)
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PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9)
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PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10)
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PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11)
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PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13)
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PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14)
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PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15)
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PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0)
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PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4)
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PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6)
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PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
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PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90)
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PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98)
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PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
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PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0)
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PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8)
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PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0)
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PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1)
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PMB_DATA_USB_A: .long PMB_DATA_BASE(2)
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PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9)
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PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10)
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PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11)
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PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13)
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PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14)
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PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15)
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/* ppn ub v s1 s0 c wt */
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PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
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PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
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PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
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PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
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PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
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PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
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PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
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PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
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PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
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DUMMY_ADDR: .long 0xa0000000
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PASCR_29BIT_D: .long 0x00000000
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PASCR_INIT: .long 0x80000080 /* check booting mode */
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MMUCR_A: .long 0xff000010
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MMUCR_D: .long 0x00000004 /* clear ITLB */
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#endif /* CONFIG_SH_32BIT */
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CCR_A: .long 0xff00001c
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CCR_D: .long 0x0000090b
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@ -54,3 +54,35 @@ int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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#if defined(CONFIG_SH_32BIT)
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int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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/* clear ITLB */
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writel(0x00000004, 0xff000010);
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/* delete PMB for peripheral */
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writel(0, PMB_ADDR_BASE(0));
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writel(0, PMB_DATA_BASE(0));
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writel(0, PMB_ADDR_BASE(1));
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writel(0, PMB_DATA_BASE(1));
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writel(0, PMB_ADDR_BASE(2));
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writel(0, PMB_DATA_BASE(2));
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/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
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writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8));
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writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8));
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writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12));
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writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12));
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return 0;
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}
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U_BOOT_CMD(
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pmb, 1, 1, do_pmb,
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"pmb - PMB setting\n",
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"\n"
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" - PMB setting for all SDRAM mapping\n"
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);
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#endif
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@ -1,7 +1,7 @@
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/*
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* Copyrigth (c) 2007
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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* Copyrigth (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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* Copyrigth (c) 2008-2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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@ -28,7 +28,7 @@ ENTRY(_start)
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SECTIONS
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{
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. = 0x08000000 + (128 * 1024 * 1024) - (512 * 1024);
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. = 0x88000000 + (128 * 1024 * 1024) - (512 * 1024);
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PROVIDE (reloc_dst = .);
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96
board/renesas/sh7785lcr/u-boot_29bit
Normal file
96
board/renesas/sh7785lcr/u-boot_29bit
Normal file
@ -0,0 +1,96 @@
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/*
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* Copyrigth (c) 2007
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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* Copyrigth (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
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OUTPUT_ARCH(sh)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x08000000 + (128 * 1024 * 1024) - (512 * 1024);
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PROVIDE (reloc_dst = .);
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PROVIDE (_ftext = .);
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PROVIDE (_fcode = .);
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PROVIDE (_start = .);
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.text :
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{
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cpu/sh4/start.o (.text)
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. = ALIGN(8192);
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common/env_embedded.o (.ppcenv)
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. = ALIGN(8192);
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common/env_embedded.o (.ppcenvr)
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. = ALIGN(8192);
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*(.text)
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. = ALIGN(4);
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} =0xFF
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PROVIDE (_ecode = .);
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.rodata :
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{
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*(.rodata)
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. = ALIGN(4);
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}
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PROVIDE (_etext = .);
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PROVIDE (_fdata = .);
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.data :
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{
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*(.data)
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. = ALIGN(4);
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}
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PROVIDE (_edata = .);
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PROVIDE (_fgot = .);
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.got :
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{
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*(.got)
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. = ALIGN(4);
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}
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PROVIDE (_egot = .);
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PROVIDE (__u_boot_cmd_start = .);
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.u_boot_cmd :
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{
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*(.u_boot_cmd)
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. = ALIGN(4);
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}
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PROVIDE (__u_boot_cmd_end = .);
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PROVIDE (reloc_dst_end = .);
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/* _reloc_dst_end = .; */
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PROVIDE (bss_start = .);
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PROVIDE (__bss_start = .);
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.bss :
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{
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*(.bss)
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. = ALIGN(4);
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}
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PROVIDE (bss_end = .);
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PROVIDE (_end = .);
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}
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96
board/renesas/sh7785lcr/u-boot_32bit
Normal file
96
board/renesas/sh7785lcr/u-boot_32bit
Normal file
@ -0,0 +1,96 @@
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/*
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* Copyrigth (c) 2007
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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* Copyrigth (c) 2008-2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
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*/
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OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
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OUTPUT_ARCH(sh)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x88000000 + (128 * 1024 * 1024) - (512 * 1024);
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PROVIDE (reloc_dst = .);
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PROVIDE (_ftext = .);
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PROVIDE (_fcode = .);
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PROVIDE (_start = .);
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|
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.text :
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{
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cpu/sh4/start.o (.text)
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. = ALIGN(8192);
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common/env_embedded.o (.ppcenv)
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. = ALIGN(8192);
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common/env_embedded.o (.ppcenvr)
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. = ALIGN(8192);
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*(.text)
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. = ALIGN(4);
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} =0xFF
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PROVIDE (_ecode = .);
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.rodata :
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{
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*(.rodata)
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. = ALIGN(4);
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}
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PROVIDE (_etext = .);
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PROVIDE (_fdata = .);
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.data :
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{
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*(.data)
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. = ALIGN(4);
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}
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PROVIDE (_edata = .);
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PROVIDE (_fgot = .);
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.got :
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{
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*(.got)
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. = ALIGN(4);
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}
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PROVIDE (_egot = .);
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PROVIDE (__u_boot_cmd_start = .);
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.u_boot_cmd :
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{
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*(.u_boot_cmd)
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. = ALIGN(4);
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}
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PROVIDE (__u_boot_cmd_end = .);
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PROVIDE (reloc_dst_end = .);
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/* _reloc_dst_end = .; */
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PROVIDE (bss_start = .);
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PROVIDE (__bss_start = .);
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.bss :
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{
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*(.bss)
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. = ALIGN(4);
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}
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PROVIDE (bss_end = .);
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PROVIDE (_end = .);
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}
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@ -33,6 +33,38 @@ This board has 2 physical memory maps. It can be changed with DIP switch(S2-5).
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||||
0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
|
||||
|
||||
|
||||
configuration for This board:
|
||||
=============================
|
||||
|
||||
You can choose configuration as follows:
|
||||
|
||||
- make sh7785lcr_config
|
||||
- make sh7785lcr_32bit_config
|
||||
|
||||
When you use "make sh7785lcr_config", there is build U-Boot for 29-bit
|
||||
address mode. This mode can use 128MB DDR-SDRAM.
|
||||
|
||||
When you use "make sh7785lcr_32bit_config", there is build U-Boot for 32-bit
|
||||
extended address mode. This mode can use 384MB DDR-SDRAM. And if you run
|
||||
"pmb" command, this mode can use 512MB DDR-SDRAM.
|
||||
|
||||
* 32-bit extended address mode PMB mapping *
|
||||
a) on start-up
|
||||
virt | phys | size | device
|
||||
-------------+---------------+---------------+---------------
|
||||
0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
|
||||
0xa0000000 | 0x00000000 | 64MB | NOR Flash
|
||||
0xa4000000 | 0x04000000 | 16MB | PLD
|
||||
0xa6000000 | 0x08000000 | 16MB | USB
|
||||
0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable)
|
||||
|
||||
b) after "pmb" command
|
||||
virt | phys | size | device
|
||||
-------------+---------------+---------------+---------------
|
||||
0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable)
|
||||
0xa0000000 | 0x40000000 | 512MB | DDR-SDRAM (Non-cacheable)
|
||||
|
||||
|
||||
This board specific command:
|
||||
============================
|
||||
|
||||
@ -41,6 +73,7 @@ This board has the following its specific command:
|
||||
- hwtest
|
||||
- printmac
|
||||
- setmac
|
||||
- pmb (sh7785lcr_32bit_config only)
|
||||
|
||||
|
||||
1. hwtest
|
||||
@ -80,3 +113,11 @@ This command writes MAC address of this board.
|
||||
|
||||
i.e)
|
||||
=> setmac 00:00:87:**:**:**
|
||||
|
||||
|
||||
4. pmb
|
||||
|
||||
This command change PMB for DDR-SDRAM all mapping. However you cannot use
|
||||
NOR Flash and USB Host on U-Boot when you run this command.
|
||||
i.e)
|
||||
=> pmb
|
||||
|
||||
@ -61,11 +61,20 @@
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
/* MEMORY */
|
||||
#if defined(CONFIG_SH_32BIT)
|
||||
#define SH7785LCR_SDRAM_PHYS_BASE (0x48000000)
|
||||
#define SH7785LCR_SDRAM_BASE (0x88000000)
|
||||
#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
|
||||
#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
|
||||
#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
|
||||
#define SH7785LCR_USB_BASE (0xa6000000)
|
||||
#else
|
||||
#define SH7785LCR_SDRAM_BASE (0x08000000)
|
||||
#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
|
||||
#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
|
||||
#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
|
||||
#define SH7785LCR_USB_BASE (0xb4000000)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_PROMPT "=> "
|
||||
@ -133,9 +142,15 @@
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_SH4_PCI
|
||||
#define CONFIG_SH7780_PCI
|
||||
#if defined(CONFIG_SH_32BIT)
|
||||
#define CONFIG_SH7780_PCI_LSR 0x1ff00001
|
||||
#define CONFIG_SH7780_PCI_LAR 0x5f000000
|
||||
#define CONFIG_SH7780_PCI_BAR 0x5f000000
|
||||
#else
|
||||
#define CONFIG_SH7780_PCI_LSR 0x07f00001
|
||||
#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
|
||||
#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
|
||||
#endif
|
||||
#define CONFIG_PCI_PNP
|
||||
#define CONFIG_PCI_SCAN_SHOW 1
|
||||
|
||||
@ -147,8 +162,12 @@
|
||||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
|
||||
#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
|
||||
|
||||
#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
|
||||
#if defined(CONFIG_SH_32BIT)
|
||||
#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE
|
||||
#else
|
||||
#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
|
||||
#endif
|
||||
#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
|
||||
|
||||
/* Network device (RTL8169) support */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user