From a0018fc8209c0bf7188592527fc0a7d459b9c144 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 19 Jul 2020 23:17:07 -0700 Subject: [PATCH 01/19] riscv: Make SiFive HiFive Unleashed board boot again Commit 40686c394e53 ("riscv: Clean up IPI initialization code") caused U-Boot failed to boot on SiFive HiFive Unleashed board. The codes inside arch_cpu_init_dm() may call U-Boot timer APIs before the call to riscv_init_ipi(). At that time the timer register base (e.g.: the SiFive CLINT device in this case) is unknown yet. It might be the name riscv_init_ipi() that misleads people to only consider it is related to IPI, but in fact the timer capability is provided by the same SiFive CLINT device that provides the IPI. Timer capability is needed for both UP and SMP. Considering that the original refactor does have benefits, that it makes the IPI code more similar to U-Boot initialization idioms. It also removes some quite ugly macros. Let's do the minimal revert instead of a complete revert, plus a fixes to arch_cpu_init_dm() to consider the SPL case. Fixes: 40686c394e53 ("riscv: Clean up IPI initialization code") Signed-off-by: Bin Meng Reviewed-by: Sean Anderson Tested-by: Leo Liang --- arch/riscv/cpu/cpu.c | 2 +- arch/riscv/lib/sifive_clint.c | 16 ++++++++++++---- common/spl/spl_opensbi.c | 5 ----- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index bbd6c15352..bfa2d4a426 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -107,7 +107,7 @@ int arch_cpu_init_dm(void) #endif } -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) ret = riscv_init_ipi(); if (ret) return ret; diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c index 78fc6c868d..b9a2c649cc 100644 --- a/arch/riscv/lib/sifive_clint.c +++ b/arch/riscv/lib/sifive_clint.c @@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR; int riscv_get_time(u64 *time) { + /* ensure timer register base has a sane value */ + riscv_init_ipi(); + *time = readq((void __iomem *)MTIME_REG(gd->arch.clint)); return 0; @@ -33,6 +36,9 @@ int riscv_get_time(u64 *time) int riscv_set_timecmp(int hart, u64 cmp) { + /* ensure timer register base has a sane value */ + riscv_init_ipi(); + writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); return 0; @@ -40,11 +46,13 @@ int riscv_set_timecmp(int hart, u64 cmp) int riscv_init_ipi(void) { - long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT); + if (!gd->arch.clint) { + long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT); - if (IS_ERR(ret)) - return PTR_ERR(ret); - gd->arch.clint = ret; + if (IS_ERR(ret)) + return PTR_ERR(ret); + gd->arch.clint = ret; + } return 0; } diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index 3440bc0294..14f335f75f 100644 --- a/common/spl/spl_opensbi.c +++ b/common/spl/spl_opensbi.c @@ -79,11 +79,6 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) invalidate_icache_all(); #ifdef CONFIG_SPL_SMP - /* Initialize the IPI before we use it */ - ret = riscv_init_ipi(); - if (ret) - hang(); - /* * Start OpenSBI on all secondary harts and wait for acknowledgment. * From 3d5ac3536be97a679763e261c55167bfd356a412 Mon Sep 17 00:00:00 2001 From: Pragnesh Patel Date: Fri, 29 May 2020 12:14:52 +0530 Subject: [PATCH 02/19] riscv: sifive: fu540: Enable SiFive PWM driver This patch enables SiFive PWM driver for the SiFive Unleashed board. Signed-off-by: Pragnesh Patel Reviewed-by: Bin Meng --- board/sifive/fu540/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index 86193d7668..683668d059 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -65,5 +65,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SMP imply MISC imply SIFIVE_OTP + imply DM_PWM + imply PWM_SIFIVE endif From 868e295ef72535300037fc264e770cfdca3f5894 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 15 Jul 2020 15:38:58 +0530 Subject: [PATCH 03/19] sifive: fu540: Add runtime boot mode detection Add support to detect boot mode at runtime for SiFive FU540 boards. Signed-off-by: Jagan Teki Reviewed-by: Bin Meng Tested-by: Bin Meng --- board/sifive/fu540/fu540.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c index 27ff52f903..57753ba50b 100644 --- a/board/sifive/fu540/fu540.c +++ b/board/sifive/fu540/fu540.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -128,14 +129,26 @@ int board_init(void) } #ifdef CONFIG_SPL +#define MODE_SELECT_REG 0x1000 +#define MODE_SELECT_QSPI 0x6 +#define MODE_SELECT_SD 0xb +#define MODE_SELECT_MASK GENMASK(3, 0) + u32 spl_boot_device(void) { -#ifdef CONFIG_SPL_MMC_SUPPORT - return BOOT_DEVICE_MMC1; -#else - puts("Unknown boot device\n"); - hang(); -#endif + u32 mode_select = readl((void *)MODE_SELECT_REG); + u32 boot_device = mode_select & MODE_SELECT_MASK; + + switch (boot_device) { + case MODE_SELECT_QSPI: + return BOOT_DEVICE_SPI; + case MODE_SELECT_SD: + return BOOT_DEVICE_MMC1; + default: + debug("Unsupported boot device 0x%x but trying MMC1\n", + boot_device); + return BOOT_DEVICE_MMC1; + } } #endif From 4243ff11fe73bef0d60b2a48c8663e02975ebb6b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 15 Jul 2020 15:38:59 +0530 Subject: [PATCH 04/19] sifive: fu540: Add Booting from SPI Add booting from SPI for SiFive Unleashed board. Signed-off-by: Jagan Teki Reviewed-by: Bin Meng Tested-by: Bin Meng --- .../dts/hifive-unleashed-a00-u-boot.dtsi | 12 ++++++ configs/sifive_fu540_defconfig | 4 ++ doc/board/sifive/fu540.rst | 41 +++++++++++++++++++ 3 files changed, 57 insertions(+) diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi index e037150520..7d838bf9de 100644 --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -16,6 +16,10 @@ spi2 = &qspi2; }; + config { + u-boot,spl-payload-offset = <0x105000>; /* loader2 @1044KB */ + }; + hfclk { u-boot,dm-spl; }; @@ -26,6 +30,14 @@ }; +&qspi0 { + u-boot,dm-spl; + + flash@0 { + u-boot,dm-spl; + }; +}; + &qspi2 { mmc@0 { u-boot,dm-spl; diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig index 9e00a56ce6..06e17860c6 100644 --- a/configs/sifive_fu540_defconfig +++ b/configs/sifive_fu540_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_DM_SPI=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_TARGET_SIFIVE_FU540=y CONFIG_ARCH_RV64I=y @@ -16,8 +17,11 @@ CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00" CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_CLK=y CONFIG_DM_MTD=y diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst index 739eefa669..1ce9ab14f5 100644 --- a/doc/board/sifive/fu540.rst +++ b/doc/board/sifive/fu540.rst @@ -533,3 +533,44 @@ Sample boot log from HiFive Unleashed board type: 0fc63daf-8483-4772-8e79-3d69d8477de4 type: linux guid: 9faa81b6-39b1-4418-af5e-89c48f29c20d + +Booting from SPI +---------------- + +Use Building steps from "Booting from MMC using U-Boot SPL" section. + +Partition the SPI in Linux via mtdblock. (Require to boot the board in +SD boot mode by enabling MTD block in Linux) + +Use prebuilt image from here [1], which support to partition the SPI flash. + +.. code-block:: none + + # sgdisk --clear \ + > --set-alignment=2 \ + > --new=1:40:2087 --change-name=1:loader1 --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \ + > --new=2:2088:10279 --change-name=2:loader2 --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \ + > --new=3:10536:65494 --change-name=3:rootfs --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \ + > /dev/mtdblock0 + +Program the SPI (Require to boot the board in SD boot mode) + +Execute below steps on U-Boot proper, + +.. code-block:: none + + tftpboot $kernel_addr_r u-boot-spl.bin + sf erase 0x5000 $filesize + sf write $kernel_addr_r 0x5000 $filesize + + tftpboot $kernel_addr_r u-boot.itb + sf erase 0x105000 $filesize + sf write $kernel_addr_r 0x105000 $filesize + +Power off the board + +Change DIP switches MSEL[3:0] are set to 0110 + +Power up the board. + +[1] https://github.com/amarula/bsp-sifive From ff7d25e8db8de47dea4c6850b6a3a642a2d8befd Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 15 Jul 2020 15:39:00 +0530 Subject: [PATCH 05/19] env: Enable SPI flash env for SiFive FU540 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SPI flash device on HiFive Unleashed has 32MiB Size. This patch adds SPI flash environment after U-Boot proper partition with a size of 128KiB. SPI flash partition layout(32MiB): 0 - 34 : reserved for GPT header 35 - 39 : unused 40 - 2087 : loader1 (SPL, FSBL) 2088 - 10279 : loader2 (U-Boot proper, U-Boot) 10280 - 10535 : environment 10536 - 65494 : rootfs 65528 - 65536 : distro script Note: the loader1 must start from 40th sector even though there are 6 free sectors prior since 40th sector is nearest flash sector boundary.  Signed-off-by: Jagan Teki Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/riscv/cpu/fu540/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig index e9302e87c0..2dcad8e27f 100644 --- a/arch/riscv/cpu/fu540/Kconfig +++ b/arch/riscv/cpu/fu540/Kconfig @@ -13,3 +13,16 @@ config SIFIVE_FU540 imply SPL_CPU_SUPPORT imply SPL_OPENSBI imply SPL_LOAD_FIT + +if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x505000 + +config ENV_SIZE + default 0x20000 + +config ENV_SECT_SIZE + default 0x10000 + +endif # ENV_IS_IN_SPI_FLASH From 662d518e8a547038494a7e9bf50d58195174a4ef Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 15 Jul 2020 15:39:01 +0530 Subject: [PATCH 06/19] sifive: fu540: Mark the default env as SPI flash Mark the default U-Boot environment as SPI flash since this is an on board flash device. Reviewed-by: Bin Meng Signed-off-by: Jagan Teki Reviewed-by: Bin Meng Tested-by: Bin Meng --- board/sifive/fu540/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index 683668d059..4aa1e4c19d 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SIFIVE_FU540 select SUPPORT_SPL + select ENV_IS_IN_SPI_FLASH select RAM select SPL_RAM if SPL imply CMD_DHCP From ca0f93fb748bcc40e5da70613a92fe3185b58ccd Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 15 Jul 2020 15:39:02 +0530 Subject: [PATCH 07/19] sifive: fu540: Add boot flash script offset, size HiFive-Unleashed-A00 has SPI flash with 32MiB size. So, let's use the script offset at the end of 4K. This way it cannot overlap any offsets being used by software components in flash layout. So, SF distrocmd will pick the script at desired script address and run. Signed-off-by: Jagan Teki Reviewed-by: Bin Meng --- include/configs/sifive-fu540.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h index 72c841eb9b..68fda14d76 100644 --- a/include/configs/sifive-fu540.h +++ b/include/configs/sifive-fu540.h @@ -62,6 +62,8 @@ "kernel_addr_r=0x84000000\0" \ "fdt_addr_r=0x88000000\0" \ "scriptaddr=0x88100000\0" \ + "script_offset_f=0x1fff000\0" \ + "script_size_f=0x1000\0" \ "pxefile_addr_r=0x88200000\0" \ "ramdisk_addr_r=0x88300000\0" \ "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ From 2270ae63884fd68f0b63b5ce7ecf4ba44b5e87cf Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 15 Jul 2020 15:39:03 +0530 Subject: [PATCH 08/19] sifive: fu540: Enable SF distro bootcmd Enable SPI flash(SF) distro boot command in Sifive FU540. This distro boot will read the boot script at specific location at the flash and start sourcing the same. Included the SF device at the last of the target devices list since all the rest of the devices on the list have more possibility to boot the distribution due to the size of the SPI flash is concern. Signed-off-by: Jagan Teki Reviewed-by: Bin Meng --- include/configs/sifive-fu540.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h index 68fda14d76..f21411a701 100644 --- a/include/configs/sifive-fu540.h +++ b/include/configs/sifive-fu540.h @@ -43,9 +43,11 @@ #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ + func(SF, sf, 0) \ func(DHCP, dhcp, na) #include +#include #define TYPE_GUID_LOADER1 "5B193300-FC78-40CD-8002-E86C45580B47" #define TYPE_GUID_LOADER2 "2E54B353-1271-4842-806F-E436D6AF6985" @@ -70,7 +72,8 @@ "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ "partitions=" PARTS_DEFAULT "\0" \ - BOOTENV + BOOTENV \ + BOOTENV_SF #define CONFIG_PREBOOT \ "setenv fdt_addr ${fdtcontroladdr};" \ From d20d0a57778619d779646ab71d64ec9977408ea3 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 19 Jul 2020 20:52:23 -0700 Subject: [PATCH 09/19] azure: gitlab: travis: Update OpenSBI used for RISC-V testing Change to use OpenSBI release v0.8 generic platform images for QEMU RISC-V CI testing for azure, gitlab and travis-ci. Signed-off-by: Bin Meng Reviewed-by: Tom Rini --- .azure-pipelines.yml | 8 ++++---- .gitlab-ci.yml | 8 ++++---- .travis.yml | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 3e52f32890..9ba9f1d43e 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -295,12 +295,12 @@ jobs: grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.6/opensbi-0.6-rv32-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.6-rv32-bin/platform/qemu/virt/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.6/opensbi-0.6-rv64-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.6-rv64-bin/platform/qemu/virt/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi # the below corresponds to .gitlab-ci.yml "script" cd ${WORK_DIR} diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 6c8a323ad3..43f9d3bb14 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -21,12 +21,12 @@ stages: - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.6/opensbi-0.6-rv32-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.6-rv32-bin/platform/qemu/virt/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.6/opensbi-0.6-rv64-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.6-rv64-bin/platform/qemu/virt/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi after_script: diff --git a/.travis.yml b/.travis.yml index 9438bd13cf..73daf273c5 100644 --- a/.travis.yml +++ b/.travis.yml @@ -204,12 +204,12 @@ before_script: popd; fi - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.6/opensbi-0.6-rv32-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.6-rv32-bin/platform/qemu/virt/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.6/opensbi-0.6-rv64-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.6-rv64-bin/platform/qemu/virt/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi script: From 6b62495026ea650221a365fd32756c60c2633390 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 19 Jul 2020 20:06:45 -0700 Subject: [PATCH 10/19] Revert "riscv: Allow use of reset drivers" This reverts commit 958a3f464c7f8ef7e10db9feb663e9e80445ce2f. A more appropriate change below is already in mainline. Commit fd31e4fd184f ("riscv: Do not build reset.c if SYSRESET is on") Revert this patch, so that U-Boot can be built successfully for SiFive Fu540 board. Signed-off-by: Bin Meng Reviewed-by: Sean Anderson Reviewed-by: Leo Liang --- arch/riscv/lib/reset.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c index 6008bbe78e..8779c619cc 100644 --- a/arch/riscv/lib/reset.c +++ b/arch/riscv/lib/reset.c @@ -7,7 +7,6 @@ #include #include -#ifndef CONFIG_SYSRESET int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { printf("resetting ...\n"); @@ -17,4 +16,3 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return 0; } -#endif From 265d46ba137c59f83c9d2c86900960415292dbed Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 19 Jul 2020 20:06:46 -0700 Subject: [PATCH 11/19] Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"" This reverts commit 23da3c682a84a2ad67a67287979dd4f5259ff607. Now the build failure of sifive_fu540_defconfig board has been fixed, revert this "revert patch". Signed-off-by: Bin Meng --- board/sifive/fu540/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index 4aa1e4c19d..f3217f62c4 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -68,5 +68,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SIFIVE_OTP imply DM_PWM imply PWM_SIFIVE + imply SYSRESET + imply SYSRESET_GPIO endif From 1ce8182b0f7254d0d01e309341c35bbc1b8c10e4 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 22 Jun 2020 22:29:42 -0700 Subject: [PATCH 12/19] sysreset: syscon: Don't assume default value for offset and mask property Per the DT binding, is a required property. Let's abort the probe if it is missing. For the property, current codes assume a default value of zero, which is not correct either. Signed-off-by: Bin Meng Reviewed-by: Simon Glass Reviewed-by: Pragnesh Patel --- drivers/sysreset/sysreset_syscon.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c index f64701aab3..caf24823cc 100644 --- a/drivers/sysreset/sysreset_syscon.c +++ b/drivers/sysreset/sysreset_syscon.c @@ -41,6 +41,7 @@ static struct sysreset_ops syscon_reboot_ops = { int syscon_reboot_probe(struct udevice *dev) { struct syscon_reboot_priv *priv = dev_get_priv(dev); + int err; priv->regmap = syscon_regmap_lookup_by_phandle(dev, "regmap"); if (IS_ERR(priv->regmap)) { @@ -48,8 +49,17 @@ int syscon_reboot_probe(struct udevice *dev) return -ENODEV; } - priv->offset = dev_read_u32_default(dev, "offset", 0); - priv->mask = dev_read_u32_default(dev, "mask", 0); + err = dev_read_u32(dev, "offset", &priv->offset); + if (err) { + pr_err("unable to find offset\n"); + return -ENOENT; + } + + err = dev_read_u32(dev, "mask", &priv->mask); + if (err) { + pr_err("unable to find mask\n"); + return -ENOENT; + } return 0; } From 9cdfade85ebeab73ce001e3dfdb8c529bf3cabed Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 22 Jun 2020 22:29:43 -0700 Subject: [PATCH 13/19] sysreset: syscon: Support value property Per the DT binding, and property can have either one or both, and if is missing, should be used, which is what current U-Boot sysreset_syscon driver supports. This adds support to the property to the driver, and semantics is updated to really be a mask to the value if both exist. Signed-off-by: Bin Meng Reviewed-by: Simon Glass Reviewed-by: Pragnesh Patel --- drivers/sysreset/sysreset_syscon.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c index caf24823cc..1c47486614 100644 --- a/drivers/sysreset/sysreset_syscon.c +++ b/drivers/sysreset/sysreset_syscon.c @@ -19,6 +19,7 @@ struct syscon_reboot_priv { struct regmap *regmap; unsigned int offset; unsigned int mask; + unsigned int value; }; static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type) @@ -29,7 +30,7 @@ static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type) if (type != driver_data) return -EPROTONOSUPPORT; - regmap_write(priv->regmap, priv->offset, priv->mask); + regmap_update_bits(priv->regmap, priv->offset, priv->mask, priv->value); return -EINPROGRESS; } @@ -42,6 +43,7 @@ int syscon_reboot_probe(struct udevice *dev) { struct syscon_reboot_priv *priv = dev_get_priv(dev); int err; + int mask_err, value_err; priv->regmap = syscon_regmap_lookup_by_phandle(dev, "regmap"); if (IS_ERR(priv->regmap)) { @@ -55,10 +57,20 @@ int syscon_reboot_probe(struct udevice *dev) return -ENOENT; } - err = dev_read_u32(dev, "mask", &priv->mask); - if (err) { - pr_err("unable to find mask\n"); - return -ENOENT; + mask_err = dev_read_u32(dev, "mask", &priv->mask); + value_err = dev_read_u32(dev, "value", &priv->value); + if (mask_err && value_err) { + pr_err("unable to find mask and value\n"); + return -EINVAL; + } + + if (value_err) { + /* support old binding */ + priv->value = priv->mask; + priv->mask = 0xffffffff; + } else if (mask_err) { + /* support value without mask*/ + priv->mask = 0xffffffff; } return 0; From a0cc38ab44b0fa8af65632cbea1b13630195f03d Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 22 Jun 2020 22:29:45 -0700 Subject: [PATCH 14/19] riscv: qemu: Add syscon reboot and poweroff support This adds syscon reboot and poweroff support to QEMU RISC-V. Signed-off-by: Bin Meng Reviewed-by: Pragnesh Patel --- board/emulation/qemu-riscv/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index ad99b08b44..617c4aa33f 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -53,5 +53,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply NVME imply SPL_RAM_SUPPORT imply SPL_RAM_DEVICE + imply SYSRESET + imply SYSRESET_SYSCON + imply CMD_POWEROFF + imply SYSRESET_CMD_POWEROFF endif From 27b4a4abe60ef4f42e45cb33075ca37369831588 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 10 Jul 2020 12:41:13 +0200 Subject: [PATCH 15/19] serial: Fix SIFIVE debug serial dependency The commit 4cc24aeaf420 ("serial: Add missing Kconfig dependencies for debug consoles") has added incorrect dependency for SIFIVE debug uart which should depend on SIFIVE driver instead of PL01x. Fixes: 4cc24aeaf420 ("serial: Add missing Kconfig dependencies for debug consoles") Signed-off-by: Michal Simek Reviewed-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Leo Liang Reviewed-by: Sean Anderson --- drivers/serial/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 14df2e9247..e146ffc5f8 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -359,7 +359,7 @@ config DEBUG_UART_SANDBOX config DEBUG_UART_SIFIVE bool "SiFive UART" - depends on PL01X_SERIAL + depends on SIFIVE_SERIAL help Select this to enable a debug UART using the serial_sifive driver. You will need to provide parameters to make this work. The driver will From e491e15a3f4bdf7e22d5e448c3f0cfb733a8dd8b Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Mon, 29 Jun 2020 16:27:28 +0800 Subject: [PATCH 16/19] riscv: Fix linking error when building u-boot-spl with no SMP support Switch off SMP support when building u-boot-spl would cause linking error as follow: undefined reference to 'secondary hart relocate' and 'smp_call_function'. Add macro to wrap up proper code region that needs SMP configuration on. Signed-off by: Leo Liang Cc: rick@andestech.com Reviewed-by: Bin Meng --- arch/riscv/cpu/start.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index f408e41ab9..bf9fdf369b 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -193,6 +193,7 @@ spl_stack_gd_setup: mv sp, s0 #endif +#if CONFIG_IS_ENABLED(SMP) /* set new stack and global data pointer on secondary harts */ spl_secondary_hart_stack_gd_setup: la a0, secondary_hart_relocate @@ -207,6 +208,7 @@ spl_secondary_hart_stack_gd_setup: la a0, secondary_harts_relocation_error jal printf jal hang +#endif /* set new global data pointer on main hart */ 1: mv gp, s0 From e8fa43182a487e7542c49408eb2499cc4c0ed53c Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Fri, 17 Jul 2020 16:24:44 +0800 Subject: [PATCH 17/19] riscv: ae350: Use fdtdec_get_addr_size_auto_noparent to parse smc reg Use fdtdec_get_addr_size_auto_noparent to read the "reg" property instead of fdtdec_get_addr. This will increase the compatibility of dtb parsing. Signed-off-by: Rick Chen Acked-by: Leo Liang Reviewed-by: Bin Meng Tested-by: Leo Liang --- board/AndesTech/ax25-ae350/ax25-ae350.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index add0d56ef2..59a43e4dcc 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -71,7 +71,8 @@ int smc_init(void) if (node < 0) return -FDT_ERR_NOTFOUND; - addr = fdtdec_get_addr(blob, node, "reg"); + addr = fdtdec_get_addr_size_auto_noparent(blob, node, + "reg", 0, NULL, false); if (addr == FDT_ADDR_T_NONE) return -EINVAL; From 142dd57c5d971d3291e8896b5ecd7e878f97e1f1 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 19 Jul 2020 23:06:34 -0700 Subject: [PATCH 18/19] riscv: dts: hifive-unleashed-a00: Make memory node available to SPL Make memory node available to SPL in prepration to updates to SiFive DDR RAM driver to read memory information from DT. Signed-off-by: Bin Meng Reviewed-by: Pragnesh Patel --- arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi index 7d838bf9de..5d0c928b29 100644 --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -20,6 +20,10 @@ u-boot,spl-payload-offset = <0x105000>; /* loader2 @1044KB */ }; + memory@80000000 { + u-boot,dm-spl; + }; + hfclk { u-boot,dm-spl; }; From ecb70bdb9f12b694e3a50895a759119b3fc27507 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 19 Jul 2020 23:06:35 -0700 Subject: [PATCH 19/19] ram: sifive: Avoid using hardcoded ram base and size At present the SiFive FU540 RAM driver uses hard-coded memory base address and size to initialize the DDR controller. This may not be true when this driver is used on another board based on FU540. Update the driver to read the memory information from DT and use that during the initialization. Signed-off-by: Bin Meng Reviewed-by: Leo Liang Reviewed-by: Pragnesh Patel --- drivers/ram/sifive/fu540_ddr.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/ram/sifive/fu540_ddr.c b/drivers/ram/sifive/fu540_ddr.c index f8f8ca9ad5..2eef1e7565 100644 --- a/drivers/ram/sifive/fu540_ddr.c +++ b/drivers/ram/sifive/fu540_ddr.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -39,9 +40,6 @@ #define DENALI_PHY_1152 1152 #define DENALI_PHY_1214 1214 -#define PAYLOAD_DEST 0x80000000 -#define DDR_MEM_SIZE (8UL * 1024UL * 1024UL * 1024UL) - #define DRAM_CLASS_OFFSET 8 #define DRAM_CLASS_DDR4 0xA #define OPTIMAL_RMODW_EN_OFFSET 0 @@ -65,6 +63,8 @@ #define PHY_RX_CAL_DQ0_0_OFFSET 0 #define PHY_RX_CAL_DQ1_0_OFFSET 16 +DECLARE_GLOBAL_DATA_PTR; + struct fu540_ddrctl { volatile u32 denali_ctl[265]; }; @@ -235,8 +235,8 @@ static int fu540_ddr_setup(struct udevice *dev) struct fu540_ddr_params *params = &plat->ddr_params; volatile u32 *denali_ctl = priv->ctl->denali_ctl; volatile u32 *denali_phy = priv->phy->denali_phy; - const u64 ddr_size = DDR_MEM_SIZE; - const u64 ddr_end = PAYLOAD_DEST + ddr_size; + const u64 ddr_size = priv->info.size; + const u64 ddr_end = priv->info.base + ddr_size; int ret, i; u32 physet; @@ -302,7 +302,7 @@ static int fu540_ddr_setup(struct udevice *dev) | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET)); /* set up range protection */ - fu540_ddr_setup_range_protection(denali_ctl, DDR_MEM_SIZE); + fu540_ddr_setup_range_protection(denali_ctl, priv->info.size); /* Mask off port command error interrupt DENALI_CTL_136 */ setbits_le32(DENALI_CTL_136 + denali_ctl, @@ -314,14 +314,14 @@ static int fu540_ddr_setup(struct udevice *dev) /* check size */ priv->info.size = get_ram_size((long *)priv->info.base, - DDR_MEM_SIZE); + ddr_size); debug("%s : %lx\n", __func__, priv->info.size); /* check memory access for all memory */ - if (priv->info.size != DDR_MEM_SIZE) { + if (priv->info.size != ddr_size) { printf("DDR invalid size : 0x%lx, expected 0x%lx\n", - priv->info.size, DDR_MEM_SIZE); + priv->info.size, (uintptr_t)ddr_size); return -EINVAL; } @@ -333,6 +333,11 @@ static int fu540_ddr_probe(struct udevice *dev) { struct fu540_ddr_info *priv = dev_get_priv(dev); + /* Read memory base and size from DT */ + fdtdec_setup_mem_size_base(); + priv->info.base = gd->ram_base; + priv->info.size = gd->ram_size; + #if defined(CONFIG_SPL_BUILD) struct regmap *map; int ret; @@ -368,14 +373,9 @@ static int fu540_ddr_probe(struct udevice *dev) priv->phy = regmap_get_range(map, 1); priv->physical_filter_ctrl = regmap_get_range(map, 2); - priv->info.base = CONFIG_SYS_SDRAM_BASE; - - priv->info.size = 0; return fu540_ddr_setup(dev); -#else - priv->info.base = CONFIG_SYS_SDRAM_BASE; - priv->info.size = DDR_MEM_SIZE; #endif + return 0; }