imx: mx6: add clock api for lcdif
Implement mxs_set_lcdclk, enable_lcdif_clock and enable_pll_video. The three API can be used to configure lcdif related clock when CONFIG_VIDEO_MXS enabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan
Stefano Babic
parent
64ffef05e0
commit
ad153782e0
@ -473,6 +473,251 @@ static u32 get_mmdc_ch0_clk(void)
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}
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}
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#if defined(CONFIG_VIDEO_MXS)
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static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
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u32 post_div)
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{
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u32 reg = 0;
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ulong start;
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debug("pll5 div = %d, num = %d, denom = %d\n",
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pll_div, pll_num, pll_denom);
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/* Power up PLL5 video */
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writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
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BM_ANADIG_PLL_VIDEO_BYPASS |
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BM_ANADIG_PLL_VIDEO_DIV_SELECT |
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BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
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&imx_ccm->analog_pll_video_clr);
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/* Set div, num and denom */
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switch (post_div) {
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case 1:
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writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
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BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
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&imx_ccm->analog_pll_video_set);
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break;
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case 2:
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writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
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BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
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&imx_ccm->analog_pll_video_set);
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break;
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case 4:
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writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
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BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
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&imx_ccm->analog_pll_video_set);
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break;
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default:
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puts("Wrong test_div!\n");
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return -EINVAL;
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}
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writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
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&imx_ccm->analog_pll_video_num);
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writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
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&imx_ccm->analog_pll_video_denom);
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/* Wait PLL5 lock */
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start = get_timer(0); /* Get current timestamp */
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do {
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reg = readl(&imx_ccm->analog_pll_video);
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if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
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/* Enable PLL out */
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writel(BM_ANADIG_PLL_VIDEO_ENABLE,
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&imx_ccm->analog_pll_video_set);
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return 0;
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}
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} while (get_timer(0) < (start + 10)); /* Wait 10ms */
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puts("Lock PLL5 timeout\n");
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return -ETIME;
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}
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/*
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* 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
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*
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* 'freq' using KHz as unit, see driver/video/mxsfb.c.
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*/
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void mxs_set_lcdclk(u32 base_addr, u32 freq)
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{
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u32 reg = 0;
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u32 hck = MXC_HCLK / 1000;
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/* DIV_SELECT ranges from 27 to 54 */
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u32 min = hck * 27;
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u32 max = hck * 54;
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u32 temp, best = 0;
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u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
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u32 pll_div, pll_num, pll_denom, post_div = 1;
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debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
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if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL)) {
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debug("This chip not support lcd!\n");
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return;
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}
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if (base_addr == LCDIF1_BASE_ADDR) {
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reg = readl(&imx_ccm->cscdr2);
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/* Can't change clocks when clock not from pre-mux */
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if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
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return;
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}
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if (is_cpu_type(MXC_CPU_MX6SX)) {
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reg = readl(&imx_ccm->cscdr2);
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/* Can't change clocks when clock not from pre-mux */
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if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
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return;
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}
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temp = freq * max_pred * max_postd;
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if (temp > max) {
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puts("Please decrease freq, too large!\n");
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return;
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}
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if (temp < min) {
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/*
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* Register: PLL_VIDEO
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* Bit Field: POST_DIV_SELECT
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* 00 — Divide by 4.
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* 01 — Divide by 2.
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* 10 — Divide by 1.
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* 11 — Reserved
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* No need to check post_div(1)
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*/
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for (post_div = 2; post_div <= 4; post_div <<= 1) {
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if ((temp * post_div) > min) {
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freq *= post_div;
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break;
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}
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}
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if (post_div > 4) {
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printf("Fail to set rate to %dkhz", freq);
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return;
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}
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}
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/* Choose the best pred and postd to match freq for lcd */
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for (i = 1; i <= max_pred; i++) {
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for (j = 1; j <= max_postd; j++) {
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temp = freq * i * j;
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if (temp > max || temp < min)
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continue;
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if (best == 0 || temp < best) {
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best = temp;
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pred = i;
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postd = j;
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}
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}
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}
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if (best == 0) {
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printf("Fail to set rate to %dKHz", freq);
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return;
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}
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debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
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pll_div = best / hck;
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pll_denom = 1000000;
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pll_num = (best - hck * pll_div) * pll_denom / hck;
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/*
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* pll_num
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* (24MHz * (pll_div + --------- ))
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* pll_denom
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*freq KHz = --------------------------------
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* post_div * pred * postd * 1000
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*/
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if (base_addr == LCDIF1_BASE_ADDR) {
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if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
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return;
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/* Select pre-lcd clock to PLL5 and set pre divider */
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clrsetbits_le32(&imx_ccm->cscdr2,
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MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
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MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
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(0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
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((pred - 1) <<
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MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
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/* Set the post divider */
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clrsetbits_le32(&imx_ccm->cbcmr,
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MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
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((postd - 1) <<
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MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
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} else if (is_cpu_type(MXC_CPU_MX6SX)) {
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/* Setting LCDIF2 for i.MX6SX */
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if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
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return;
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/* Select pre-lcd clock to PLL5 and set pre divider */
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clrsetbits_le32(&imx_ccm->cscdr2,
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MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
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MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
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(0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
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((pred - 1) <<
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MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
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/* Set the post divider */
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clrsetbits_le32(&imx_ccm->cscmr1,
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MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
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((postd - 1) <<
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MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
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}
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}
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int enable_lcdif_clock(u32 base_addr)
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{
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u32 reg = 0;
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u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
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if (is_cpu_type(MXC_CPU_MX6SX)) {
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if ((base_addr == LCDIF1_BASE_ADDR) ||
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(base_addr == LCDIF2_BASE_ADDR)) {
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puts("Wrong LCD interface!\n");
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return -EINVAL;
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}
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/* Set to pre-mux clock at default */
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lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
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MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
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MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
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lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
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(MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
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MXC_CCM_CCGR3_DISP_AXI_MASK) :
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(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
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MXC_CCM_CCGR3_DISP_AXI_MASK);
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} else if (is_cpu_type(MXC_CPU_MX6UL)) {
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if (base_addr != LCDIF1_BASE_ADDR) {
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puts("Wrong LCD interface!\n");
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return -EINVAL;
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}
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/* Set to pre-mux clock at default */
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lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
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lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
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} else {
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return 0;
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}
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reg = readl(&imx_ccm->cscdr2);
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reg &= ~lcdif_clk_sel_mask;
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writel(reg, &imx_ccm->cscdr2);
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/* Enable the LCDIF pix clock */
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reg = readl(&imx_ccm->CCGR3);
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reg |= lcdif_ccgr3_mask;
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writel(reg, &imx_ccm->CCGR3);
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reg = readl(&imx_ccm->CCGR2);
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reg |= MXC_CCM_CCGR2_LCD_MASK;
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writel(reg, &imx_ccm->CCGR2);
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}
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#endif
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#ifdef CONFIG_FSL_QSPI
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/* qspi_num can be from 0 - 1 */
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void enable_qspi_clk(int qspi_num)
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@ -66,6 +66,8 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num);
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void enable_ipu_clock(void);
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int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
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void enable_enet_clk(unsigned char enable);
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int enable_lcdif_clock(u32 base_addr);
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void enable_qspi_clk(int qspi_num);
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void enable_thermal_clk(void);
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void mxs_set_lcdclk(u32 base_addr, u32 freq);
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#endif /* __ASM_ARCH_CLOCK_H */
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