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sunxi: nand: Add pinmux and clock settings for NAND support

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To enable NAND flash in sunxi SPL,
pins 0-6, 8-22 and 24 on port C are configured.

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Karol Gugala
2015-07-23 14:33:01 +02:00
committed by Hans de Goede
parent 38c4f8ba4c
commit ad00829971
3 changed files with 30 additions and 0 deletions
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2
arch/arm/include/asm/arch-sunxi/clock_sun4i.h
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@@ -267,6 +267,8 @@ struct sunxi_ccm_reg {
#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
#define CCM_MBUS_CTRL_GATE (0x1 << 31)
#define CCM_NAND_CTRL_ENABLE (0x1 << 31)
#define CCM_MMC_CTRL_M(x) ((x) - 1)
#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8)
#define CCM_MMC_CTRL_N(x) ((x) << 16)

1
arch/arm/include/asm/arch-sunxi/gpio.h
View File

@@ -158,6 +158,7 @@ enum sunxi_gpio_number {
#define SUN8I_GPB_UART2 2
#define SUN8I_A33_GPB_UART0 3
#define SUNXI_GPC_NAND 2
#define SUNXI_GPC_SDC2 3
#define SUN6I_GPC_SDC3 4