riscv: dts: sifive: Synchronize FU740 and Unmatched DT
These DT files are synchronized from Linux 5.19. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Icenowy Zheng
Leo Yu-Chi Liang
parent
d13cd77068
commit
ac48fc3deb
@ -1,10 +1,9 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020-2021 SiFive, Inc */
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/* Copyright (c) 2020 SiFive, Inc */
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/dts-v1/;
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#include <dt-bindings/clock/sifive-fu740-prci.h>
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#include <dt-bindings/reset/sifive-fu740-prci.h>
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/ {
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#address-cells = <2>;
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@ -139,20 +138,21 @@
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus";
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compatible = "simple-bus";
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ranges;
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plic0: interrupt-controller@c000000 {
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#interrupt-cells = <1>;
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compatible = "sifive,plic-1.0.0";
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#address-cells = <0>;
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compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
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reg = <0x0 0xc000000 0x0 0x4000000>;
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riscv,ndev = <69>;
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interrupt-controller;
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interrupts-extended = <
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&cpu0_intc 0xffffffff
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&cpu1_intc 0xffffffff &cpu1_intc 9
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&cpu2_intc 0xffffffff &cpu2_intc 9
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&cpu3_intc 0xffffffff &cpu3_intc 9
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&cpu4_intc 0xffffffff &cpu4_intc 9>;
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interrupts-extended =
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<&cpu0_intc 0xffffffff>,
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<&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
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<&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
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<&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
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<&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
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};
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prci: clock-controller@10000000 {
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compatible = "sifive,fu740-c000-prci";
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@ -203,8 +203,8 @@
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};
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qspi0: spi@10040000 {
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compatible = "sifive,fu740-c000-spi", "sifive,spi0";
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reg = <0x0 0x10040000 0x0 0x1000
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0x0 0x20000000 0x0 0x10000000>;
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reg = <0x0 0x10040000 0x0 0x1000>,
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<0x0 0x20000000 0x0 0x10000000>;
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interrupt-parent = <&plic0>;
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interrupts = <41>;
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clocks = <&prci FU740_PRCI_CLK_PCLK>;
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@ -214,8 +214,8 @@
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};
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qspi1: spi@10041000 {
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compatible = "sifive,fu740-c000-spi", "sifive,spi0";
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reg = <0x0 0x10041000 0x0 0x1000
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0x0 0x30000000 0x0 0x10000000>;
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reg = <0x0 0x10041000 0x0 0x1000>,
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<0x0 0x30000000 0x0 0x10000000>;
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interrupt-parent = <&plic0>;
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interrupts = <42>;
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clocks = <&prci FU740_PRCI_CLK_PCLK>;
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@ -237,8 +237,8 @@
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compatible = "sifive,fu540-c000-gem";
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interrupt-parent = <&plic0>;
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interrupts = <55>;
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reg = <0x0 0x10090000 0x0 0x2000
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0x0 0x100a0000 0x0 0x1000>;
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reg = <0x0 0x10090000 0x0 0x2000>,
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<0x0 0x100a0000 0x0 0x1000>;
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local-mac-address = [00 00 00 00 00 00];
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clock-names = "pclk", "hclk";
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clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>,
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@ -251,7 +251,7 @@
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compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
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reg = <0x0 0x10020000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <44 45 46 47>;
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interrupts = <44>, <45>, <46>, <47>;
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clocks = <&prci FU740_PRCI_CLK_PCLK>;
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#pwm-cells = <3>;
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status = "disabled";
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@ -260,7 +260,7 @@
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compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
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reg = <0x0 0x10021000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <48 49 50 51>;
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interrupts = <48>, <49>, <50>, <51>;
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clocks = <&prci FU740_PRCI_CLK_PCLK>;
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#pwm-cells = <3>;
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status = "disabled";
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@ -273,7 +273,7 @@
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cache-size = <2097152>;
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cache-unified;
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interrupt-parent = <&plic0>;
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interrupts = <19 21 22 20>;
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interrupts = <19>, <21>, <22>, <20>;
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reg = <0x0 0x2010000 0x0 0x1000>;
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};
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gpio: gpio@10060000 {
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@ -291,24 +291,23 @@
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status = "disabled";
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};
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pcie@e00000000 {
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#address-cells = <3>;
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#interrupt-cells = <1>;
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#num-lanes = <8>;
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#size-cells = <2>;
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compatible = "sifive,fu740-pcie";
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reg = <0xe 0x00000000 0x1 0x0
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0xd 0xf0000000 0x0 0x10000000
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0x0 0x100d0000 0x0 0x1000>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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reg = <0xe 0x00000000 0x0 0x80000000>,
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<0xd 0xf0000000 0x0 0x10000000>,
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<0x0 0x100d0000 0x0 0x1000>;
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reg-names = "dbi", "config", "mgmt";
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device_type = "pci";
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dma-coherent;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000
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0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000
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0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000
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0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;
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ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
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<0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
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<0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
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<0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
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num-lanes = <0x8>;
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interrupts = <56 57 58 59 60 61 62 63 64>;
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interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
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interrupt-names = "msi", "inta", "intb", "intc", "intd";
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interrupt-parent = <&plic0>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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@ -316,13 +315,11 @@
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<0x0 0x0 0x0 0x2 &plic0 58>,
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<0x0 0x0 0x0 0x3 &plic0 59>,
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<0x0 0x0 0x0 0x4 &plic0 60>;
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clock-names = "pcie_aux";
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clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;
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pwren-gpios = <&gpio 5 0>;
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reset-gpios = <&gpio 8 0>;
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clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;
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clock-names = "pcie_aux";
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resets = <&prci PRCI_RST_PCIE_POWER_UP_N>;
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reset-names = "rst_n";
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resets = <&prci 4>;
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status = "okay";
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};
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};
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@ -1,5 +1,5 @@
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// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (c) 2019-2021 SiFive, Inc */
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020 SiFive, Inc */
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#include "fu740-c000.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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@ -9,8 +9,6 @@
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#define RTCCLK_FREQ 1000000
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "SiFive HiFive Unmatched A00";
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compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
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"sifive,fu740";
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@ -28,9 +26,6 @@
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reg = <0x0 0x80000000 0x4 0x00000000>;
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};
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soc {
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};
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hfclk: hfclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@ -65,10 +60,21 @@
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temperature-sensor@4c {
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compatible = "ti,tmp451";
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reg = <0x4c>;
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vcc-supply = <&vdd_bpro>;
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interrupt-parent = <&gpio>;
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interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
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};
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eeprom@54 {
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compatible = "microchip,24c02", "atmel,24c02";
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reg = <0x54>;
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vcc-supply = <&vdd_bpro>;
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label = "board-id";
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pagesize = <16>;
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read-only;
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size = <256>;
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};
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pmic@58 {
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compatible = "dlg,da9063";
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reg = <0x58>;
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@ -89,47 +95,31 @@
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};
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regulators {
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vdd_bcore1: bcore1 {
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vdd_bcore: bcores-merged {
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regulator-min-microvolt = <1050000>;
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regulator-max-microvolt = <1050000>;
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regulator-min-microamp = <5000000>;
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regulator-max-microamp = <5000000>;
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regulator-always-on;
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};
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vdd_bcore2: bcore2 {
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regulator-min-microvolt = <1050000>;
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regulator-max-microvolt = <1050000>;
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regulator-min-microamp = <5000000>;
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regulator-max-microamp = <5000000>;
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regulator-min-microamp = <4800000>;
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regulator-max-microamp = <4800000>;
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regulator-always-on;
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};
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vdd_bpro: bpro {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-min-microamp = <2500000>;
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regulator-max-microamp = <2500000>;
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regulator-min-microamp = <2400000>;
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regulator-max-microamp = <2400000>;
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regulator-always-on;
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};
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vdd_bperi: bperi {
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regulator-min-microvolt = <1050000>;
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regulator-max-microvolt = <1050000>;
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regulator-min-microvolt = <1060000>;
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regulator-max-microvolt = <1060000>;
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regulator-min-microamp = <1500000>;
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regulator-max-microamp = <1500000>;
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regulator-always-on;
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};
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vdd_bmem: bmem {
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-min-microamp = <3000000>;
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regulator-max-microamp = <3000000>;
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regulator-always-on;
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};
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vdd_bio: bio {
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vdd_bmem_bio: bmem-bio-merged {
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-min-microamp = <3000000>;
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@ -140,86 +130,66 @@
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vdd_ldo1: ldo1 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-min-microamp = <100000>;
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regulator-max-microamp = <100000>;
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regulator-always-on;
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};
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vdd_ldo2: ldo2 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-min-microamp = <200000>;
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regulator-max-microamp = <200000>;
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regulator-always-on;
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};
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vdd_ldo3: ldo3 {
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microamp = <200000>;
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regulator-max-microamp = <200000>;
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regulator-always-on;
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};
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vdd_ldo4: ldo4 {
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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regulator-min-microamp = <200000>;
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regulator-max-microamp = <200000>;
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regulator-always-on;
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};
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vdd_ldo5: ldo5 {
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microamp = <100000>;
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regulator-max-microamp = <100000>;
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regulator-always-on;
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};
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vdd_ldo6: ldo6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-min-microamp = <200000>;
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regulator-max-microamp = <200000>;
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regulator-always-on;
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};
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vdd_ldo7: ldo7 {
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microamp = <200000>;
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regulator-max-microamp = <200000>;
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regulator-always-on;
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};
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vdd_ldo8: ldo8 {
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microamp = <200000>;
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regulator-max-microamp = <200000>;
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regulator-always-on;
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};
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vdd_ld09: ldo9 {
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regulator-min-microvolt = <1050000>;
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regulator-max-microvolt = <1050000>;
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regulator-min-microamp = <200000>;
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regulator-max-microamp = <200000>;
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regulator-always-on;
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};
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vdd_ldo10: ldo10 {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-min-microamp = <300000>;
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regulator-max-microamp = <300000>;
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regulator-always-on;
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};
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vdd_ldo11: ldo11 {
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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regulator-min-microamp = <300000>;
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regulator-max-microamp = <300000>;
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regulator-always-on;
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};
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};
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@ -269,4 +239,8 @@
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&gpio {
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status = "okay";
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gpio-line-names = "J29.1", "PMICNTB", "PMICSHDN", "J8.1", "J8.3",
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"PCIe_PWREN", "THERM", "UBRDG_RSTN", "PCIe_PERSTN",
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"ULPI_RSTN", "J8.2", "UHUB_RSTN", "GEMGXL_RST", "J8.4",
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"EN_VDD_SD", "SD_CD";
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};
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