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Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

Browse Source 
Conflicts:

	Makefile

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2008-09-09 02:24:51 +02:00
commit ab00e7a23e
40 changed files with 2107 additions and 336 deletions
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3
CREDITS
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@ -405,7 +405,8 @@ D: Atmel AT91CAP9ADK support
N: Ricardo Ribalda Delgado
E: ricardo.ribalda@uam.es
D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460
D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460, v5fx30teval
D: Virtex ppc440 generic architecture
W: http://www.ii.uam.es/~rribalda
N: Stefan Roese

2
MAINTAINERS
View File

@ -314,6 +314,8 @@ Daniel Poirot <dan.poirot@windriver.com>
Ricardo Ribalda <ricardo.ribalda@uam.es>
ml507 PPC440x5
v5fx30teval PPC440x5
xilinx-pp440-generic PPC440x5
Stefan Roese <sr@denx.de>

4
MAKEALL
View File

@ -230,12 +230,16 @@ LIST_4xx=" \
sequoia_nand \
taihu \
taishan \
v5fx30teval \
v5fx30teval_flash \
VOH405 \
VOM405 \
W7OLMC \
W7OLMG \
walnut \
WUH405 \
xilinx-ppc440-generic \
xilinx-ppc440-generic_flash \
XPEDITE1K \
yellowstone \
yosemite \

49
Makefile
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@ -1242,12 +1242,14 @@ CMS700_config: unconfig
CPCI2DP_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
CPCI405_config \
CPCI4052_config \
CPCI405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
CPCI4052_config \
CPCI405DT_config \
CPCI405AB_config: unconfig
@echo "TEXT_BASE = 0xFFFC0000" > $(obj)board/esd/cpci405/config.tmp
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
@echo "BOARD_REVISION = $(@:_config=)" >> $(obj)include/config.mk
CPCIISER4_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpciiser4 esd
@ -1356,16 +1358,19 @@ ML2_config: unconfig
ml300_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml300 xilinx
ml507_flash_config: unconfig
ml507_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ml507
@cp board/xilinx/ml507/u-boot-rom.lds $(obj)board/xilinx/ml507/u-boot.lds
@echo "TEXT_BASE = 0xFE360000" > $(obj)board/xilinx/ml507/config.tmp
@$(MKCONFIG) $(@:_flash_config=) ppc ppc4xx ml507 xilinx
@echo "LDSCRIPT := $(obj)board/xilinx/ppc440-generic/u-boot-rom.lds" \
> $(obj)board/xilinx/ml507/config.mk
@echo "TEXT_BASE := 0xFE360000" >> $(obj)board/xilinx/ml507/config.mk
@$(MKCONFIG) ml507 ppc ppc4xx ml507 xilinx
ml507_config: unconfig
ml507_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ml507
@cp board/xilinx/ml507/u-boot-ram.lds $(obj)board/xilinx/ml507/u-boot.lds
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml507 xilinx
@echo "LDSCRIPT := $(obj)board/xilinx/ppc440-generic/u-boot-ram.lds" \
> $(obj)board/xilinx/ml507/config.mk
@echo "TEXT_BASE := 0x04000000" >> $(obj)board/xilinx/ml507/config.mk
@$(MKCONFIG) ml507 ppc ppc4xx ml507 xilinx
ocotea_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ocotea amcc
@ -1461,6 +1466,18 @@ taihu_config: unconfig
taishan_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
v5fx30teval_config: unconfig
@mkdir -p $(obj)include $(obj)board/avnet/v5fx30teval
@echo "LDSCRIPT := $(obj)board/xilinx/ppc440-generic/u-boot-ram.lds" > $(obj)board/avnet/v5fx30teval/config.mk
@echo "TEXT_BASE := 0x03000000" >> $(obj)board/avnet/v5fx30teval/config.mk
@$(MKCONFIG) v5fx30teval ppc ppc4xx v5fx30teval avnet
v5fx30teval_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/avnet/v5fx30teval
@echo "LDSCRIPT := $(obj)board/xilinx/ppc440-generic/u-boot-rom.lds" > $(obj)board/avnet/v5fx30teval/config.mk
@echo "TEXT_BASE := 0xFF1C0000" >> $(obj)board/avnet/v5fx30teval/config.mk
@$(MKCONFIG) v5fx30teval ppc ppc4xx v5fx30teval avnet
VOH405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx voh405 esd
@ -1479,6 +1496,18 @@ sycamore_config: unconfig
WUH405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx wuh405 esd
xilinx-ppc440-generic_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic/
@echo "LDSCRIPT := $(obj)board/xilinx/ppc440-generic/u-boot-rom.lds" > $(obj)board/xilinx/ppc440-generic/config.mk
@echo "TEXT_BASE := 0xFE360000" >> $(obj)board/xilinx/ppc440-generic/config.mk
@$(MKCONFIG) xilinx-ppc440-generic ppc ppc4xx ppc440-generic xilinx
xilinx-ppc440-generic_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic/
@echo "LDSCRIPT := $(obj)board/xilinx/ppc440-generic/u-boot-ram.lds" > $(obj)board/xilinx/ppc440-generic/config.mk
@echo "TEXT_BASE := 0x04000000" >> $(obj)board/xilinx/ppc440-generic/config.mk
@$(MKCONFIG) xilinx-ppc440-generic ppc ppc4xx ppc440-generic xilinx
XPEDITE1K_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx xpedite1k

1
board/avnet/v5fx30teval/.gitignore vendored Normal file
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@ -0,0 +1 @@
/config.mk

12
board/xilinx/ml507/config.mk → board/avnet/v5fx30teval/Makefile
View File

@ -1,6 +1,7 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# (C) Copyright 2008
# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
# This work has been supported by: Qtechnology http://qtec.com/
#
# See file CREDITS for list of people who contributed to this
# project.
@ -20,8 +21,7 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
TEXT_BASE = 0x04000000
endif
COBJS += $(BOARD).o
include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile

28
board/avnet/v5fx30teval/v5fx30teval.c Normal file
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@ -0,0 +1,28 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <config.h>
#include <common.h>
#include <asm/processor.h>
int checkboard(void)
{
puts("Avnet Virtex 5 FX30 Evaluation Board\n");
return 0;
}

33
board/avnet/v5fx30teval/xparameters.h Normal file
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@ -0,0 +1,33 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters.h by Xilinx
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef XPARAMETER_H
#define XPARAMETER_H
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#endif

16
board/esd/cpci405/config.mk
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@ -21,20 +21,8 @@
# MA 02111-1307 USA
#
#
# esd CPCI405 boards
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifeq ($(BOARD_REVISION),CPCI4052)
TEXT_BASE = 0xFFFC0000
else
ifeq ($(BOARD_REVISION),CPCI405DT)
TEXT_BASE = 0xFFFC0000
else
ifeq ($(BOARD_REVISION),CPCI405AB)
TEXT_BASE = 0xFFFC0000
else
ifndef TEXT_BASE
TEXT_BASE = 0xFFFD0000
endif
endif
endif

15
board/esd/cpci405/u-boot.lds
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@ -57,22 +57,7 @@ SECTIONS
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)

2
board/netstal/hcu5/sdram.c
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@ -122,7 +122,7 @@ void sdram_panic(const char *reason)
}
#ifdef CONFIG_DDR_ECC
static void blank_string(int size)
void blank_string(int size)
{
int i;

1
board/xilinx/ml507/.gitignore vendored Normal file
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@ -0,0 +1 @@
/config.mk

41
board/xilinx/ml507/Makefile
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@ -1,6 +1,7 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# (C) Copyright 2008
# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
# This work has been supported by: Qtechnology http://qtec.com/
#
# See file CREDITS for list of people who contributed to this
# project.
@ -21,38 +22,6 @@
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
endif
COBJS += $(BOARD).o
INCS :=
CFLAGS += $(INCS)
HOST_CFLAGS += $(INCS)
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile

53
board/xilinx/ml507/init.S
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@ -1,53 +0,0 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm-ppc/mmu.h>
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/* SDRAM */
tlbentry(XPAR_DDR2_SDRAM_MEM_BASEADDR, SZ_256M, CFG_SDRAM_BASE, 0,
AC_R | AC_W | AC_X | SA_G | SA_I)
/* UART */
tlbentry(XPAR_UARTLITE_0_BASEADDR, SZ_64K, XPAR_UARTLITE_0_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
/* PIC */
tlbentry(XPAR_INTC_0_BASEADDR, SZ_64K, XPAR_INTC_0_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
#ifdef XPAR_IIC_EEPROM_BASEADDR
/* I2C */
tlbentry(XPAR_IIC_EEPROM_BASEADDR, SZ_64K, XPAR_IIC_EEPROM_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
#endif
#ifdef XPAR_LLTEMAC_0_BASEADDR
/* Net */
tlbentry(XPAR_LLTEMAC_0_BASEADDR, SZ_64K, XPAR_LLTEMAC_0_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
#endif
#ifdef XPAR_FLASH_MEM0_BASEADDR
/*Flash*/
tlbentry(XPAR_FLASH_MEM0_BASEADDR, SZ_256M, XPAR_FLASH_MEM0_BASEADDR, 0,
AC_R | AC_W | AC_X | SA_G | SA_I)
#endif
tlbtab_end

21
board/xilinx/ml507/ml507.c
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@ -20,28 +20,9 @@
#include <common.h>
#include <asm/processor.h>
int board_pre_init(void)
{
return 0;
}
int checkboard(void)
{
puts("ML507 Board\n");
puts("Xilinx ML507 Board\n");
return 0;
}
phys_size_t initdram(int board_type)
{
return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CFG_SDRAM_SIZE_MB * 1024 * 1024);
}
void get_sys_info(sys_info_t * sysInfo)
{
sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
sysInfo->freqPCI = 0;
return;
}

17
board/xilinx/ml507/xparameters.h
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@ -21,15 +21,14 @@
#ifndef XPARAMETER_H
#define XPARAMETER_H
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_LLTEMAC_0_BASEADDR 0x81C00000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#endif

1
board/xilinx/ppc440-generic/.gitignore vendored Normal file
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@ -0,0 +1 @@
/config.mk

62
board/xilinx/ppc440-generic/Makefile Normal file
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@ -0,0 +1,62 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
# Work supported by Qtechnology http://www.qtec.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
endif
INCS :=
CFLAGS += $(INCS)
HOST_CFLAGS += $(INCS)
LIB = $(obj)lib$(BOARD).a
COBJS += $(SRCTREE)/board/xilinx/ppc440-generic/xilinx_ppc440_generic.o
SOBJS += $(SRCTREE)/board/xilinx/ppc440-generic/init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

45
board/xilinx/ppc440-generic/init.S Normal file
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@ -0,0 +1,45 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm-ppc/mmu.h>
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
tlbentry(0x00000000, SZ_256M, 0x00000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x10000000, SZ_256M, 0x10000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x20000000, SZ_256M, 0x20000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x30000000, SZ_256M, 0x30000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x40000000, SZ_256M, 0x40000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x50000000, SZ_256M, 0x50000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x60000000, SZ_256M, 0x60000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x70000000, SZ_256M, 0x70000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x80000000, SZ_256M, 0x80000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x90000000, SZ_256M, 0x90000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0xa0000000, SZ_256M, 0xa0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0xb0000000, SZ_256M, 0xb0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0xc0000000, SZ_256M, 0xc0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0xd0000000, SZ_256M, 0xd0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0xe0000000, SZ_256M, 0xe0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0xf0000000, SZ_256M, 0xf0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbtab_end

0
board/xilinx/ml507/u-boot-ram.lds → board/xilinx/ppc440-generic/u-boot-ram.lds
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0
board/xilinx/ml507/u-boot-rom.lds → board/xilinx/ppc440-generic/u-boot-rom.lds
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52
board/xilinx/ppc440-generic/xilinx_ppc440_generic.c Normal file
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@ -0,0 +1,52 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <config.h>
#include <common.h>
#include <asm/processor.h>
int __board_pre_init(void)
{
return 0;
}
int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
int __checkboard(void)
{
puts("Xilinx PPC440 Generic Board\n");
return 0;
}
int checkboard(void) __attribute__((weak, alias("__checkboard")));
phys_size_t __initdram(int board_type)
{
return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CFG_SDRAM_SIZE_MB * 1024 * 1024);
}
phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
void __get_sys_info(sys_info_t *sysInfo)
{
sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
sysInfo->freqPCI = 0;
return;
}
void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));

34
board/xilinx/ppc440-generic/xparameters.h Normal file
View File

@ -0,0 +1,34 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters-ml507.h by Xilinx
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef XPARAMETER_H
#define XPARAMETER_H
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#endif

158
cpu/ppc4xx/44x_spd_ddr2.c
View File

@ -60,8 +60,6 @@
"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
} while (0)
static inline void ppc4xx_ibm_ddr2_register_dump(void);
#if defined(CONFIG_SPD_EEPROM)
/*-----------------------------------------------------------------------------+
@ -260,62 +258,19 @@ static void program_ecc_addr(unsigned long start_address,
unsigned long num_bytes,
unsigned long tlb_word2_i_value);
#endif
#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
static void program_DQS_calibration(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks);
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks);
#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
static void test(void);
#else
static void DQS_calibration_process(void);
#endif
#endif
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
void dcbz_area(u32 start_address, u32 num_bytes);
static u32 mfdcr_any(u32 dcr)
{
u32 val;
switch (dcr) {
case SDRAM_R0BAS + 0:
val = mfdcr(SDRAM_R0BAS + 0);
break;
case SDRAM_R0BAS + 1:
val = mfdcr(SDRAM_R0BAS + 1);
break;
case SDRAM_R0BAS + 2:
val = mfdcr(SDRAM_R0BAS + 2);
break;
case SDRAM_R0BAS + 3:
val = mfdcr(SDRAM_R0BAS + 3);
break;
default:
printf("DCR %d not defined in case statement!!!\n", dcr);
val = 0; /* just to satisfy the compiler */
}
return val;
}
static void mtdcr_any(u32 dcr, u32 val)
{
switch (dcr) {
case SDRAM_R0BAS + 0:
mtdcr(SDRAM_R0BAS + 0, val);
break;
case SDRAM_R0BAS + 1:
mtdcr(SDRAM_R0BAS + 1, val);
break;
case SDRAM_R0BAS + 2:
mtdcr(SDRAM_R0BAS + 2, val);
break;
case SDRAM_R0BAS + 3:
mtdcr(SDRAM_R0BAS + 3, val);
break;
default:
printf("DCR %d not defined in case statement!!!\n", dcr);
}
}
static unsigned char spd_read(uchar chip, uint addr)
{
unsigned char data[2];
@ -609,7 +564,11 @@ phys_size_t initdram(int board_type)
/*------------------------------------------------------------------
* DQS calibration.
*-----------------------------------------------------------------*/
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
DQS_autocalibration();
#else
program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
#endif
#ifdef CONFIG_DDR_ECC
/*------------------------------------------------------------------
@ -2329,18 +2288,6 @@ static unsigned long is_ecc_enabled(void)
return ecc;
}
static void blank_string(int size)
{
int i;
for (i=0; i<size; i++)
putc('\b');
for (i=0; i<size; i++)
putc(' ');
for (i=0; i<size; i++)
putc('\b');
}
#ifdef CONFIG_DDR_ECC
/*-----------------------------------------------------------------------------+
* program_ecc.
@ -2468,6 +2415,7 @@ static void program_ecc_addr(unsigned long start_address,
}
#endif
#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
/*-----------------------------------------------------------------------------+
* program_DQS_calibration.
*-----------------------------------------------------------------------------*/
@ -3001,7 +2949,8 @@ static void test(void)
(ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
| ecc_temp);
}
#endif
#endif /* !HARD_CODED_DQS */
#endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
#else /* CONFIG_SPD_EEPROM */
@ -3104,9 +3053,12 @@ phys_size_t initdram(int board_type)
/* Set Delay Control Registers */
mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
#endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
/*
* Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
@ -3115,18 +3067,98 @@ phys_size_t initdram(int board_type)
mfsdram(SDRAM_MCOPT2, val);
mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*------------------------------------------------------------------
| DQS calibration.
+-----------------------------------------------------------------*/
DQS_autocalibration();
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
#if defined(CONFIG_DDR_ECC)
ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
#endif /* defined(CONFIG_DDR_ECC) */
ppc4xx_ibm_ddr2_register_dump();
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
/*
* Clear potential errors resulting from auto-calibration.
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
set_mcsr(get_mcsr());
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
return (CFG_MBYTES_SDRAM << 20);
}
#endif /* CONFIG_SPD_EEPROM */
static inline void ppc4xx_ibm_ddr2_register_dump(void)
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#if defined(CONFIG_440)
u32 mfdcr_any(u32 dcr)
{
u32 val;
switch (dcr) {
case SDRAM_R0BAS + 0:
val = mfdcr(SDRAM_R0BAS + 0);
break;
case SDRAM_R0BAS + 1:
val = mfdcr(SDRAM_R0BAS + 1);
break;
case SDRAM_R0BAS + 2:
val = mfdcr(SDRAM_R0BAS + 2);
break;
case SDRAM_R0BAS + 3:
val = mfdcr(SDRAM_R0BAS + 3);
break;
default:
printf("DCR %d not defined in case statement!!!\n", dcr);
val = 0; /* just to satisfy the compiler */
}
return val;
}
void mtdcr_any(u32 dcr, u32 val)
{
switch (dcr) {
case SDRAM_R0BAS + 0:
mtdcr(SDRAM_R0BAS + 0, val);
break;
case SDRAM_R0BAS + 1:
mtdcr(SDRAM_R0BAS + 1, val);
break;
case SDRAM_R0BAS + 2:
mtdcr(SDRAM_R0BAS + 2, val);
break;
case SDRAM_R0BAS + 3:
mtdcr(SDRAM_R0BAS + 3, val);
break;
default:
printf("DCR %d not defined in case statement!!!\n", dcr);
}
}
#endif /* defined(CONFIG_440) */
void blank_string(int size)
{
int i;
for (i = 0; i < size; i++)
putc('\b');
for (i = 0; i < size; i++)
putc(' ');
for (i = 0; i < size; i++)
putc('\b');
}
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
inline void ppc4xx_ibm_ddr2_register_dump(void)
{
#if defined(DEBUG)
printf("\nPPC4xx IBM DDR2 Register Dump:\n");

168
cpu/ppc4xx/4xx_enet.c
View File

@ -198,6 +198,7 @@
#define BI_PHYMODE_RMII 8
#endif
#endif
#define BI_PHYMODE_SGMII 9
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
@ -216,6 +217,52 @@
#define MAL_RX_CHAN_MUL 1
#endif
/*--------------------------------------------------------------------+
* Fixed PHY (PHY-less) support for Ethernet Ports.
*--------------------------------------------------------------------*/
/*
* Some boards do not have a PHY for each ethernet port. These ports
* are known as Fixed PHY (or PHY-less) ports. For such ports, set
* the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
* then define CFG_FIXED_PHY_PORTS to define what the speed and
* duplex should be for these ports in the board configuration
* file.
*
* For Example:
* #define CONFIG_FIXED_PHY 0xFFFFFFFF
*
* #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
* #define CONFIG_PHY1_ADDR 1
* #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY
* #define CONFIG_PHY3_ADDR 3
*
* #define CFG_FIXED_PHY_PORT(devnum,speed,duplex) \
* {devnum, speed, duplex},
*
* #define CFG_FIXED_PHY_PORTS \
* CFG_FIXED_PHY_PORT(0,1000,FULL) \
* CFG_FIXED_PHY_PORT(2,100,HALF)
*/
#ifndef CONFIG_FIXED_PHY
#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
#endif
#ifndef CFG_FIXED_PHY_PORTS
#define CFG_FIXED_PHY_PORTS /* default is an empty array */
#endif
struct fixed_phy_port {
unsigned int devnum; /* ethernet port */
unsigned int speed; /* specified speed 10,100 or 1000 */
unsigned int duplex; /* specified duplex FULL or HALF */
};
static const struct fixed_phy_port fixed_phy_port[] = {
CFG_FIXED_PHY_PORTS /* defined in board configuration file */
};
/*-----------------------------------------------------------------------------+
* Global variables. TX and RX descriptors and buffers.
*-----------------------------------------------------------------------------*/
@ -611,8 +658,17 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
#if defined(CONFIG_460EX)
mode = 9;
mfsdr(SDR0_ETH_CFG, eth_cfg);
if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0))
mode = 11; /* config SGMII */
#else
mode = 10;
mfsdr(SDR0_ETH_CFG, eth_cfg);
if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) &&
((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0))
mode = 12; /* config SGMII */
#endif
/* TODO:
@ -635,6 +691,8 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
/*
* Right now only 2*RGMII is supported. Please extend when needed.
* sr - 2008-02-19
* Add SGMII support.
* vg - 2008-07-28
*/
switch (mode) {
case 1:
@ -761,6 +819,20 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
bis->bi_phymode[2] = BI_PHYMODE_RGMII;
bis->bi_phymode[3] = BI_PHYMODE_RGMII;
break;
case 11:
/* 2 SGMII - 460EX */
bis->bi_phymode[0] = BI_PHYMODE_SGMII;
bis->bi_phymode[1] = BI_PHYMODE_SGMII;
bis->bi_phymode[2] = BI_PHYMODE_NONE;
bis->bi_phymode[3] = BI_PHYMODE_NONE;
break;
case 12:
/* 3 SGMII - 460GT */
bis->bi_phymode[0] = BI_PHYMODE_SGMII;
bis->bi_phymode[1] = BI_PHYMODE_SGMII;
bis->bi_phymode[2] = BI_PHYMODE_SGMII;
bis->bi_phymode[3] = BI_PHYMODE_NONE;
break;
default:
break;
}
@ -945,9 +1017,50 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
#if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \
defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR)
if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
/*
* In SGMII mode, GPCS access is needed for
* communication with the internal SGMII SerDes.
*/
switch (devnum) {
#if defined(CONFIG_GPCS_PHY_ADDR)
case 0:
reg = CONFIG_GPCS_PHY_ADDR;
break;
#endif
#if defined(CONFIG_GPCS_PHY1_ADDR)
case 1:
reg = CONFIG_GPCS_PHY1_ADDR;
break;
#endif
#if defined(CONFIG_GPCS_PHY2_ADDR)
case 2:
reg = CONFIG_GPCS_PHY2_ADDR;
break;
#endif
#if defined(CONFIG_GPCS_PHY3_ADDR)
case 3:
reg = CONFIG_GPCS_PHY3_ADDR;
break;
#endif
}
mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
mode_reg |= EMAC_M1_MF_1000GPCS | EMAC_M1_IPPA_SET(reg);
out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
/* Configure GPCS interface to recommended setting for SGMII */
miiphy_reset(dev->name, reg);
miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */
miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */
miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */
}
#endif /* defined(CONFIG_GPCS_PHY_ADDR) */
/* wait for PHY to complete auto negotiation */
reg_short = 0;
#ifndef CONFIG_CS8952_PHY
switch (devnum) {
case 0:
reg = CONFIG_PHY_ADDR;
@ -974,6 +1087,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
bis->bi_phynum[devnum] = reg;
if (reg == CONFIG_FIXED_PHY)
goto get_speed;
#if defined(CONFIG_PHY_RESET)
/*
* Reset the phy, only if its the first time through
@ -986,6 +1102,27 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
miiphy_write (dev->name, reg, 0x09, 0x0e00);
miiphy_write (dev->name, reg, 0x04, 0x01e1);
#endif
#if defined(CONFIG_M88E1112_PHY)
if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
/*
* Marvell 88E1112 PHY needs to have the SGMII MAC
* interace (page 2) properly configured to
* communicate with the 460EX/GT GPCS interface.
*/
/* Set access to Page 2 */
miiphy_write(dev->name, reg, 0x16, 0x0002);
miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */
miiphy_read(dev->name, reg, 0x1a, &reg_short);
reg_short |= 0x8000; /* bypass Auto-Negotiation */
miiphy_write(dev->name, reg, 0x1a, reg_short);
miiphy_reset(dev->name, reg); /* reset MAC interface */
/* Reset access to Page 0 */
miiphy_write(dev->name, reg, 0x16, 0x0000);
}
#endif /* defined(CONFIG_M88E1112_PHY) */
miiphy_reset (dev->name, reg);
#if defined(CONFIG_440GX) || \
@ -1022,7 +1159,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
miiphy_write (dev->name, reg, 0x1f, 0x0000);
/* end Vitesse/Cicada errata */
}
#endif
#endif /* defined(CONFIG_CIS8201_PHY) */
#if defined(CONFIG_ET1011C_PHY)
/*
@ -1041,9 +1178,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
miiphy_write(dev->name, reg, 0x1c, 0x74f0);
}
#endif
#endif /* defined(CONFIG_ET1011C_PHY) */
#endif
#endif /* defined(CONFIG_440GX) ... */
/* Start/Restart autonegotiation */
phy_setup_aneg (dev->name, reg);
udelay (1000);
@ -1073,15 +1210,30 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
}
udelay (1000); /* 1 ms */
miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
}
puts (" done\n");
udelay (500000); /* another 500 ms (results in faster booting) */
}
#endif /* #ifndef CONFIG_CS8952_PHY */
speed = miiphy_speed (dev->name, reg);
duplex = miiphy_duplex (dev->name, reg);
get_speed:
if (reg == CONFIG_FIXED_PHY) {
for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
if (devnum == fixed_phy_port[i].devnum) {
speed = fixed_phy_port[i].speed;
duplex = fixed_phy_port[i].duplex;
break;
}
}
if (i == ARRAY_SIZE(fixed_phy_port)) {
printf("ERROR: PHY (%s) not configured correctly!\n",
dev->name);
return -1;
}
} else {
speed = miiphy_speed(dev->name, reg);
duplex = miiphy_duplex(dev->name, reg);
}
if (hw_p->print_speed) {
hw_p->print_speed = 0;

1212
cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c Normal file
View File

File diff suppressed because it is too large Load Diff

3
cpu/ppc4xx/Makefile
View File

@ -35,6 +35,9 @@ SOBJS += kgdb.o
COBJS := 40x_spd_sdram.o
COBJS += 44x_spd_ddr.o
COBJS += 44x_spd_ddr2.o
ifdef CONFIG_PPC4xx_DDR_AUTOCALIBRATION
COBJS += 4xx_ibm_ddr2_autocalib.o
endif
COBJS += 4xx_pci.o
COBJS += 4xx_pcie.o
COBJS += bedbug_405.o

37
cpu/ppc4xx/miiphy.c
View File

@ -180,8 +180,10 @@ int phy_setup_aneg (char *devname, unsigned char addr)
*
* sr: Currently on 460EX only EMAC0 works with MDIO, so we always
* return EMAC0 offset here
* vg: For 460EX/460GT if internal GPCS PHY address is specified
* return appropriate EMAC offset
*/
unsigned int miiphy_getemac_offset (void)
unsigned int miiphy_getemac_offset(u8 addr)
{
#if (defined(CONFIG_440) && \
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
@ -233,6 +235,35 @@ unsigned int miiphy_getemac_offset (void)
return 0x100;
#endif
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
u32 eoffset = 0;
switch (addr) {
#if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR)
case CONFIG_GPCS_PHY1_ADDR:
if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x100)))
eoffset = 0x100;
break;
#endif
#if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR)
case CONFIG_GPCS_PHY2_ADDR:
if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x300)))
eoffset = 0x300;
break;
#endif
#if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR)
case CONFIG_GPCS_PHY3_ADDR:
if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x400)))
eoffset = 0x400;
break;
#endif
default:
eoffset = 0;
break;
}
return eoffset;
#endif
return 0;
#endif
}
@ -262,7 +293,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
u32 emac_reg;
u32 sta_reg;
emac_reg = miiphy_getemac_offset();
emac_reg = miiphy_getemac_offset(addr);
/* wait for completion */
if (emac_miiphy_wait(emac_reg) != 0)
@ -311,7 +342,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg,
unsigned long sta_reg;
unsigned long emac_reg;
emac_reg = miiphy_getemac_offset ();
emac_reg = miiphy_getemac_offset(addr);
if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0)
return -1;

17
include/asm-ppc/ppc4xx-sdram.h
View File

@ -29,6 +29,7 @@
/*
* SDRAM Controller
*/
/*
* XXX - ToDo: Revisit file to change all these lower case defines into
* upper case. Also needs to be done in the controller setup code too
@ -256,6 +257,7 @@
#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
#if !defined(CONFIG_405EX)
/*
* Memory queue defines
*/
@ -293,7 +295,6 @@
#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
#if !defined(CONFIG_405EX)
/*
* Memory Bank 0-7 configuration
*/
@ -1401,4 +1402,18 @@
#endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
#ifndef __ASSEMBLY__
/*
* Prototypes
*/
void inline blank_string(int size);
inline void ppc4xx_ibm_ddr2_register_dump(void);
u32 mfdcr_any(u32);
void mtdcr_any(u32, u32);
u32 ddr_wrdtr(u32);
u32 ddr_clktr(u32);
void spd_ddr_init_hang(void);
u32 DQS_autocalibration(void);
#endif /* __ASSEMBLY__ */
#endif /* _PPC4xx_SDRAM_H_ */

6
include/configs/CPCI4052.h
View File

@ -146,6 +146,8 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
@ -219,6 +221,10 @@
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
/*-----------------------------------------------------------------------
* FLASH organization
*/

6
include/configs/CPCI405AB.h
View File

@ -144,6 +144,8 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
@ -215,6 +217,10 @@
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
/*-----------------------------------------------------------------------
* FLASH organization
*/

1
include/configs/PIP405.h
View File

@ -281,7 +281,6 @@
***********************************************************/
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_CS8952_PHY 1 /* its a CS8952 PHY */
/************************************************************
* RTC
***********************************************************/

19
include/configs/kilauea.h
View File

@ -223,6 +223,22 @@
*----------------------------------------------------------------------*/
#define CFG_MBYTES_SDRAM (256) /* 256MB */
/*
* CONFIG_PPC4xx_DDR_AUTOCALIBRATION
*
* Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
* SDRAM Controller DDR autocalibration values and takes a lot longer
* to run than Method_B.
* (See the Method_A and Method_B algorithm discription in the file:
* cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
* Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
*
* DDR Autocalibration Method_B is the default.
*/
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
#undef CONFIG_PPC4xx_DDR_METHOD_A
#define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE)
/* DDR1/2 SDRAM Device Control Register Data Values */
@ -386,6 +402,9 @@
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY1_ADDR 2
/* Debug messages for the DDR autocalibration */
#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
/*
* Default environment variables
*/

91
include/configs/ml507.h
View File

@ -17,106 +17,33 @@
#ifndef __CONFIG_H
#define __CONFIG_H
/*
#define DEBUG
#define ET_DEBUG
*/
/*CPU*/
#define CONFIG_XILINX_ML507 1
#define CONFIG_XILINX_440 1
/*CPU*/
#define CONFIG_440 1
#define CONFIG_4xx 1
#define CONFIG_XILINX_ML507 1
#include "../board/xilinx/ml507/xparameters.h"
/*Mem Map*/
#define CFG_SDRAM_BASE 0x0
#define CFG_SDRAM_SIZE_MB 256
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN ( 192 * 1024 )
#define CFG_MALLOC_LEN ( CFG_ENV_SIZE + 128 * 1024 )
/*Uart*/
#define CONFIG_XILINX_UARTLITE
#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE
#define CFG_BAUDRATE_TABLE { XPAR_UARTLITE_0_BAUDRATE }
#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR
/*Cmd*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_JFFS2
#define CONFIG_JFFS2_CMDLINE
#undef CONFIG_CMD_I2C
#undef CONFIG_CMD_DTT
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_PING
#undef CONFIG_CMD_DHCP
#undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_IMLS
/*Env*/
#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x20000
#define CFG_ENV_SECT_SIZE 0x20000
#define CFG_ENV_OFFSET 0x340000
#define CFG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CFG_ENV_OFFSET)
#define CFG_ENV_OFFSET 0x340000
#define CFG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CFG_ENV_OFFSET)
/*Misc*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "board:/# " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE ( CFG_CBSIZE + sizeof( CFG_PROMPT ) + 16 )
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x00400000 /* default load address */
#define CFG_EXTBDINFO 1 /* Extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_LOOPW /* enable loopw command */
#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE /* include version env variable */
#define CFG_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CFG_HUSH_PARSER /* Use the HUSH parser */
#define CFG_PROMPT_HUSH_PS2 "> "
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
#define CFG_BOOTMAPSZ ( 8 << 20 ) /* Initial Memory map for Linux */
#define CFG_PROMPT "ml507:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Stack*/
#define CFG_INIT_RAM_ADDR 0x800000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET ( CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE )
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*Speed*/
#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ
/*Flash*/
#define CFG_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR
#define CFG_FLASH_SIZE (32*1024*1024)
#define CFG_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_EMPTY_INFO 1
#define CFG_MAX_FLASH_BANKS 1
#define CFG_MAX_FLASH_SECT 259
#define CFG_FLASH_PROTECTION
#define MTDIDS_DEFAULT "nor0=ml507-flash"
#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)"
/*Generic Configs*/
#include <configs/xilinx-ppc440.h>
#endif /* __CONFIG_H */

49
include/configs/v5fx30teval.h Normal file
View File

@ -0,0 +1,49 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*CPU*/
#define CONFIG_440 1
#define CONFIG_XILINX_ML507 1
#include "../board/avnet/v5fx30teval/xparameters.h"
/*Mem Map*/
#define CFG_SDRAM_SIZE_MB 64
/*Env*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x20000
#define CFG_ENV_SECT_SIZE 0x20000
#define CFG_ENV_OFFSET 0x1A0000
#define CFG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CFG_ENV_OFFSET)
/*Misc*/
#define CFG_PROMPT "v5fx30t:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Flash*/
#define CFG_FLASH_SIZE (16*1024*1024)
#define CFG_MAX_FLASH_SECT 131
#define MTDIDS_DEFAULT "nor0=v5fx30t-flash"
#define MTDPARTS_DEFAULT "mtdparts=v5fx30t-flash:-(user)"
/*Generic Configs*/
#include <configs/xilinx-ppc440.h>
#endif /* __CONFIG_H */

49
include/configs/xilinx-ppc440-generic.h Normal file
View File

@ -0,0 +1,49 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*CPU*/
#define CONFIG_440 1
#define CONFIG_XILINX_PPC440_GENERIC 1
#include "../board/xilinx/ppc440-generic/xparameters.h"
/*Mem Map*/
#define CFG_SDRAM_SIZE_MB 256
/*Env*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x20000
#define CFG_ENV_SECT_SIZE 0x20000
#define CFG_ENV_OFFSET 0x340000
#define CFG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CFG_ENV_OFFSET)
/*Misc*/
#define CFG_PROMPT "board:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Flash*/
#define CFG_FLASH_SIZE (32*1024*1024)
#define CFG_MAX_FLASH_SECT 259
#define MTDIDS_DEFAULT "nor0=ml507-flash"
#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)"
/*Generic Configs*/
#include <configs/xilinx-ppc440.h>
#endif /* __CONFIG_H */

106
include/configs/xilinx-ppc440.h Normal file
View File

@ -0,0 +1,106 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __CONFIG_GEN_H
#define __CONFIG_GEN_H
/*
#define DEBUG
#define ET_DEBUG
*/
/*CPU*/
#define CONFIG_XILINX_440 1
#define CONFIG_440 1
#define CONFIG_4xx 1
/*Mem Map*/
#define CFG_SDRAM_BASE 0x0
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (192 * 1024)
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
/*Uart*/
#define CONFIG_XILINX_UARTLITE
#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE
#define CFG_BAUDRATE_TABLE { XPAR_UARTLITE_0_BAUDRATE }
#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR
/*Cmd*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_JFFS2
#define CONFIG_JFFS2_CMDLINE
#undef CONFIG_CMD_SPI
#undef CONFIG_CMD_I2C
#undef CONFIG_CMD_DTT
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_PING
#undef CONFIG_CMD_DHCP
#undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_IMLS
/*Misc*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CFG_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x00400000 /* default load address */
#define CFG_EXTBDINFO 1 /* Extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_LOOPW /* enable loopw command */
#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE /* include version env variable */
#define CFG_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CFG_HUSH_PARSER /* Use the HUSH parser */
#define CFG_PROMPT_HUSH_PS2 "> "
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */
/*Stack*/
#define CFG_INIT_RAM_ADDR 0x800000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*Speed*/
#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ
/*Flash*/
#define CFG_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR
#define CFG_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_EMPTY_INFO 1
#define CFG_MAX_FLASH_BANKS 1
#define CFG_FLASH_PROTECTION
#endif /* __CONFIG_H */

13
include/ppc440.h
View File

@ -2064,19 +2064,6 @@
#ifndef __ASSEMBLY__
static inline u32 get_mcsr(void)
{
u32 val;
asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
return val;
}
static inline void set_mcsr(u32 val)
{
asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
}
#endif /* _ASMLANGUAGE */
#endif /* __PPC440_H__ */

13
include/ppc4xx.h
View File

@ -203,6 +203,19 @@ typedef struct
unsigned long pllPlbDiv;
} PPC4xx_SYS_INFO;
static inline u32 get_mcsr(void)
{
u32 val;
asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
return val;
}
static inline void set_mcsr(u32 val)
{
asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
}
#endif /* __ASSEMBLY__ */
#endif /* __PPC4XX_H__ */

3
include/ppc4xx_enet.h
View File

@ -376,6 +376,7 @@ typedef struct emac_4xx_hw_st {
#define EMAC_M1_APP (0x08000000)
#define EMAC_M1_RSVD (0x06000000)
#define EMAC_M1_IST (0x01000000)
#define EMAC_M1_MF_1000GPCS (0x00C00000)
#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
#define EMAC_M1_MF_100MBPS (0x00400000)
#define EMAC_M1_RFS_MASK (0x00380000)
@ -394,6 +395,8 @@ typedef struct emac_4xx_hw_st {
#define EMAC_M1_MWSW (0x00007000)
#define EMAC_M1_JUMBO_ENABLE (0x00000800)
#define EMAC_M1_IPPA (0x000007c0)
#define EMAC_M1_IPPA_SET(id) (((id) & 0x1f) << 6)
#define EMAC_M1_IPPA_GET(id) (((id) >> 6) & 0x1f)
#define EMAC_M1_OBCI_GT100 (0x00000020)
#define EMAC_M1_OBCI_100 (0x00000018)
#define EMAC_M1_OBCI_83 (0x00000010)