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at91: Update board NAND drivers to current API.

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Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Scott Wood 2008-08-13 15:56:00 -05:00
parent d438d50848
commit aa5f75f20d
5 changed files with 90 additions and 95 deletions
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37
board/atmel/at91cap9adk/nand.c
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@ -37,36 +37,35 @@
#define MASK_ALE (1 << 21) /* our ALE is AD21 */ #define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */ #define MASK_CLE (1 << 22) /* our CLE is AD22 */
static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd) static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd,
int cmd, unsigned int ctrl)
{ {
struct nand_chip *this = mtd->priv; struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); if (ctrl & NAND_CTRL_CHANGE) {
switch (cmd) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
case NAND_CTL_SETCLE: IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
IO_ADDR_W |= MASK_CLE;
break; if (ctrl & NAND_CLE)
case NAND_CTL_SETALE: IO_ADDR_W |= MASK_CLE;
IO_ADDR_W |= MASK_ALE; if (ctrl & NAND_ALE)
break; IO_ADDR_W |= MASK_ALE;
case NAND_CTL_CLRNCE:
at91_set_gpio_value(AT91_PIN_PD15, 1); at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
break; this->IO_ADDR_W = (void *) IO_ADDR_W;
case NAND_CTL_SETNCE:
at91_set_gpio_value(AT91_PIN_PD15, 0);
break;
} }
this->IO_ADDR_W = (void *) IO_ADDR_W;
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
} }
int board_nand_init(struct nand_chip *nand) int board_nand_init(struct nand_chip *nand)
{ {
nand->eccmode = NAND_ECC_SOFT; nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16 #ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16; nand->options = NAND_BUSWIDTH_16;
#endif #endif
nand->hwcontrol = at91cap9adk_nand_hwcontrol; nand->cmd_ctrl = at91cap9adk_nand_hwcontrol;
nand->chip_delay = 20; nand->chip_delay = 20;
return 0; return 0;

37
board/atmel/at91sam9260ek/nand.c
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@ -37,27 +37,26 @@
#define MASK_ALE (1 << 21) /* our ALE is AD21 */ #define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */ #define MASK_CLE (1 << 22) /* our CLE is AD22 */
static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd, int cmd) static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd,
int cmd, unsigned int ctrl)
{ {
struct nand_chip *this = mtd->priv; struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); if (ctrl & NAND_CTRL_CHANGE) {
switch (cmd) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
case NAND_CTL_SETCLE: IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
IO_ADDR_W |= MASK_CLE;
break; if (ctrl & NAND_CLE)
case NAND_CTL_SETALE: IO_ADDR_W |= MASK_CLE;
IO_ADDR_W |= MASK_ALE; if (ctrl & NAND_ALE)
break; IO_ADDR_W |= MASK_ALE;
case NAND_CTL_CLRNCE:
at91_set_gpio_value(AT91_PIN_PC14, 1); at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
break; this->IO_ADDR_W = (void *) IO_ADDR_W;
case NAND_CTL_SETNCE:
at91_set_gpio_value(AT91_PIN_PC14, 0);
break;
} }
this->IO_ADDR_W = (void *) IO_ADDR_W;
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
} }
static int at91sam9260ek_nand_ready(struct mtd_info *mtd) static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
@ -67,11 +66,11 @@ static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand) int board_nand_init(struct nand_chip *nand)
{ {
nand->eccmode = NAND_ECC_SOFT; nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16 #ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16; nand->options = NAND_BUSWIDTH_16;
#endif #endif
nand->hwcontrol = at91sam9260ek_nand_hwcontrol; nand->cmd_ctrl = at91sam9260ek_nand_hwcontrol;
nand->dev_ready = at91sam9260ek_nand_ready; nand->dev_ready = at91sam9260ek_nand_ready;
nand->chip_delay = 20; nand->chip_delay = 20;

37
board/atmel/at91sam9261ek/nand.c
View File

@ -37,27 +37,26 @@
#define MASK_ALE (1 << 22) /* our ALE is AD22 */ #define MASK_ALE (1 << 22) /* our ALE is AD22 */
#define MASK_CLE (1 << 21) /* our CLE is AD21 */ #define MASK_CLE (1 << 21) /* our CLE is AD21 */
static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd, int cmd) static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd,
int cmd, unsigned int ctrl)
{ {
struct nand_chip *this = mtd->priv; struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); if (ctrl & NAND_CTRL_CHANGE) {
switch (cmd) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
case NAND_CTL_SETCLE: IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
IO_ADDR_W |= MASK_CLE;
break; if (ctrl & NAND_CLE)
case NAND_CTL_SETALE: IO_ADDR_W |= MASK_CLE;
IO_ADDR_W |= MASK_ALE; if (ctrl & NAND_ALE)
break; IO_ADDR_W |= MASK_ALE;
case NAND_CTL_CLRNCE:
at91_set_gpio_value(AT91_PIN_PC14, 1); at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
break; this->IO_ADDR_W = (void *) IO_ADDR_W;
case NAND_CTL_SETNCE:
at91_set_gpio_value(AT91_PIN_PC14, 0);
break;
} }
this->IO_ADDR_W = (void *) IO_ADDR_W;
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
} }
static int at91sam9261ek_nand_ready(struct mtd_info *mtd) static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
@ -67,11 +66,11 @@ static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand) int board_nand_init(struct nand_chip *nand)
{ {
nand->eccmode = NAND_ECC_SOFT; nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16 #ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16; nand->options = NAND_BUSWIDTH_16;
#endif #endif
nand->hwcontrol = at91sam9261ek_nand_hwcontrol; nand->cmd_ctrl = at91sam9261ek_nand_hwcontrol;
nand->dev_ready = at91sam9261ek_nand_ready; nand->dev_ready = at91sam9261ek_nand_ready;
nand->chip_delay = 20; nand->chip_delay = 20;

37
board/atmel/at91sam9263ek/nand.c
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@ -37,27 +37,26 @@
#define MASK_ALE (1 << 21) /* our ALE is AD21 */ #define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */ #define MASK_CLE (1 << 22) /* our CLE is AD22 */
static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd, int cmd) static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd,
int cmd, unsigned int ctrl)
{ {
struct nand_chip *this = mtd->priv; struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); if (ctrl & NAND_CTRL_CHANGE) {
switch (cmd) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
case NAND_CTL_SETCLE: IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
IO_ADDR_W |= MASK_CLE;
break; if (ctrl & NAND_CLE)
case NAND_CTL_SETALE: IO_ADDR_W |= MASK_CLE;
IO_ADDR_W |= MASK_ALE; if (ctrl & NAND_ALE)
break; IO_ADDR_W |= MASK_ALE;
case NAND_CTL_CLRNCE:
at91_set_gpio_value(AT91_PIN_PD15, 1); at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
break; this->IO_ADDR_W = (void *) IO_ADDR_W;
case NAND_CTL_SETNCE:
at91_set_gpio_value(AT91_PIN_PD15, 0);
break;
} }
this->IO_ADDR_W = (void *) IO_ADDR_W;
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
} }
static int at91sam9263ek_nand_ready(struct mtd_info *mtd) static int at91sam9263ek_nand_ready(struct mtd_info *mtd)
@ -67,11 +66,11 @@ static int at91sam9263ek_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand) int board_nand_init(struct nand_chip *nand)
{ {
nand->eccmode = NAND_ECC_SOFT; nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16 #ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16; nand->options = NAND_BUSWIDTH_16;
#endif #endif
nand->hwcontrol = at91sam9263ek_nand_hwcontrol; nand->cmd_ctrl = at91sam9263ek_nand_hwcontrol;
nand->dev_ready = at91sam9263ek_nand_ready; nand->dev_ready = at91sam9263ek_nand_ready;
nand->chip_delay = 20; nand->chip_delay = 20;

37
board/atmel/at91sam9rlek/nand.c
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@ -37,27 +37,26 @@
#define MASK_ALE (1 << 21) /* our ALE is AD21 */ #define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */ #define MASK_CLE (1 << 22) /* our CLE is AD22 */
static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd, int cmd) static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd,
int cmd, unsigned int ctrl)
{ {
struct nand_chip *this = mtd->priv; struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); if (ctrl & NAND_CTRL_CHANGE) {
switch (cmd) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
case NAND_CTL_SETCLE: IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
IO_ADDR_W |= MASK_CLE;
break; if (ctrl & NAND_CLE)
case NAND_CTL_SETALE: IO_ADDR_W |= MASK_CLE;
IO_ADDR_W |= MASK_ALE; if (ctrl & NAND_ALE)
break; IO_ADDR_W |= MASK_ALE;
case NAND_CTL_CLRNCE:
at91_set_gpio_value(AT91_PIN_PB6, 1); at91_set_gpio_value(AT91_PIN_PB6, !(ctrl & NAND_NCE));
break; this->IO_ADDR_W = (void *) IO_ADDR_W;
case NAND_CTL_SETNCE:
at91_set_gpio_value(AT91_PIN_PB6, 0);
break;
} }
this->IO_ADDR_W = (void *) IO_ADDR_W;
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
} }
static int at91sam9rlek_nand_ready(struct mtd_info *mtd) static int at91sam9rlek_nand_ready(struct mtd_info *mtd)
@ -67,11 +66,11 @@ static int at91sam9rlek_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand) int board_nand_init(struct nand_chip *nand)
{ {
nand->eccmode = NAND_ECC_SOFT; nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16 #ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16; nand->options = NAND_BUSWIDTH_16;
#endif #endif
nand->hwcontrol = at91sam9rlek_nand_hwcontrol; nand->cmd_ctrl = at91sam9rlek_nand_hwcontrol;
nand->dev_ready = at91sam9rlek_nand_ready; nand->dev_ready = at91sam9rlek_nand_ready;
nand->chip_delay = 20; nand->chip_delay = 20;