clk: clk_stm32f: Fix stm32_clk_get_rate()
Wrong parameter was passed to stm32_clk_pll48clk_rate(). sysclk (PLL_p output value) was passed instead of VCO value. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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167f2c90f6
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@ -230,7 +230,7 @@ static int configure_clocks(struct udevice *dev)
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}
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static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
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u32 sysclk)
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u32 vco)
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{
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struct stm32_rcc_regs *regs = priv->base;
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u16 pllq, pllm, pllsain, pllsaip;
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@ -254,7 +254,7 @@ static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
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return ((priv->hse_rate / pllm) * pllsain) / pllsaip;
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}
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/* PLL48CLK is selected from PLLQ */
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return sysclk / pllq;
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return vco / pllq;
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}
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static bool stm32_get_timpre(struct stm32_clk *priv)
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@ -337,6 +337,7 @@ static ulong stm32_clk_get_rate(struct clk *clk)
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struct stm32_clk *priv = dev_get_priv(clk->dev);
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struct stm32_rcc_regs *regs = priv->base;
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u32 sysclk = 0;
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u32 vco;
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u16 pllm, plln, pllp;
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if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
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@ -346,7 +347,8 @@ static ulong stm32_clk_get_rate(struct clk *clk)
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>> RCC_PLLCFGR_PLLN_SHIFT);
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pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
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>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
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sysclk = ((priv->hse_rate / pllm) * plln) / pllp;
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vco = (priv->hse_rate / pllm) * plln;
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sysclk = vco / pllp;
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} else {
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return -EINVAL;
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}
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@ -388,14 +390,14 @@ static ulong stm32_clk_get_rate(struct clk *clk)
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/* System clock is selected as SDMMC1 clock */
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return sysclk;
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else
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return stm32_clk_pll48clk_rate(priv, sysclk);
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return stm32_clk_pll48clk_rate(priv, vco);
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break;
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case STM32F7_APB2_CLOCK(SDMMC2):
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if (readl(®s->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL)
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/* System clock is selected as SDMMC2 clock */
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return sysclk;
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else
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return stm32_clk_pll48clk_rate(priv, sysclk);
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return stm32_clk_pll48clk_rate(priv, vco);
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break;
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/* For timer clock, an additionnal prescaler is used*/
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