Merge branch '2021-08-30-kconfig-migrations-part1' into next

- Begin merging some Kconfig migration, and CONFIG namespace cleanup series in. This gives us: - A number of I2C symbols migrated over - DWC2, i8042, altera_spi and a few other areas updated to use CFG not CONFIG for the concept of "configuration space" defines. - Rename CONFIG_EXTRA_ENV_BOARD_SETTINGS to EXTRA_ENV_BOARD_SETTINGS - Some dead code removal. - Rename a number of CONFIG symbols that were only referenced within the config header to not use CONFIG as a prefix.
2021-08-30 16:44:54 -04:00 · 2021-08-30 16:44:54 -04:00 · a85a8e63c5
commit a85a8e63c5
parent 9b0583a839 809c4f242f
789 changed files with 2834 additions and 7086 deletions
--- a/124
+++ b/124
@ -1461,129 +1461,7 @@ The following options need to be configured:
 		In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
 		with a list of GPIO LEDs that have inverted polarity.

- I2C Support:	CONFIG_SYS_I2C_LEGACY
-
-		Note: This is deprecated in favour of driver model. Use
-		CONFIG_DM_I2C instead.
-
-		This enable the legacy i2c subsystem, and will allow you to use
-		i2c commands at the u-boot command line (as long as you set
-		    CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE
-		    for defining speed and slave address
-		  - activate second bus with I2C_SOFT_DECLARATIONS2 define
-		    CONFIG_SYS_I2C_SOFT_SPEED_2 and CONFIG_SYS_I2C_SOFT_SLAVE_2
-		    for defining speed and slave address
-		  - activate third bus with I2C_SOFT_DECLARATIONS3 define
-		    CONFIG_SYS_I2C_SOFT_SPEED_3 and CONFIG_SYS_I2C_SOFT_SLAVE_3
-		    for defining speed and slave address
-		  - activate fourth bus with I2C_SOFT_DECLARATIONS4 define
-		    CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4
-		    for defining speed and slave address
-
-		- drivers/i2c/fsl_i2c.c:
-		  - activate i2c driver with CONFIG_SYS_I2C_FSL
-		    define CONFIG_SYS_FSL_I2C_OFFSET for setting the register
-		    offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and
-		    CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first
-		    bus.
-		  - If your board supports a second fsl i2c bus, define
-		    CONFIG_SYS_FSL_I2C2_OFFSET for the register offset
-		    CONFIG_SYS_FSL_I2C2_SPEED for the speed and
-		    CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the
-		    second bus.
-
-		- drivers/i2c/tegra_i2c.c:
-		  - activate this driver with CONFIG_SYS_I2C_TEGRA
-		  - This driver adds 4 i2c buses with a fix speed from
-		    100000 and the slave addr 0!
-
-		- drivers/i2c/ppc4xx_i2c.c
-		  - activate this driver with CONFIG_SYS_I2C_PPC4XX
-		  - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
-		  - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
-
-		- drivers/i2c/i2c_mxc.c
-		  - activate this driver with CONFIG_SYS_I2C_MXC
-		  - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1
-		  - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2
-		  - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
-		  - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
-		  - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
-		  - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
-		  - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
-		  - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
-		  - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
-		  - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
-		  - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED
-		  - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE
-		If those defines are not set, default value is 100000
-		for speed, and 0 for slave.
-
-		- drivers/i2c/rcar_i2c.c:
-		  - activate this driver with CONFIG_SYS_I2C_RCAR
-		  - This driver adds 4 i2c buses
-
-		- drivers/i2c/sh_i2c.c:
-		  - activate this driver with CONFIG_SYS_I2C_SH
-		  - This driver adds from 2 to 5 i2c buses
-
-		  - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
-		  - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
-		  - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
-		  - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
-		  - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
-		  - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
-		  - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
-		  - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
-		  - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
-		  - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
-		  - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses
-
-		- drivers/i2c/omap24xx_i2c.c
-		  - activate this driver with CONFIG_SYS_I2C_OMAP24XX
-		  - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
-		  - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
-		  - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
-		  - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
-		  - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
-		  - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
-		  - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
-		  - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
-		  - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
-		  - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
-
-		- drivers/i2c/s3c24x0_i2c.c:
-		  - activate this driver with CONFIG_SYS_I2C_S3C24X0
-		  - This driver adds i2c buses (11 for Exynos5250, Exynos5420
-		    9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
-		    with a fix speed from 100000 and the slave addr 0!
-
-		- drivers/i2c/ihs_i2c.c
-		  - activate this driver with CONFIG_SYS_I2C_IHS
-		  - CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0
-		  - CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0
-		  - CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0
-		  - CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1
-		  - CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1
-		  - CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1
-		  - CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2
-		  - CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2
-		  - CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2
-		  - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
-		  - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
-		  - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3
-		  - activate dual channel with CONFIG_SYS_I2C_IHS_DUAL
-		  - CONFIG_SYS_I2C_IHS_SPEED_0_1 speed channel 0_1
-		  - CONFIG_SYS_I2C_IHS_SLAVE_0_1 slave addr channel 0_1
-		  - CONFIG_SYS_I2C_IHS_SPEED_1_1 speed channel 1_1
-		  - CONFIG_SYS_I2C_IHS_SLAVE_1_1 slave addr channel 1_1
-		  - CONFIG_SYS_I2C_IHS_SPEED_2_1 speed channel 2_1
-		  - CONFIG_SYS_I2C_IHS_SLAVE_2_1 slave addr channel 2_1
-		  - CONFIG_SYS_I2C_IHS_SPEED_3_1 speed channel 3_1
-		  - CONFIG_SYS_I2C_IHS_SLAVE_3_1 slave addr channel 3_1
-
-		additional defines:
-
+- I2C Support:
 		CONFIG_SYS_NUM_I2C_BUSES
 		Hold the number of i2c buses you want to use.

--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@ -63,6 +63,12 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE
 endif
 endif

+config GICV2
+	bool
+
+config GICV3
+	bool
+
 config GIC_V3_ITS
 	bool "ARM GICV3 ITS"
 	select REGMAP
@ -797,6 +803,7 @@ config ARCH_IMX8M
 	select SYS_FSL_HAS_SEC if IMX_HAB
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
+	select SYS_I2C_MXC
 	select DM
 	select SUPPORT_SPL
 	imply CMD_DM
@ -952,6 +959,7 @@ config ARCH_SOCFPGA
 	select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select DM
 	select DM_SERIAL
+	select GICV2
 	select GPIO_EXTRA_HEADER
 	select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select OF_CONTROL
@ -1062,6 +1070,7 @@ config ARCH_VERSAL
 	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
+	select GICV3
 	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SOC_DEVICE
@ -1131,6 +1140,7 @@ config ARCH_ZYNQMP
 	select DM_SPI if SPI
 	select DM_SPI_FLASH if DM_SPI
 	select FIRMWARE
+	select GICV2
 	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SPL_BOARD_INIT if SPL
@ -1880,6 +1890,7 @@ config TARGET_DURIAN
 config TARGET_PRESIDIO_ASIC
 	bool "Support Cortina Presidio ASIC Platform"
 	select ARM64
+	select GICV2

 config TARGET_XENGUEST_ARM64
 	bool "Xen guest ARM64"
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@ -20,6 +20,7 @@ config ARCH_LS1021A
 	select SYS_FSL_SEC_LE
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
+	select SYS_I2C_MXC
 	imply CMD_PCI
 	imply SCSI
 	imply SCSI_AHCI
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@ -4,6 +4,7 @@ config ARCH_LS1012A
 	select ARM_ERRATA_855873 if !TFABOOT
 	select FSL_LAYERSCAPE
 	select FSL_LSCH2
+	select GICV2
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR_BE
@ -25,6 +26,7 @@ config ARCH_LS1028A
 	select ARMV8_SET_SMPEN
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
+	select GICV3
 	select NXP_LSCH3_2
 	select SYS_FSL_HAS_CCI400
 	select SYS_FSL_SRDS_1
@ -58,6 +60,7 @@ config ARCH_LS1043A
 	select ARM_ERRATA_855873 if !TFABOOT
 	select FSL_LAYERSCAPE
 	select FSL_LSCH2
+	select GICV2
 	select HAS_FSL_XHCI_USB if USB_HOST
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
@ -84,12 +87,14 @@ config ARCH_LS1043A
 	select SYS_I2C_MXC_I2C3 if !DM_I2C
 	select SYS_I2C_MXC_I2C4 if !DM_I2C
 	imply CMD_PCI
+	imply ID_EEPROM

 config ARCH_LS1046A
 	bool
 	select ARMV8_SET_SMPEN
 	select FSL_LAYERSCAPE
 	select FSL_LSCH2
+	select GICV2
 	select HAS_FSL_XHCI_USB if USB_HOST
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
@ -117,8 +122,10 @@ config ARCH_LS1046A
 	select SYS_I2C_MXC_I2C2 if !DM_I2C
 	select SYS_I2C_MXC_I2C3 if !DM_I2C
 	select SYS_I2C_MXC_I2C4 if !DM_I2C
+	imply ID_EEPROM
 	imply SCSI
 	imply SCSI_AHCI
+	imply SPL_SYS_I2C_LEGACY

 config ARCH_LS1088A
 	bool
@ -126,6 +133,7 @@ config ARCH_LS1088A
 	select ARM_ERRATA_855873 if !TFABOOT
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
+	select GICV3
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
@ -158,7 +166,9 @@ config ARCH_LS1088A
 	select SYS_I2C_MXC_I2C3 if !TFABOOT
 	select SYS_I2C_MXC_I2C4 if !TFABOOT
 	select RESV_RAM if GIC_V3_ITS
+	imply ID_EEPROM
 	imply SCSI
+	imply SPL_SYS_I2C_LEGACY
 	imply PANIC_HANG

 config ARCH_LS2080A
@ -170,6 +180,7 @@ config ARCH_LS2080A
 	select ARM_ERRATA_833471
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
+	select GICV3
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
@ -210,12 +221,15 @@ config ARCH_LS2080A
 	select SYS_I2C_MXC_I2C4 if !TFABOOT
 	select RESV_RAM if GIC_V3_ITS
 	imply DISTRO_DEFAULTS
+	imply ID_EEPROM
 	imply PANIC_HANG
+	imply SPL_SYS_I2C_LEGACY

 config ARCH_LX2162A
 	bool
 	select ARMV8_SET_SMPEN
 	select FSL_LSCH3
+	select GICV3
 	select NXP_LSCH3_2
 	select SYS_HAS_SERDES
 	select SYS_FSL_SRDS_1
@ -242,11 +256,13 @@ config ARCH_LX2162A
 	imply PANIC_HANG
 	imply SCSI
 	imply SCSI_AHCI
+	imply SPL_SYS_I2C_LEGACY

 config ARCH_LX2160A
 	bool
 	select ARMV8_SET_SMPEN
 	select FSL_LSCH3
+	select GICV3
 	select HAS_FSL_XHCI_USB if USB_HOST
 	select NXP_LSCH3_2
 	select SYS_HAS_SERDES
@ -272,9 +288,11 @@ config ARCH_LX2160A
 	select SYS_I2C_MXC
 	select RESV_RAM if GIC_V3_ITS
 	imply DISTRO_DEFAULTS
+	imply ID_EEPROM
 	imply PANIC_HANG
 	imply SCSI
 	imply SCSI_AHCI
+	imply SPL_SYS_I2C_LEGACY

 config FSL_LSCH2
 	bool
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@ -329,7 +329,7 @@ static void erratum_rcw_src(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
 static void erratum_a009203(void)
 {
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 	u8 __iomem *ptr;
 #ifdef I2C1_BASE_ADDR
 	ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@ -88,7 +88,7 @@ void board_init_f(ulong dummy)
 	preloader_console_init();
 	spl_set_bd();

-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 #ifdef CONFIG_SPL_I2C
 	i2c_init_all();
 #endif
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@ -123,7 +123,6 @@
 #elif defined(CONFIG_ARCH_LS1088A)
 #define CONFIG_SYS_FSL_NUM_CC_PLLS		3
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
-#define CONFIG_GICV3
 #define CONFIG_SYS_PAGE_SIZE		0x10000

 #define	SRDS_MAX_LANES	4
@ -183,10 +182,6 @@
 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define TZPC_BASE				0x02200000
 #define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_EARLY_INIT
-#endif
 #define SRDS_MAX_LANES  8
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT		6
@ -239,7 +234,6 @@
 #elif defined(CONFIG_ARCH_LS1028A)
 #define CONFIG_SYS_FSL_NUM_CC_PLLS		3
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
-#define CONFIG_GICV3
 #define CONFIG_FSL_TZPC_BP147
 #define CONFIG_FSL_TZASC_400

--- a/arch/arm/mach-davinci/include/mach/davinci_misc.h
+++ b/arch/arm/mach-davinci/include/mach/davinci_misc.h
@ -35,7 +35,6 @@ struct lpsc_resource {
 	const int	lpsc_no;
 };

-int dvevm_read_mac_address(uint8_t *buf);
 void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
 int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
 int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
--- a/arch/arm/mach-davinci/misc.c
+++ b/arch/arm/mach-davinci/misc.c
@ -41,33 +41,6 @@ int dram_init_banksize(void)
 #endif

 #ifdef CONFIG_DRIVER_TI_EMAC
-/*
- * Read ethernet MAC address from EEPROM for DVEVM compatible boards.
- * Returns 1 if found, 0 otherwise.
- */
-int dvevm_read_mac_address(uint8_t *buf)
-{
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
-	/* Read MAC address. */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00,
-		CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))
-		goto i2cerr;
-
-	/* Check that MAC address is valid. */
-	if (!is_valid_ethaddr(buf))
-		goto err;
-
-	return 1; /* Found */
-
-i2cerr:
-	printf("Read from EEPROM @ 0x%02x failed\n",
-		CONFIG_SYS_I2C_EEPROM_ADDR);
-err:
-#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
-
-	return 0;
-}
-
 /*
 * Set the mii mode as MII or RMII
 */
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@ -141,7 +141,7 @@ if ARCH_EXYNOS7
 choice
 	prompt "EXYNOS7 board select"

-config  TARGET_ESPRESSO7420
+config TARGET_ESPRESSO7420
 	bool "ESPRESSO7420 board"
 	select ARM64
 	select ARMV8_MULTIENTRY
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@ -91,18 +91,6 @@
 #define CONFIG_SYS_ATA_BASE_ADDR	MV_SATA_BASE
 #endif /* CONFIG_IDE */

-/*
- * I2C related stuff
- */
-#if defined(CONFIG_CMD_I2C) && !CONFIG_IS_ENABLED(DM_I2C)
-#ifndef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MVTWSI
-#endif
-#define CONFIG_SYS_I2C_SLAVE		0x0
-#define CONFIG_SYS_I2C_SPEED		100000
-#endif
-
 /* Use common timer */
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 #define CONFIG_SYS_TIMER_COUNTER	(MVEBU_TIMER_BASE + 0x14)
--- a/arch/arm/mach-mvebu/include/mach/config.h
+++ b/arch/arm/mach-mvebu/include/mach/config.h
@ -63,8 +63,6 @@
 #ifndef CONFIG_SYS_I2C_SOFT
 #define CONFIG_I2C_MVTWSI
 #endif
-#define CONFIG_SYS_I2C_SLAVE		0x0
-#define CONFIG_SYS_I2C_SPEED		100000
 #endif

 /* Use common timer */
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@ -203,7 +203,7 @@ void spl_board_init(void)
 	gpmc_init();
 #endif
 #if defined(CONFIG_SPL_I2C) && !CONFIG_IS_ENABLED(DM_I2C)
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW)
 	arch_misc_init();
--- a/arch/arm/mach-omap2/clocks-common.c
+++ b/arch/arm/mach-omap2/clocks-common.c
@ -918,8 +918,8 @@ void gpi2c_init(void)
 	static int gpi2c = 1;

 	if (gpi2c) {
-		i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
-			 CONFIG_SYS_OMAP24_I2C_SLAVE);
+		i2c_init(CONFIG_SYS_I2C_SPEED,
+			 CONFIG_SYS_I2C_SLAVE);
 		gpi2c = 0;
 	}
 }
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@ -4,61 +4,73 @@ menu "Select Target SoC"

 config R8A774A1
 	bool "Renesas SoC R8A774A1"
+	select GICV2
 	imply CLK_R8A774A1
 	imply PINCTRL_PFC_R8A774A1

 config R8A774B1
 	bool "Renesas SoC R8A774B1"
+	select GICV2
 	imply CLK_R8A774B1
 	imply PINCTRL_PFC_R8A774B1

 config R8A774C0
 	bool "Renesas SoC R8A774C0"
+	select GICV2
 	imply CLK_R8A774C0
 	imply PINCTRL_PFC_R8A774C0

 config R8A774E1
 	bool "Renesas SoC R8A774E1"
+	select GICV2
 	imply CLK_R8A774E1
 	imply PINCTRL_PFC_R8A774E1

 config R8A7795
 	bool "Renesas SoC R8A7795"
+	select GICV2
 	imply CLK_R8A7795
 	imply PINCTRL_PFC_R8A7795

 config R8A7796
 	bool "Renesas SoC R8A7796"
+	select GICV2
 	imply CLK_R8A7796
 	imply PINCTRL_PFC_R8A7796

 config R8A77965
 	bool "Renesas SoC R8A77965"
+	select GICV2
 	imply CLK_R8A77965
 	imply PINCTRL_PFC_R8A77965

 config R8A77970
 	bool "Renesas SoC R8A77970"
+	select GICV2
 	imply CLK_R8A77970
 	imply PINCTRL_PFC_R8A77970

 config R8A77980
 	bool "Renesas SoC R8A77980"
+	select GICV2
 	imply CLK_R8A77980
 	imply PINCTRL_PFC_R8A77980

 config R8A77990
 	bool "Renesas SoC R8A77990"
+	select GICV2
 	imply CLK_R8A77990
 	imply PINCTRL_PFC_R8A77990

 config R8A77995
 	bool "Renesas SoC R8A77995"
+	select GICV2
 	imply CLK_R8A77995
 	imply PINCTRL_PFC_R8A77995

 config R8A779A0
 	bool "Renesas SoC R8A779A0"
+	select GICV3
 	imply CLK_R8A779A0
 	imply PINCTRL_PFC_R8A779A0

--- a/arch/arm/mach-rmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7790.h
@ -10,10 +10,6 @@

 #include "rcar-base.h"

-/* SH-I2C */
-#define CONFIG_SYS_I2C_SH_BASE2	0xE6520000
-#define CONFIG_SYS_I2C_SH_BASE3	0xE60B0000
-
 /* Module stop control/status register bits */
 #define MSTP0_BITS	0x00640801
 #define MSTP1_BITS	0xDB6E9BDF
--- a/arch/arm/mach-rmobile/include/mach/r8a7791.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7791.h
@ -13,9 +13,6 @@
 * R-Car (R8A7791) I/O Addresses
 */

-/* SH-I2C */
-#define CONFIG_SYS_I2C_SH_BASE2	0xE60B0000
-
 /* SDHI */
 #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
 #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
--- a/arch/arm/mach-rmobile/include/mach/r8a7792.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7792.h
@ -10,10 +10,6 @@

 #include "rcar-base.h"

-/* SH-I2C */
-#define CONFIG_SYS_I2C_SH_BASE2	0xE6520000
-#define CONFIG_SYS_I2C_SH_BASE3	0xE60B0000
-
 /* Module stop control/status register bits */
 #define MSTP0_BITS	0x00400801
 #define MSTP1_BITS	0x9B6F987F
--- a/arch/arm/mach-rmobile/include/mach/r8a7793.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7793.h
@ -14,9 +14,6 @@
 * R8A7793 I/O Addresses
 */

-/* SH-I2C */
-#define CONFIG_SYS_I2C_SH_BASE2	0xE60B0000
-
 /* SDHI */
 #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
 #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
--- a/arch/arm/mach-rmobile/include/mach/r8a7794.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7794.h
@ -10,9 +10,6 @@

 #include "rcar-base.h"

-/* SH-I2C */
-#define CONFIG_SYS_I2C_SH_BASE2	0xE60B0000
-
 /* Module stop control/status register bits */
 #define MSTP0_BITS	0x00440801
 #define MSTP1_BITS	0x936899DA
--- a/arch/arm/mach-rmobile/include/mach/rcar-base.h
+++ b/arch/arm/mach-rmobile/include/mach/rcar-base.h
@ -70,14 +70,6 @@
 #define SMSTPCR10		0xE6150998
 #define SMSTPCR11		0xE615099C

-/*
- * SH-I2C
- * Ch2 and ch3 are different address. These are defined
- * in the header of each SoCs.
- */
-#define CONFIG_SYS_I2C_SH_BASE0	0xE6500000
-#define CONFIG_SYS_I2C_SH_BASE1	0xE6510000
-
 /* RCAR-I2C */
 #define CONFIG_SYS_RCAR_I2C0_BASE	0xE6508000
 #define CONFIG_SYS_RCAR_I2C1_BASE	0xE6518000
--- a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
+++ b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
@ -74,9 +74,6 @@
 #define PUEN_USB1_OVC   (1 << 2)
 #define PUEN_USB1_PWEN  (1 << 1)

-/* IICDVFS (I2C) */
-#define CONFIG_SYS_I2C_SH_BASE0	0xE60B0000
-
 #ifndef __ASSEMBLY__
 #include <asm/types.h>
 #include <linux/bitops.h>
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@ -209,6 +209,8 @@ config MACH_SUN4I
 	select DRAM_SUN4I
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
+	imply SPL_SYS_I2C_LEGACY
+	imply SYS_I2C_LEGACY

 config MACH_SUN5I
 	bool "sun5i (Allwinner A13)"
@ -219,6 +221,8 @@ config MACH_SUN5I
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 	imply CONS_INDEX_2 if !DM_SERIAL
+	imply SPL_SYS_I2C_LEGACY
+	imply SYS_I2C_LEGACY

 config MACH_SUN6I
 	bool "sun6i (Allwinner A31)"
@ -245,6 +249,8 @@ config MACH_SUN7I
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+	imply SPL_SYS_I2C_LEGACY
+	imply SYS_I2C_LEGACY

 config MACH_SUN8I_A23
 	bool "sun8i (Allwinner A23)"
@ -303,6 +309,7 @@ config MACH_SUN8I_R40
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_32BIT
 	select PHY_SUN4I_USB
+	imply SPL_SYS_I2C_LEGACY

 config MACH_SUN8I_V3S
 	bool "sun8i (Allwinner V3/V3s/S3/S3L)"
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@ -124,6 +124,7 @@ config TEGRA124

 config TEGRA210
 	bool "Tegra210 family"
+	select GICV2
 	select TEGRA_ARMV8_COMMON
 	select TEGRA_CLKRST
 	select TEGRA_GPIO
@ -137,6 +138,7 @@ config TEGRA210
 config TEGRA186
 	bool "Tegra186 family"
 	select DM_MAILBOX
+	select GICV2
 	select TEGRA186_BPMP
 	select TEGRA186_CLOCK
 	select TEGRA186_GPIO
--- a/arch/arm/mach-versal/Kconfig
+++ b/arch/arm/mach-versal/Kconfig
@ -21,9 +21,6 @@ config SYS_CONFIG_NAME
 	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
 	  will be used for board configuration.

-config GICV3
-	def_bool y
-
 config SYS_MALLOC_LEN
 	default 0x2000000

--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@ -34,148 +34,6 @@ static struct {
 #endif
 };

-#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
-
-/* private structure for mpc83xx pcie hose */
-static struct mpc83xx_pcie_priv {
-	u8 index;
-} pcie_priv[PCIE_MAX_BUSES] = {
-	{
-		/* pcie controller 1 */
-		.index = 0,
-	},
-	{
-		/* pcie controller 2 */
-		.index = 1,
-	},
-};
-
-static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
-{
-	int bus = PCI_BUS(dev) - hose->first_busno;
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
-	pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
-	struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
-	u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
-	u32 dev_base = bus << 24 | devfn << 16;
-
-	if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
-		return -1;
-	/*
-	 * Workaround for the HW bug: for Type 0 configure transactions the
-	 * PCI-E controller does not check the device number bits and just
-	 * assumes that the device number bits are 0.
-	 */
-	if (devfn & 0xf8)
-		return -1;
-
-	out_le32(&out_win->tarl, dev_base);
-	return 0;
-}
-
-#define cfg_read(val, addr, type, op) \
-	do { *val = op((type)(addr)); } while (0)
-#define cfg_write(val, addr, type, op) \
-	do { op((type *)(addr), (val)); } while (0)
-
-#define cfg_read_err(val) do { *val = -1; } while (0)
-#define cfg_write_err(val) do { } while (0)
-
-#define PCIE_OP(rw, size, type, op)					\
-static int pcie_##rw##_config_##size(struct pci_controller *hose,	\
-				     pci_dev_t dev, int offset,		\
-				     type val)				\
-{									\
-	int ret;							\
-									\
-	ret = mpc83xx_pcie_remap_cfg(hose, dev);			\
-	if (ret) {							\
-		cfg_##rw##_err(val); 					\
-		return ret; 						\
-	}								\
-	cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op);	\
-	return 0;							\
-}
-
-PCIE_OP(read, byte, u8 *, in_8)
-PCIE_OP(read, word, u16 *, in_le16)
-PCIE_OP(read, dword, u32 *, in_le32)
-PCIE_OP(write, byte, u8, out_8)
-PCIE_OP(write, word, u16, out_le16)
-PCIE_OP(write, dword, u32, out_le32)
-
-static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
-				       u8 link)
-{
-	extern void disable_addr_trans(void); /* start.S */
-	static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
-	struct pci_controller *hose = &pcie_hose[bus];
-	int i;
-
-	/*
-	 * There are no spare BATs to remap all PCI-E windows for U-Boot, so
-	 * disable translations. In general, this is not great solution, and
-	 * that's why we don't register PCI-E hoses by default.
-	 */
-	disable_addr_trans();
-
-	for (i = 0; i < 2; i++, reg++) {
-		if (reg->size == 0)
-			break;
-
-		hose->regions[i] = *reg;
-		hose->region_count++;
-	}
-
-	i = hose->region_count++;
-	hose->regions[i].bus_start = 0;
-	hose->regions[i].phys_start = 0;
-	hose->regions[i].size = gd->ram_size;
-	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
-
-	i = hose->region_count++;
-	hose->regions[i].bus_start = CONFIG_SYS_IMMR;
-	hose->regions[i].phys_start = CONFIG_SYS_IMMR;
-	hose->regions[i].size = 0x100000;
-	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
-
-	hose->first_busno = pci_last_busno() + 1;
-	hose->last_busno = 0xff;
-
-	hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
-
-	hose->priv_data = &pcie_priv[bus];
-
-	pci_set_ops(hose,
-			pcie_read_config_byte,
-			pcie_read_config_word,
-			pcie_read_config_dword,
-			pcie_write_config_byte,
-			pcie_write_config_word,
-			pcie_write_config_dword);
-
-	if (!link)
-		hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
-
-	pci_register_hose(hose);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
-	printf("PCI:   Bus Dev VenId DevId Class Int\n");
-#endif
-	/*
-	 * Hose scan.
-	 */
-	hose->last_busno = pci_hose_scan(hose);
-}
-
-#else
-
-static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
-				       u8 link) {}
-
-#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
-
 int get_pcie_clk(int index)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
@ -340,8 +198,6 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
 		printf("link\n");
 	else
 		printf("No link\n");
-
-	mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
 }

 /*
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@ -724,6 +724,7 @@ config ARCH_T2080
 	imply CMD_NAND
 	imply CMD_REGINFO
 	imply FSL_SATA
+	imply ID_EEPROM

 config ARCH_T4240
 	bool
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@ -29,7 +29,6 @@ obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o
 endif
 obj-$(CONFIG_CPM2)	+= commproc.o

-obj-$(CONFIG_CPM2)	+= ether_fcc.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_FSL_CORENET) += liodn.o
 obj-$(CONFIG_MP)	+= mp.o
--- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
@ -1,460 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * MPC8560 FCC Fast Ethernet
- * Copyright (c) 2003 Motorola,Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * Copyright (c) 2000 MontaVista Software, Inc.   Dan Malek (dmalek@jlc.net)
- *
- * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- */
-
-/*
- * MPC8560 FCC Fast Ethernet
- * Basic ET HW initialization and packet RX/TX routines
- *
- * This code will not perform the IO port configuration. This should be
- * done in the iop_conf_t structure specific for the board.
- *
- * TODO:
- * add a PHY driver to do the negotiation
- * reflect negotiation results in FPSMR
- * look for ways to configure the board specific stuff elsewhere, eg.
- *    config_xxx.h or the board directory
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/cpm_85xx.h>
-#include <command.h>
-#include <config.h>
-#include <net.h>
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-#endif
-
-#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET)
-
-static struct ether_fcc_info_s
-{
-	int ether_index;
-	int proff_enet;
-	ulong cpm_cr_enet_sblock;
-	ulong cpm_cr_enet_page;
-	ulong cmxfcr_mask;
-	ulong cmxfcr_value;
-}
-	ether_fcc_info[] =
-{
-#ifdef CONFIG_ETHER_ON_FCC1
-{
-	0,
-	PROFF_FCC1,
-	CPM_CR_FCC1_SBLOCK,
-	CPM_CR_FCC1_PAGE,
-	CONFIG_SYS_CMXFCR_MASK1,
-	CONFIG_SYS_CMXFCR_VALUE1
-},
-#endif
-
-#ifdef CONFIG_ETHER_ON_FCC2
-{
-	1,
-	PROFF_FCC2,
-	CPM_CR_FCC2_SBLOCK,
-	CPM_CR_FCC2_PAGE,
-	CONFIG_SYS_CMXFCR_MASK2,
-	CONFIG_SYS_CMXFCR_VALUE2
-},
-#endif
-
-#ifdef CONFIG_ETHER_ON_FCC3
-{
-	2,
-	PROFF_FCC3,
-	CPM_CR_FCC3_SBLOCK,
-	CPM_CR_FCC3_PAGE,
-	CONFIG_SYS_CMXFCR_MASK3,
-	CONFIG_SYS_CMXFCR_VALUE3
-},
-#endif
-};
-
-/*---------------------------------------------------------------------*/
-
-/* Maximum input DMA size.  Must be a should(?) be a multiple of 4. */
-#define PKT_MAXDMA_SIZE         1520
-
-/* The FCC stores dest/src/type, data, and checksum for receive packets. */
-#define PKT_MAXBUF_SIZE         1518
-#define PKT_MINBUF_SIZE         64
-
-/* Maximum input buffer size.  Must be a multiple of 32. */
-#define PKT_MAXBLR_SIZE         1536
-
-#define TOUT_LOOP 1000000
-
-#define TX_BUF_CNT 2
-
-static uint rxIdx;	/* index of the current RX buffer */
-static uint txIdx;	/* index of the current TX buffer */
-
-/*
- * FCC Ethernet Tx and Rx buffer descriptors.
- * Provide for Double Buffering
- * Note: PKTBUFSRX is defined in net.h
- */
-
-typedef volatile struct rtxbd {
-    cbd_t rxbd[PKTBUFSRX];
-    cbd_t txbd[TX_BUF_CNT];
-} RTXBD;
-
-/*  Good news: the FCC supports external BDs! */
-#ifdef __GNUC__
-static RTXBD rtx __attribute__ ((aligned(8)));
-#else
-#error "rtx must be 64-bit aligned"
-#endif
-
-#undef ET_DEBUG
-
-static int fec_send(struct eth_device *dev, void *packet, int length)
-{
-    int i = 0;
-    int result = 0;
-
-    if (length <= 0) {
-	printf("fec: bad packet size: %d\n", length);
-	goto out;
-    }
-
-    for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
-	if (i >= TOUT_LOOP) {
-	    printf("fec: tx buffer not ready\n");
-	    goto out;
-	}
-    }
-
-    rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
-    rtx.txbd[txIdx].cbd_datlen = length;
-    rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \
-			       BD_ENET_TX_TC | BD_ENET_TX_PAD);
-
-    for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
-	if (i >= TOUT_LOOP) {
-	    printf("fec: tx error\n");
-	    goto out;
-	}
-    }
-
-#ifdef ET_DEBUG
-    printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc);
-    printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length);
-    for(i=0;i<(length/16 + 1);i++) {
-	 printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\
-    *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \
-    *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3));
-    }
-#endif
-
-    /* return only status bits */
-    result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
-    txIdx = (txIdx + 1) % TX_BUF_CNT;
-
-out:
-    return result;
-}
-
-static int fec_recv(struct eth_device* dev)
-{
-    int length;
-
-    for (;;)
-    {
-	if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
-	    length = -1;
-	    break;     /* nothing received - leave for() loop */
-	}
-	length = rtx.rxbd[rxIdx].cbd_datlen;
-
-	if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
-	    printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
-	}
-	else {
-	    /* Pass the packet up to the protocol layers. */
-	    net_process_received_packet(net_rx_packets[rxIdx], length - 4);
-	}
-
-
-	/* Give the buffer back to the FCC. */
-	rtx.rxbd[rxIdx].cbd_datlen = 0;
-
-	/* wrap around buffer index when necessary */
-	if ((rxIdx + 1) >= PKTBUFSRX) {
-	    rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
-	    rxIdx = 0;
-	}
-	else {
-	    rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
-	    rxIdx++;
-	}
-    }
-    return length;
-}
-
-
-static int fec_init(struct eth_device* dev, struct bd_info *bis)
-{
-    struct ether_fcc_info_s * info = dev->priv;
-    int i;
-    volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-    volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
-    fcc_enet_t *pram_ptr;
-    unsigned long mem_addr;
-
-#if 0
-    mii_discover_phy();
-#endif
-
-    /* 28.9 - (1-2): ioports have been set up already */
-
-    /* 28.9 - (3): connect FCC's tx and rx clocks */
-    cpm->im_cpm_mux.cmxuar = 0; /* ATM */
-    cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
-							info->cmxfcr_value;
-
-    /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
-    if(info->ether_index == 0) {
-	cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
-    } else if (info->ether_index == 1) {
-	cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
-    } else if (info->ether_index == 2) {
-	cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
-    }
-
-    /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
-    if(info->ether_index == 0) {
-	cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
-    } else if (info->ether_index == 1){
-	cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
-    } else if (info->ether_index == 2){
-	cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
-    }
-
-    /* 28.9 - (6): FDSR: Ethernet Syn */
-    if(info->ether_index == 0) {
-	cpm->im_cpm_fcc1.fdsr = 0xD555;
-    } else if (info->ether_index == 1) {
-	cpm->im_cpm_fcc2.fdsr = 0xD555;
-    } else if (info->ether_index == 2) {
-	cpm->im_cpm_fcc3.fdsr = 0xD555;
-    }
-
-    /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
-    rxIdx = 0;
-    txIdx = 0;
-
-    /* Setup Receiver Buffer Descriptors */
-    for (i = 0; i < PKTBUFSRX; i++)
-    {
-      rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
-      rtx.rxbd[i].cbd_datlen = 0;
-      rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i];
-    }
-    rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
-
-    /* Setup Ethernet Transmitter Buffer Descriptors */
-    for (i = 0; i < TX_BUF_CNT; i++)
-    {
-      rtx.txbd[i].cbd_sc = 0;
-      rtx.txbd[i].cbd_datlen = 0;
-      rtx.txbd[i].cbd_bufaddr = 0;
-    }
-    rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
-
-    /* 28.9 - (7): initialize parameter ram */
-    pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]);
-
-    /* clear whole structure to make sure all reserved fields are zero */
-    memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
-
-    /*
-     * common Parameter RAM area
-     *
-     * Allocate space in the reserved FCC area of DPRAM for the
-     * internal buffers.  No one uses this space (yet), so we
-     * can do this.  Later, we will add resource management for
-     * this area.
-     * CPM_FCC_SPECIAL_BASE:	0xB000 for MPC8540, MPC8560
-     *				0x9000 for MPC8541, MPC8555
-     */
-    mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
-    pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
-    pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
-    /*
-     * Set maximum bytes per receive buffer.
-     * It must be a multiple of 32.
-     */
-    pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */
-    /* localbus SDRAM should be preferred */
-    pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
-				       CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
-    pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
-    pram_ptr->fen_genfcc.fcc_rbdstat = 0;
-    pram_ptr->fen_genfcc.fcc_rbdlen = 0;
-    pram_ptr->fen_genfcc.fcc_rdptr = 0;
-    /* localbus SDRAM should be preferred */
-    pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
-				       CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
-    pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
-    pram_ptr->fen_genfcc.fcc_tbdstat = 0;
-    pram_ptr->fen_genfcc.fcc_tbdlen = 0;
-    pram_ptr->fen_genfcc.fcc_tdptr = 0;
-
-    /* protocol-specific area */
-    pram_ptr->fen_statbuf = 0x0;
-    pram_ptr->fen_cmask = 0xdebb20e3;	/* CRC mask */
-    pram_ptr->fen_cpres = 0xffffffff;	/* CRC preset */
-    pram_ptr->fen_crcec = 0;
-    pram_ptr->fen_alec = 0;
-    pram_ptr->fen_disfc = 0;
-    pram_ptr->fen_retlim = 15;		/* Retry limit threshold */
-    pram_ptr->fen_retcnt = 0;
-    pram_ptr->fen_pper = 0;
-    pram_ptr->fen_boffcnt = 0;
-    pram_ptr->fen_gaddrh = 0;
-    pram_ptr->fen_gaddrl = 0;
-    pram_ptr->fen_mflr = PKT_MAXBUF_SIZE;   /* maximum frame length register */
-    /*
-     * Set Ethernet station address.
-     *
-     * This is supplied in the board information structure, so we
-     * copy that into the controller.
-     * So far we have only been given one Ethernet address. We make
-     * it unique by setting a few bits in the upper byte of the
-     * non-static part of the address.
-     */
-#define ea eth_get_ethaddr()
-    pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
-    pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
-    pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
-#undef ea
-    pram_ptr->fen_ibdcount = 0;
-    pram_ptr->fen_ibdstart = 0;
-    pram_ptr->fen_ibdend = 0;
-    pram_ptr->fen_txlen = 0;
-    pram_ptr->fen_iaddrh = 0;  /* disable hash */
-    pram_ptr->fen_iaddrl = 0;
-    pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */
-    /* pad pointer. use tiptr since we don't need a specific padding char */
-    pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
-    pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE;	/* maximum DMA1 length:1520 */
-    pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE;	/* maximum DMA2 length:1520 */
-
-#if defined(ET_DEBUG)
-    printf("parm_ptr(0xff788500) = %p\n",pram_ptr);
-    printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n",
-	pram_ptr->fen_genfcc.fcc_rbase);
-    printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n",
-	pram_ptr->fen_genfcc.fcc_tbase);
-#endif
-
-    /* 28.9 - (8)(9): clear out events in FCCE */
-    /* 28.9 - (9): FCCM: mask all events */
-    if(info->ether_index == 0) {
-	cpm->im_cpm_fcc1.fcce = ~0x0;
-	cpm->im_cpm_fcc1.fccm = 0;
-    } else if (info->ether_index == 1) {
-	cpm->im_cpm_fcc2.fcce = ~0x0;
-	cpm->im_cpm_fcc2.fccm = 0;
-    } else if (info->ether_index == 2) {
-	cpm->im_cpm_fcc3.fcce = ~0x0;
-	cpm->im_cpm_fcc3.fccm = 0;
-    }
-
-    /* 28.9 - (10-12): we don't use ethernet interrupts */
-
-    /* 28.9 - (13)
-     *
-     * Let's re-initialize the channel now.  We have to do it later
-     * than the manual describes because we have just now finished
-     * the BD initialization.
-     */
-    cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
-			    info->cpm_cr_enet_sblock,
-			    0x0c,
-			    CPM_CR_INIT_TRX) | CPM_CR_FLG;
-    do {
-	__asm__ __volatile__ ("eieio");
-    } while (cp->cpcr & CPM_CR_FLG);
-
-    /* 28.9 - (14): enable tx/rx in gfmr */
-    if(info->ether_index == 0) {
-	cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
-    } else if (info->ether_index == 1) {
-	cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
-    } else if (info->ether_index == 2) {
-	cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
-    }
-
-    return 1;
-}
-
-static void fec_halt(struct eth_device* dev)
-{
-    struct ether_fcc_info_s * info = dev->priv;
-    volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-
-    /* write GFMR: disable tx/rx */
-    if(info->ether_index == 0) {
-	cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
-    } else if(info->ether_index == 1) {
-	cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
-    } else if(info->ether_index == 2) {
-	cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
-    }
-}
-
-int fec_initialize(struct bd_info *bis)
-{
-	struct eth_device* dev;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
-	{
-		dev = (struct eth_device*) malloc(sizeof *dev);
-		memset(dev, 0, sizeof *dev);
-
-		sprintf(dev->name, "FCC%d",
-			ether_fcc_info[i].ether_index + 1);
-		dev->priv   = &ether_fcc_info[i];
-		dev->init   = fec_init;
-		dev->halt   = fec_halt;
-		dev->send   = fec_send;
-		dev->recv   = fec_recv;
-
-		eth_register(dev);
-
-#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
-		&& defined(CONFIG_BITBANGMII)
-		int retval;
-		struct mii_dev *mdiodev = mdio_alloc();
-		if (!mdiodev)
-			return -ENOMEM;
-		strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
-		mdiodev->read = bb_miiphy_read;
-		mdiodev->write = bb_miiphy_write;
-
-		retval = mdio_register(mdiodev);
-		if (retval < 0)
-			return retval;
-#endif
-	}
-
-	return 1;
-}
-
-#endif
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@ -351,10 +351,6 @@ int fixup_cpu(void)
 */
 int cpu_eth_init(struct bd_info *bis)
 {
-#if defined(CONFIG_ETHER_ON_FCC)
-	fec_initialize(bis);
-#endif
-
 #if defined(CONFIG_UEC_ETH)
 	uec_standard_init(bis);
 #endif
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@ -46,11 +46,7 @@
 #define MSR_RI		(1<<1)		/* Recoverable Exception */
 #define MSR_LE		(1<<0)		/* Little Endian */

-#ifdef CONFIG_APUS_FAST_EXCEPT
-#define MSR_		MSR_ME|MSR_IP|MSR_RI
-#else
 #define MSR_		MSR_ME|MSR_RI
-#endif
 #ifndef CONFIG_E500
 #define MSR_KERNEL	MSR_|MSR_IR|MSR_DR
 #else
--- a/board/Arcturus/ucp1020/spl.c
+++ b/board/Arcturus/ucp1020/spl.c
@ -106,7 +106,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	env_relocate();
 #endif

-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 	i2c_init_all();
 #else
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
--- a/board/bosch/guardian/board.c
+++ b/board/bosch/guardian/board.c
@ -142,7 +142,7 @@ void am33xx_spl_board_init(void)
 const struct dpll_params *get_dpll_ddr_params(void)
 {
 	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

 	return &dpll_ddr;
 }
--- a/board/bosch/shc/board.c
+++ b/board/bosch/shc/board.c
@ -51,16 +51,17 @@ static int shc_eeprom_valid;
 /*
 * Read header information from EEPROM into global structure.
 */
+#define EEPROM_ADDR	0x50
 static int read_eeprom(void)
 {
 	/* Check if baseboard eeprom is available */
-	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+	if (i2c_probe(EEPROM_ADDR)) {
 		puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
 		return -ENODEV;
 	}

 	/* read the eeprom using i2c */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
+	if (i2c_read(EEPROM_ADDR, 0, 2, (uchar *)&header,
 		     sizeof(header))) {
 		puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
 		return -EIO;
--- a/board/compulab/cm_t43/cm_t43.c
+++ b/board/compulab/cm_t43/cm_t43.c
@ -48,7 +48,7 @@ int board_init(void)
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 	gpmc_init();
 	set_i2c_pin_mux();
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 	i2c_probe(TPS65218_CHIP_PM);

 	return 0;
--- a/board/compulab/cm_t43/spl.c
+++ b/board/compulab/cm_t43/spl.c
@ -106,7 +106,7 @@ const struct dpll_params *get_dpll_per_params(void)
 void scale_vcores(void)
 {
 	set_i2c_pin_mux();
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 	if (i2c_probe(TPS65218_CHIP_PM))
 		return;

--- a/board/compulab/common/Makefile
+++ b/board/compulab/common/Makefile
@ -5,6 +5,6 @@
 # Author: Igor Grinberg <grinberg@compulab.co.il>

 obj-y				+= common.o
-obj-$(CONFIG_SYS_I2C_LEGACY)		+= eeprom.o
+obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY)	+= eeprom.o
 obj-$(CONFIG_LCD)		+= omap3_display.o
 obj-$(CONFIG_SMC911X)		+= omap3_smc911x.o
--- a/board/compulab/common/eeprom.c
+++ b/board/compulab/common/eeprom.c
@ -15,15 +15,6 @@
 #include <linux/kernel.h>
 #include "eeprom.h"

-#ifndef CONFIG_SYS_I2C_EEPROM_ADDR
-# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-#endif
-
-#ifndef CONFIG_SYS_I2C_EEPROM_BUS
-#define CONFIG_SYS_I2C_EEPROM_BUS	0
-#endif
-
 #define EEPROM_LAYOUT_VER_OFFSET	44
 #define BOARD_SERIAL_OFFSET		20
 #define BOARD_SERIAL_OFFSET_LEGACY	8
--- a/board/compulab/common/eeprom.h
+++ b/board/compulab/common/eeprom.h
@ -10,7 +10,7 @@
 #define _EEPROM_
 #include <errno.h>

-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus);
 u32 cl_eeprom_get_board_rev(uint eeprom_bus);
 int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus);
--- a/board/compulab/imx8mm-cl-iot-gate/spl.c
+++ b/board/compulab/imx8mm-cl-iot-gate/spl.c
@ -176,7 +176,7 @@ void board_init_f(ulong dummy)

 	enable_tzc380();

-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(1, 100000, 0x7f, &i2c_pad_info1);

 	power_init_board();

--- a/board/davinci/da8xxevm/Kconfig
+++ b/board/davinci/da8xxevm/Kconfig
@ -22,15 +22,6 @@ config MAC_ADDR_IN_SPIFLASH
 	  their MAC address in SPI Flash from the factory
 	  Enable this option to read the MAC from SPI Flash

-config MAC_ADDR_IN_EEPROM
-	bool "MAC address in EEPROM"
-	help
-	  The DA850 EVM comes with SoM are programmed with
-	  their MAC address in SPI Flash from the factory,
-	  but the kit has an optional expansion board with
-	  EEPROM available.  Enable this option to read the
-	  MAC from the EEPROM
-
 endif

 endif
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@ -129,19 +129,12 @@ int misc_init_r(void)
 {
 	dspwake();

-#if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM)
-
-	uchar env_enetaddr[6];
-	int enetaddr_found;
+#if defined(CONFIG_MAC_ADDR_IN_SPIFLASH)
+	uchar env_enetaddr[6], buff[6];
+	int enetaddr_found, spi_mac_read;

 	enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr);

-#endif
-
-#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
-	int spi_mac_read;
-	uchar buff[6];
-
 	spi_mac_read = get_mac_addr(buff);
 	buff[0] = 0;

@ -173,34 +166,6 @@ int misc_init_r(void)
 					"with the MAC address in the environment\n");
 		printf("Default using MAC address from environment\n");
 	}
-
-#elif defined(CONFIG_MAC_ADDR_IN_EEPROM)
-	uint8_t enetaddr[8];
-	int eeprom_mac_read;
-
-	/* Read Ethernet MAC address from EEPROM */
-	eeprom_mac_read = dvevm_read_mac_address(enetaddr);
-
-	/*
-	 * MAC address not present in the environment
-	 * try and read the MAC address from EEPROM flash
-	 * and set it.
-	 */
-	if (!enetaddr_found) {
-		if (eeprom_mac_read)
-			/* Set Ethernet MAC address from EEPROM */
-			davinci_sync_env_enetaddr(enetaddr);
-	} else {
-		/*
-		 * MAC address present in environment compare it with
-		 * the MAC address in EEPROM and warn on mismatch
-		 */
-		if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
-			printf("Warning: MAC address in EEPROM don't match "
-					"with the MAC address in the environment\n");
-		printf("Default using MAC address from environment\n");
-	}
-
 #endif
 	return 0;
 }
--- a/board/davinci/da8xxevm/omapl138_lcdk.c
+++ b/board/davinci/da8xxevm/omapl138_lcdk.c
@ -236,12 +236,6 @@ int board_init(void)

 #define CFG_MAC_ADDR_OFFSET	(flash->size - SZ_64K)

-static int  get_mac_addr(u8 *addr)
-{
-	/* Need to find a way to get MAC ADDRESS */
-	return 0;
-}
-
 void dsp_lpsc_on(unsigned domain, unsigned int id)
 {
 	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
@ -304,29 +298,6 @@ int rmii_hw_init(void)

 int misc_init_r(void)
 {
-	uint8_t tmp[20], addr[10];
-
-
-	if (env_get("ethaddr") == NULL) {
-		/* Read Ethernet MAC address from EEPROM */
-		if (dvevm_read_mac_address(addr)) {
-			/* Set Ethernet MAC address from EEPROM */
-			davinci_sync_env_enetaddr(addr);
-		} else {
-			get_mac_addr(addr);
-		}
-
-		if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) {
-			sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x",
-				addr[0], addr[1], addr[2], addr[3], addr[4],
-				addr[5]);
-
-			env_set("ethaddr", (char *)tmp);
-		} else {
-			printf("Invalid MAC address read.\n");
-		}
-	}
-
 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
 	/* Select RMII fucntion through the expander */
 	if (rmii_hw_init())
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@ -137,7 +137,7 @@ int board_early_init_f(void)
 	u8 uart;
 #endif

-#ifdef CONFIG_SYS_I2C_EARLY_INIT
+#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD)
 	i2c_early_init_f();
 #endif

--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@ -52,10 +52,6 @@ enum {
 #define CFG_UART_MUX_SHIFT	1
 #define CFG_LPUART_EN		0x1

-#ifdef CONFIG_SYS_I2C_EARLY_INIT
-void i2c_early_init_f(void);
-#endif
-
 #ifdef CONFIG_TFABOOT
 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
@ -447,7 +443,7 @@ int board_early_init_f(void)
 	 */
 	out_le32(cntcr, 0x1);

-#ifdef CONFIG_SYS_I2C_EARLY_INIT
+#if defined(CONFIG_SYS_I2C_EARLY_INIT)
 	i2c_early_init_f();
 #endif
 	fsl_lsch2_early_init_f();
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@ -37,10 +37,6 @@

 DECLARE_GLOBAL_DATA_PTR;

-#ifdef CONFIG_SYS_I2C_EARLY_INIT
-void i2c_early_init_f(void);
-#endif
-
 #ifdef CONFIG_TFABOOT
 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
@ -318,7 +314,7 @@ int board_early_init_f(void)
 	 */
 	out_le32(cntcr, 0x1);

-#ifdef CONFIG_SYS_I2C_EARLY_INIT
+#if defined(CONFIG_SYS_I2C_EARLY_INIT)
 	i2c_early_init_f();
 #endif
 	fsl_lsch2_early_init_f();
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@ -241,7 +241,7 @@ int board_init(void)

 int board_early_init_f(void)
 {
-#ifdef CONFIG_SYS_I2C_EARLY_INIT
+#if defined(CONFIG_SYS_I2C_EARLY_INIT)
 	i2c_early_init_f();
 #endif
 	fsl_lsch3_early_init_f();
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@ -314,7 +314,7 @@ int board_init(void)

 int board_early_init_f(void)
 {
-#ifdef CONFIG_SYS_I2C_EARLY_INIT
+#if defined(CONFIG_SYS_I2C_EARLY_INIT)
 	i2c_early_init_f();
 #endif
 	fsl_lsch3_early_init_f();
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@ -89,7 +89,7 @@ static void uart_get_clock(void)

 int board_early_init_f(void)
 {
-#ifdef CONFIG_SYS_I2C_EARLY_INIT
+#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD)
 	i2c_early_init_f();
 #endif
 	/* get required clock for UART IP */
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@ -50,8 +50,6 @@ int board_early_init_f (void)
 	return 0;
 }

-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-
 int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
--- a/board/freescale/mx6memcal/Kconfig
+++ b/board/freescale/mx6memcal/Kconfig
@ -87,12 +87,12 @@ choice
 	help
 	  Select the type of DDR (DDR3 or LPDDR2) used on your design

-config	DDR3
+config DDR3
 	bool "DDR3"
 	help
 	  Select this if your board design uses DDR3.

-config	LPDDR2
+config LPDDR2
 	bool "LPDDR2"
 	help
 	  Select this if your board design uses LPDDR2.
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@ -427,7 +427,7 @@ int checkboard(void)
 	dm_i2c_write(dev, 2, &val, 1);
 #else
 	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
-	i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 	val = 0x0;  /* no polarity inversion */
 	i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
 #endif
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@ -99,7 +99,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	env_relocate();
 #endif

-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 	i2c_init_all();
 #else
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
--- a/board/k+p/kp_imx53/kp_id_rev.c
+++ b/board/k+p/kp_imx53/kp_id_rev.c
@ -64,6 +64,10 @@ void show_eeprom(void)
 	eth_env_set_enetaddr("ethaddr", p);
 }

+#define I2C_EEPROM_BUS_NUM	1
+#define I2C_EEPROM_ADDR		0x50
+#define I2C_EEPROM_ADDR_LEN	2
+
 int read_eeprom(void)
 {
 	struct udevice *dev;
@ -72,9 +76,8 @@ int read_eeprom(void)
 	if (eeprom_has_been_read)
 		return 0;

-	ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
-				      CONFIG_SYS_I2C_EEPROM_ADDR,
-				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
+	ret = i2c_get_chip_for_busnum(I2C_EEPROM_BUS_NUM, I2C_EEPROM_ADDR,
+				      I2C_EEPROM_ADDR_LEN, &dev);
 	if (ret) {
 		printf("Cannot find EEPROM !\n");
 		return ret;
--- a/board/keymile/common/ivm.c
+++ b/board/keymile/common/ivm.c
@ -346,17 +346,17 @@ int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset)
 	struct udevice *eedev = NULL;

 	ret = i2c_get_chip_for_busnum(CONFIG_KM_IVM_BUS,
-				      CONFIG_SYS_I2C_EEPROM_ADDR, 1, &eedev);
+				      CONFIG_SYS_IVM_EEPROM_ADR, 1, &eedev);
 	if (ret) {
 		printf("failed to get device for EEPROM at address 0x%02x\n",
-		       CONFIG_SYS_I2C_EEPROM_ADDR);
+		       CONFIG_SYS_IVM_EEPROM_ADR);
 		return 1;
 	}

 	ret = dm_i2c_read(eedev, 0, buf, len);
 	if (ret != 0) {
 		printf("Error: Unable to read from I2C EEPROM at address %02X:%02X\n",
-		       CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		       CONFIG_SYS_IVM_EEPROM_ADR, 0);
 		return 1;
 	}
 #else
--- a/board/keymile/km83xx/km83xx_i2c.c
+++ b/board/keymile/km83xx/km83xx_i2c.c
@ -15,7 +15,7 @@ static void i2c_write_start_seq(void)
 {
 	struct fsl_i2c_base *base;
 	base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
-			CONFIG_SYS_I2C_OFFSET);
+			CONFIG_SYS_FSL_I2C_OFFSET);
 	udelay(DELAY_ABORT_SEQ);
 	out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
 	udelay(DELAY_ABORT_SEQ);
@ -26,7 +26,7 @@ int i2c_make_abort(void)
 {
 	struct fsl_i2c_base *base;
 	base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
-			CONFIG_SYS_I2C_OFFSET);
+			CONFIG_SYS_FSL_I2C_OFFSET);
 	uchar   last;
 	int     nbr_read = 0;
 	int     i = 0;
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;

 int board_early_init_f(void)
 {
-#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
 	/* DVFS for reset */
 	mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
 #endif
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;

 int board_early_init_f(void)
 {
-#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
 	/* DVFS for reset */
 	mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
 #endif
@ -75,7 +75,7 @@ int board_init(void)

 void reset_cpu(void)
 {
-#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
 	i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
 #else
 	/* only CA57 ? */
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;

 int board_early_init_f(void)
 {
-#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
 	/* DVFS for reset */
 	mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
 #endif
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@ -70,6 +70,7 @@ void sdram_init(void)
 #endif /* #ifdef CONFIG_SPL_BUILD */

 #ifndef CONFIG_SPL_BUILD
+#define FACTORYSET_EEPROM_ADDR		0x50
 /*
 * Basic board specific setup.  Pinmux has been handled already.
 */
@ -87,7 +88,7 @@ int board_init(void)
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

 #ifdef CONFIG_FACTORYSET
-	factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR);
+	factoryset_read_eeprom(FACTORYSET_EEPROM_ADDR);
 #endif

 	gpmc_init();
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@ -132,12 +132,16 @@ struct am335x_nand_geometry {
 	u8 nand_bus;
 };

+#define EEPROM_ADDR		0x50
+#define EEPROM_ADDR_DDR3	0x90
+#define EEPROM_ADDR_CHIP	0x120
+
 static int draco_read_nand_geometry(void)
 {
 	struct am335x_nand_geometry geo;

 	/* Read NAND geometry */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
+	if (i2c_read(EEPROM_ADDR, 0x80, 2,
 		     (uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
 		printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
 		return -EIO;
@ -160,20 +164,20 @@ static int draco_read_nand_geometry(void)
 static int read_eeprom(void)
 {
 	/* Check if baseboard eeprom is available */
-	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+	if (i2c_probe(EEPROM_ADDR)) {
 		printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
 		return 1;
 	}

 #ifdef CONFIG_SPL_BUILD
 	/* Read Siemens eeprom data (DDR3) */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
+	if (i2c_read(EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
 		     (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
 		printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
 		set_default_ddr3_timings();
 	}
 	/* Read Siemens eeprom data (CHIP) */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
+	if (i2c_read(EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
 		     (uchar *)&settings.chip, sizeof(settings.chip)))
 		printf("Could not read chip settings\n");

--- a/board/somlabs/visionsom-6ull/visionsom-6ull.c
+++ b/board/somlabs/visionsom-6ull/visionsom-6ull.c
@ -104,7 +104,7 @@ int board_init(void)
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 #endif

--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@ -47,7 +47,7 @@
 #include <sy8106a.h>
 #include <asm/setup.h>

-#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
+#if defined(CONFIG_VIDEO_LCD_PANEL_I2C)
 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
 int soft_i2c_gpio_sda;
 int soft_i2c_gpio_scl;
--- a/board/tcl/sl50/board.c
+++ b/board/tcl/sl50/board.c
@ -161,7 +161,7 @@ void am33xx_spl_board_init(void)
 const struct dpll_params *get_dpll_ddr_params(void)
 {
 	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

 	return &dpll_ddr_sl50;
 }
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@ -79,10 +79,6 @@ void do_board_detect(void)
 {
 	enable_i2c0_pin_mux();
 	enable_i2c2_pin_mux();
-#if !CONFIG_IS_ENABLED(DM_I2C)
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED2, CONFIG_SYS_OMAP24_I2C_SLAVE2);
-#endif
 	if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 				 CONFIG_EEPROM_CHIP_ADDRESS))
 		printf("ti_i2c_eeprom_init failed\n");
@ -339,13 +335,8 @@ static void scale_vcores_bone(int freq)
 	if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
 		return;

-#if !CONFIG_IS_ENABLED(DM_I2C)
-	if (i2c_probe(TPS65217_CHIP_PM))
-		return;
-#else
 	if (power_tps65217_init(0))
 		return;
-#endif


 	/*
@ -438,13 +429,8 @@ void scale_vcores_generic(int freq)
 	 * 1.10V.  For MPU voltage we need to switch based on
 	 * the frequency we are running at.
 	 */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-	if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
-		return;
-#else
 	if (power_tps65910_init(0))
 		return;
-#endif
 	/*
 	 * Depending on MPU clock and PG we will need a different
 	 * VDD to drive at that speed.
@ -472,10 +458,6 @@ void gpi2c_init(void)

 	if (first_time) {
 		enable_i2c0_pin_mux();
-#if !CONFIG_IS_ENABLED(DM_I2C)
-		i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
-			 CONFIG_SYS_OMAP24_I2C_SLAVE);
-#endif
 		first_time = false;
 	}
 }
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@ -345,14 +345,6 @@ void enable_i2c2_pin_mux(void)
 static unsigned short detect_daughter_board_profile(void)
 {
 	unsigned short val;
-
-#if !CONFIG_IS_ENABLED(DM_I2C)
-	if (i2c_probe(I2C_CPLD_ADDR))
-		return PROFILE_NONE;
-
-	if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
-		return PROFILE_NONE;
-#else
 	struct udevice *dev = NULL;
 	int rc;

@ -362,7 +354,6 @@ static unsigned short detect_daughter_board_profile(void)
 	rc = dm_i2c_read(dev, CFG_REG, (unsigned char *)(&val), 2);
 	if (rc)
 		return PROFILE_NONE;
-#endif
 	return (1 << (val & PROFILE_MASK));
 }

--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@ -393,13 +393,8 @@ void scale_vcores_generic(u32 m)
 {
 	int mpu_vdd, ddr_volt;

-#if !CONFIG_IS_ENABLED(DM_I2C)
-	if (i2c_probe(TPS65218_CHIP_PM))
-		return;
-#else
 	if (power_tps65218_init(0))
 		return;
-#endif

 	switch (m) {
 	case 1000:
@ -451,13 +446,8 @@ void scale_vcores_idk(u32 m)
 {
 	int mpu_vdd;

-#if !CONFIG_IS_ENABLED(DM_I2C)
-	if (i2c_probe(TPS62362_I2C_ADDR))
-		return;
-#else
 	if (power_tps62362_init(0))
 		return;
-#endif

 	switch (m) {
 	case 1000:
@ -492,10 +482,6 @@ void gpi2c_init(void)

 	if (first_time) {
 		enable_i2c0_pin_mux();
-#if !CONFIG_IS_ENABLED(DM_I2C)
-		i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
-			 CONFIG_SYS_OMAP24_I2C_SLAVE);
-#endif
 		first_time = false;
 	}
 }
@ -632,28 +618,15 @@ void sdram_init(void)
 int power_init_board(void)
 {
 	int rc;
-#if !CONFIG_IS_ENABLED(DM_I2C)
-	struct pmic *p = NULL;
-#endif
 	if (board_is_idk()) {
 		rc = power_tps62362_init(0);
 		if (rc)
 			goto done;
-#if !CONFIG_IS_ENABLED(DM_I2C)
-		p = pmic_get("TPS62362");
-		if (!p || pmic_probe(p))
-			goto done;
-#endif
 		puts("PMIC:  TPS62362\n");
 	} else {
 		rc = power_tps65218_init(0);
 		if (rc)
 			goto done;
-#if !CONFIG_IS_ENABLED(DM_I2C)
-		p = pmic_get("TPS65218_PMIC");
-		if (!p || pmic_probe(p))
-			goto done;
-#endif
 		puts("PMIC:  TPS65218\n");
 	}
 done:
--- a/board/tqc/tqma6/tqma6.c
+++ b/board/tqc/tqma6/tqma6.c
@ -171,7 +171,7 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
 #endif
 #endif

-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 static struct i2c_pads_info tqma6_i2c3_pads = {
 	/* I2C3: on board LM75, M24C64,  */
 	.scl = {
@ -216,7 +216,7 @@ int board_init(void)
 #ifndef CONFIG_DM_SPI
 	tqma6_iomuxc_spi();
 #endif
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 	tqma6_setup_i2c();
 #endif

--- a/board/varisys/common/Makefile
+++ b/board/varisys/common/Makefile
@ -1,21 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-# necessary to create built-in.o
-obj- := __dummy__.o
-else
-ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_ID_EEPROM)	+= sys_eeprom.o
-endif
-endif
--- a/board/varisys/common/eeprom.h
+++ b/board/varisys/common/eeprom.h
@ -1,6 +0,0 @@
-/* EEPROM init functions for Cyrus */
-
-
-void init_eeprom(int bus_num, int addr, int addr_len);
-void mac_read_from_fixed_id(void);
-int mac_read_from_eeprom_common(void);
--- a/board/varisys/common/sys_eeprom.c
+++ b/board/varisys/common/sys_eeprom.c
@ -1,500 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Based on board/freescale/common/sys_eeprom.c
- * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
- *
- * This defines the API for storing board information in the
- * eeprom. It has been adapted from an earlier version of the
- * Freescale API, but has a number of key differences. Because
- * the two APIs are independent and may diverge further, the
- * Varisys version of the API is implemented separately here.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <i2c.h>
-#include <linux/ctype.h>
-#include <linux/delay.h>
-#include <u-boot/crc.h>
-
-#include "eeprom.h"
-
-#ifdef CONFIG_SYS_I2C_EEPROM_NXID_MAC
-#define MAX_NUM_PORTS	CONFIG_SYS_I2C_EEPROM_NXID_MAC
-#else
-#define MAX_NUM_PORTS	8
-#endif
-#define NXID_VERSION	0
-
-/**
- * static eeprom: EEPROM layout for NXID formats
- *
- * See Freescale application note AN3638 for details.
- */
-static struct __attribute__ ((__packed__)) eeprom {
-	u8 id[4];         /* 0x00 - 0x03 EEPROM Tag 'NXID' */
-	u8 sn[12];        /* 0x04 - 0x0F Serial Number */
-	u8 errata[5];     /* 0x10 - 0x14 Errata Level */
-	u8 date[6];       /* 0x15 - 0x1a Build Date */
-	u8 res_0;         /* 0x1b        Reserved */
-	u32 version;      /* 0x1c - 0x1f NXID Version */
-	u8 tempcal[8];    /* 0x20 - 0x27 Temperature Calibration Factors */
-	u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */
-	u8 tempcalflags;  /* 0x2a        Temperature Calibration Flags */
-	u8 res_1[21];     /* 0x2b - 0x3f Reserved */
-	u8 mac_count;     /* 0x40        Number of MAC addresses */
-	u8 mac_flag;      /* 0x41        MAC table flags */
-	u8 mac[MAX_NUM_PORTS][6];     /* 0x42 - x MAC addresses */
-	u32 crc;          /* x+1         CRC32 checksum */
-} e;
-
-/* Set to 1 if we've read EEPROM into memory */
-static int has_been_read;
-
-/* Is this a valid NXID EEPROM? */
-#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \
-		  (e.id[2] == 'I') || (e.id[3] == 'D'))
-
-/** Fixed ID field in EEPROM */
-static unsigned char uid[16];
-
-static int eeprom_bus_num = -1;
-static int eeprom_addr;
-static int eeprom_addr_len;
-
-/**
- * This must be called before any eeprom access.
- */
-void init_eeprom(int bus_num, int addr, int addr_len)
-{
-	eeprom_bus_num = bus_num;
-	eeprom_addr = addr;
-	eeprom_addr_len = addr_len;
-}
-
-/**
- * show_eeprom - display the contents of the EEPROM
- */
-void show_eeprom(void)
-{
-	int i;
-	unsigned int crc;
-
-	/* EEPROM tag ID, either CCID or NXID */
-	printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
-		be32_to_cpu(e.version));
-
-	/* Serial number */
-	printf("SN: %s\n", e.sn);
-
-	printf("UID: ");
-	for (i = 0; i < 16; i++)
-		printf("%02x", uid[i]);
-	printf("\n");
-
-	/* Errata level. */
-	printf("Errata: %s\n", e.errata);
-
-	/* Build date, BCD date values, as YYMMDDhhmmss */
-	printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
-		e.date[0], e.date[1], e.date[2],
-		e.date[3] & 0x7F, e.date[4], e.date[5],
-		e.date[3] & 0x80 ? "PM" : "");
-
-	/* Show MAC addresses  */
-	for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
-		u8 *p = e.mac[i];
-
-		printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i,
-		       p[0], p[1], p[2], p[3], p[4], p[5]);
-	}
-
-	crc = crc32(0, (void *)&e, sizeof(e) - 4);
-
-	if (crc == be32_to_cpu(e.crc))
-		printf("CRC: %08x\n", be32_to_cpu(e.crc));
-	else
-		printf("CRC: %08x (should be %08x)\n",
-		       be32_to_cpu(e.crc), crc);
-
-#ifdef DEBUG
-	printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
-	for (i = 0; i < sizeof(e); i++) {
-		if ((i % 16) == 0)
-			printf("%02X: ", i);
-		printf("%02X ", ((u8 *)&e)[i]);
-		if (((i % 16) == 15) || (i == sizeof(e) - 1))
-			printf("\n");
-	}
-#endif
-}
-
-/**
- * read_eeprom - read the EEPROM into memory
- */
-int read_eeprom(void)
-{
-	int ret;
-	unsigned int bus;
-
-	if (eeprom_bus_num < 0) {
-		printf("EEPROM not configured\n");
-		return -1;
-	}
-
-	if (has_been_read)
-		return 0;
-
-	bus = i2c_get_bus_num();
-	i2c_set_bus_num(eeprom_bus_num);
-
-	ret = i2c_read(eeprom_addr, 0, eeprom_addr_len,
-		(void *)&e, sizeof(e));
-
-
-	/* Fixed address of ID field */
-	i2c_read(0x5f, 0x80, 1, uid, 16);
-
-	i2c_set_bus_num(bus);
-
-#ifdef DEBUG
-	show_eeprom();
-#endif
-
-	has_been_read = (ret == 0) ? 1 : 0;
-
-	return ret;
-}
-
-/**
- *  update_crc - update the CRC
- *
- *  This function should be called after each update to the EEPROM structure,
- *  to make sure the CRC is always correct.
- */
-static void update_crc(void)
-{
-	u32 crc, crc_offset = offsetof(struct eeprom, crc);
-
-	crc = crc32(0, (void *)&e, crc_offset);
-	e.crc = cpu_to_be32(crc);
-}
-
-/**
- * prog_eeprom - write the EEPROM from memory
- */
-static int prog_eeprom(void)
-{
-	int ret = 0;
-	int i;
-	void *p;
-	unsigned int bus;
-
-	if (eeprom_bus_num < 0) {
-		printf("EEPROM not configured\n");
-		return -1;
-	}
-
-	/* Set the reserved values to 0xFF   */
-	e.res_0 = 0xFF;
-	memset(e.res_1, 0xFF, sizeof(e.res_1));
-	update_crc();
-
-	bus = i2c_get_bus_num();
-	i2c_set_bus_num(eeprom_bus_num);
-
-	/*
-	 * The AT24C02 datasheet says that data can only be written in page
-	 * mode, which means 8 bytes at a time, and it takes up to 5ms to
-	 * complete a given write.
-	 */
-	for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
-		ret = i2c_write(eeprom_addr, i, eeprom_addr_len,
-			p, min((int)(sizeof(e) - i), 8));
-		if (ret)
-			break;
-		udelay(5000);	/* 5ms write cycle timing */
-	}
-
-	if (!ret) {
-		/* Verify the write by reading back the EEPROM and comparing */
-		struct eeprom e2;
-
-		ret = i2c_read(eeprom_addr, 0,
-			eeprom_addr_len, (void *)&e2, sizeof(e2));
-		if (!ret && memcmp(&e, &e2, sizeof(e)))
-			ret = -1;
-	}
-
-	i2c_set_bus_num(bus);
-
-	if (ret) {
-		printf("Programming failed.\n");
-		has_been_read = 0;
-		return -1;
-	}
-
-	printf("Programming passed.\n");
-	return 0;
-}
-
-/**
- * h2i - converts hex character into a number
- *
- * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
- * the integer equivalent.
- */
-static inline u8 h2i(char p)
-{
-	if ((p >= '0') && (p <= '9'))
-		return p - '0';
-
-	if ((p >= 'A') && (p <= 'F'))
-		return (p - 'A') + 10;
-
-	if ((p >= 'a') && (p <= 'f'))
-		return (p - 'a') + 10;
-
-	return 0;
-}
-
-/**
- * set_date - stores the build date into the EEPROM
- *
- * This function takes a pointer to a string in the format "YYMMDDhhmmss"
- * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
- * and stores it in the build date field of the EEPROM local copy.
- */
-static void set_date(const char *string)
-{
-	unsigned int i;
-
-	if (strlen(string) != 12) {
-		printf("Usage: mac date YYMMDDhhmmss\n");
-		return;
-	}
-
-	for (i = 0; i < 6; i++)
-		e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
-
-	update_crc();
-}
-
-/**
- * set_mac_address - stores a MAC address into the EEPROM
- *
- * This function takes a pointer to MAC address string
- * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
- * stores it in one of the MAC address fields of the EEPROM local copy.
- */
-static void set_mac_address(unsigned int index, const char *string)
-{
-	char *p = (char *)string;
-	unsigned int i;
-
-	if ((index >= MAX_NUM_PORTS) || !string) {
-		printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n");
-		return;
-	}
-
-	for (i = 0; *p && (i < 6); i++) {
-		e.mac[index][i] = hextoul(p, &p);
-		if (*p == ':')
-			p++;
-	}
-
-	update_crc();
-}
-
-int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
-	char cmd;
-
-	if (argc == 1) {
-		show_eeprom();
-		return 0;
-	}
-
-	cmd = argv[1][0];
-
-	if (cmd == 'r') {
-		read_eeprom();
-		return 0;
-	}
-
-	if (cmd == 'i') {
-		memcpy(e.id, "NXID", sizeof(e.id));
-		e.version = NXID_VERSION;
-		update_crc();
-		return 0;
-	}
-
-	if (!is_valid) {
-		printf("Please read the EEPROM ('r') and/or set the ID ('i') first.\n");
-		return 0;
-	}
-
-	if (argc == 2) {
-		switch (cmd) {
-		case 's':	/* save */
-			prog_eeprom();
-			break;
-		default:
-			return cmd_usage(cmdtp);
-		}
-
-		return 0;
-	}
-
-	/* We know we have at least one parameter  */
-
-	switch (cmd) {
-	case 'n':	/* serial number */
-		memset(e.sn, 0, sizeof(e.sn));
-		strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
-		update_crc();
-		break;
-	case 'e':	/* errata */
-		memset(e.errata, 0, 5);
-		strncpy((char *)e.errata, argv[2], 4);
-		update_crc();
-		break;
-	case 'd':	/* date BCD format YYMMDDhhmmss */
-		set_date(argv[2]);
-		break;
-	case 'p':	/* MAC table size */
-		e.mac_count = hextoul(argv[2], NULL);
-		update_crc();
-		break;
-	case '0' ... '9':	/* "mac 0" through "mac 22" */
-		set_mac_address(dectoul(argv[1], NULL), argv[2]);
-		break;
-	case 'h':	/* help */
-	default:
-		return cmd_usage(cmdtp);
-	}
-
-	return 0;
-}
-
-int mac_read_from_generic_eeprom(const char *envvar, int chip,
-	int address, int mac_bus)
-{
-	int ret;
-	unsigned int bus;
-	unsigned char mac[6];
-	char ethaddr[18];
-
-	bus = i2c_get_bus_num();
-	i2c_set_bus_num(mac_bus);
-
-	ret = i2c_read(chip, address, 1, mac, 6);
-
-	i2c_set_bus_num(bus);
-
-	if (!ret) {
-		sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
-			mac[0],
-			mac[1],
-			mac[2],
-			mac[3],
-			mac[4],
-			mac[5]);
-
-		printf("MAC: %s\n", ethaddr);
-		env_set(envvar, ethaddr);
-	}
-
-	return ret;
-}
-
-void mac_read_from_fixed_id(void)
-{
-#ifdef CONFIG_SYS_I2C_MAC1_CHIP_ADDR
-	mac_read_from_generic_eeprom("ethaddr", CONFIG_SYS_I2C_MAC1_CHIP_ADDR,
-		CONFIG_SYS_I2C_MAC1_DATA_ADDR, CONFIG_SYS_I2C_MAC1_BUS);
-#endif
-#ifdef CONFIG_SYS_I2C_MAC2_CHIP_ADDR
-	mac_read_from_generic_eeprom("eth1addr", CONFIG_SYS_I2C_MAC2_CHIP_ADDR,
-		CONFIG_SYS_I2C_MAC2_DATA_ADDR, CONFIG_SYS_I2C_MAC2_BUS);
-#endif
-}
-
-/**
- * mac_read_from_eeprom - read the MAC addresses from EEPROM
- *
- * This function reads the MAC addresses from EEPROM and sets the
- * appropriate environment variables for each one read.
- *
- * The environment variables are only set if they haven't been set already.
- * This ensures that any user-saved variables are never overwritten.
- *
- * This function must be called after relocation.
- *
- * For NXID v1 EEPROMs, we support loading and up-converting the older NXID v0
- * format.  In a v0 EEPROM, there are only eight MAC addresses and the CRC is
- * located at a different offset.
- */
-int mac_read_from_eeprom_common(void)
-{
-	unsigned int i;
-	u32 crc, crc_offset = offsetof(struct eeprom, crc);
-	u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
-
-	puts("EEPROM: ");
-
-	if (read_eeprom()) {
-		printf("Read failed.\n");
-		return 0;
-	}
-
-	if (!is_valid) {
-		printf("Invalid ID (%02x %02x %02x %02x)\n",
-		       e.id[0], e.id[1], e.id[2], e.id[3]);
-		return 0;
-	}
-
-	crc = crc32(0, (void *)&e, crc_offset);
-	crcp = (void *)&e + crc_offset;
-	if (crc != be32_to_cpu(*crcp)) {
-		printf("CRC mismatch (%08x != %08x)\n", crc,
-			be32_to_cpu(e.crc));
-		return 0;
-	}
-
-	/*
-	 * MAC address #9 in v1 occupies the same position as the CRC in v0.
-	 * Erase it so that it's not mistaken for a MAC address.  We'll
-	 * update the CRC later.
-	 */
-	if (e.version == 0)
-		memset(e.mac[8], 0xff, 6);
-
-	for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
-		if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) &&
-		    memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
-			char ethaddr[18];
-			char enetvar[9];
-
-			sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
-				e.mac[i][0],
-				e.mac[i][1],
-				e.mac[i][2],
-				e.mac[i][3],
-				e.mac[i][4],
-				e.mac[i][5]);
-			sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i);
-			/* Only initialize environment variables that are blank
-			 * (i.e. have not yet been set)
-			 */
-			if (!env_get(enetvar))
-				env_set(enetvar, ethaddr);
-		}
-	}
-
-	printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
-		be32_to_cpu(e.version));
-
-	return 0;
-}
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c
@ -187,7 +187,7 @@ void am33xx_spl_board_init(void)
 	 */
 	i2c_set_bus_num(1);

-	printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
+	printf("I2C speed: %d Hz\n", CONFIG_SYS_I2C_SPEED);

 	if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
 		puts("i2c: cannot access TPS65910\n");
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@ -614,6 +614,37 @@ config EEPROM_LAYOUT_HELP_STRING
 	    Help printed with the LAYOUT VERSIONS part of the 'eeprom'
 	    command's help.

+config SYS_I2C_EEPROM_BUS
+	int "I2C bus of the EEPROM device."
+	depends on CMD_EEPROM
+	default 0
+
+config SYS_I2C_EEPROM_ADDR_LEN
+	int "Length in bytes of the EEPROM memory array address"
+	depends on CMD_EEPROM || ID_EEPROM
+	default 1
+	range 1 2
+	help
+	  Note: This is NOT the chip address length!
+
+config SYS_EEPROM_SIZE
+	depends on CMD_EEPROM
+	int "Size in bytes of the EEPROM device"
+	default 256
+
+config SYS_EEPROM_PAGE_WRITE_BITS
+	int "Number of bits used to address bytes in a single page"
+	depends on CMD_EEPROM
+	default 8
+	help
+	  The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
+	  A 64 byte page, for example would require six bits.
+
+config SYS_EEPROM_PAGE_WRITE_DELAY_MS
+	int "Number of milliseconds to delay between page writes"
+	depends on CMD_EEPROM || CMD_I2C
+	default 0
+
 config LOOPW
 	bool "loopw"
 	help
--- a/cmd/date.c
+++ b/cmd/date.c
@ -49,7 +49,7 @@ static int do_date(struct cmd_tbl *cmdtp, int flag, int argc,
 			return CMD_RET_FAILURE;
 		}
 	}
-#elif defined(CONFIG_SYS_I2C_LEGACY)
+#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 	old_bus = i2c_get_bus_num();
 	i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
 #else
@ -122,7 +122,7 @@ static int do_date(struct cmd_tbl *cmdtp, int flag, int argc,
 	}

 	/* switch back to original I2C bus */
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 	i2c_set_bus_num(old_bus);
 #elif !defined(CONFIG_DM_RTC)
 	I2C_SET_BUS(old_bus);
--- a/cmd/eeprom.c
+++ b/cmd/eeprom.c
@ -15,7 +15,7 @@
 * degradation (typical for EEPROM) is incured for FRAM memory:
 *
 * #define CONFIG_SYS_I2C_FRAM
- * #undef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
+ * Set CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS to 0
 *
 */

@ -27,18 +27,6 @@
 #include <eeprom_layout.h>
 #include <linux/delay.h>

-#ifndef	CONFIG_SYS_I2C_SPEED
-#define	CONFIG_SYS_I2C_SPEED	50000
-#endif
-
-#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	0
-#endif
-
-#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_BITS
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	8
-#endif
-
 #ifndef	I2C_RXTX_LEN
 #define I2C_RXTX_LEN	128
 #endif
@ -46,21 +34,6 @@
 #define	EEPROM_PAGE_SIZE	(1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
 #define	EEPROM_PAGE_OFFSET(x)	((x) & (EEPROM_PAGE_SIZE - 1))

-/*
- * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
- *   0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
- *
- * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
- *   0x00000nxx for EEPROM address selectors and page number at n.
- */
-#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
-#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || \
-	(CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1) || \
-	(CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2)
-#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2
-#endif
-#endif
-
 #if CONFIG_IS_ENABLED(DM_I2C)
 static int eeprom_i2c_bus;
 #endif
@ -75,13 +48,20 @@ void eeprom_init(int bus)
 	/* I2C EEPROM */
 #if CONFIG_IS_ENABLED(DM_I2C)
 	eeprom_i2c_bus = bus;
-#elif defined(CONFIG_SYS_I2C_LEGACY)
+#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 	if (bus >= 0)
 		i2c_set_bus_num(bus);
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 }

+/*
+ * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
+ *   0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
+ *
+ * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
+ *   0x00000nxx for EEPROM address selectors and page number at n.
+ */
 static int eeprom_addr(unsigned dev_addr, unsigned offset, uchar *addr)
 {
 	unsigned blk_off;
@ -183,8 +163,10 @@ static int eeprom_rw(unsigned dev_addr, unsigned offset, uchar *buffer,
 		buffer += len;
 		offset += len;

+#if CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS > 0
 		if (!read)
 			udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
 	}

 	return rcode;
@ -243,10 +225,10 @@ static int parse_i2c_bus_addr(int *i2c_bus, ulong *i2c_addr, int argc,
 	int argc_no_bus = argc_no_bus_addr + 1;
 	int argc_bus_addr = argc_no_bus_addr + 2;

-#ifdef CONFIG_SYS_DEF_EEPROM_ADDR
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
 	if (argc == argc_no_bus_addr) {
 		*i2c_bus = -1;
-		*i2c_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
+		*i2c_addr = CONFIG_SYS_I2C_EEPROM_ADDR;

 		return 0;
 	}
--- a/cmd/i2c.c
+++ b/cmd/i2c.c
@ -98,7 +98,7 @@ static uint	i2c_mm_last_alen;
 * pairs.  The following macros take care of this */

 #if defined(CONFIG_SYS_I2C_NOPROBES)
-#if defined(CONFIG_SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS)
 static struct
 {
 	uchar	bus;
@ -114,7 +114,7 @@ static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
 #define COMPARE_BUS(b,i)	((b) == 0)	/* Make compiler happy */
 #define COMPARE_ADDR(a,i)	(i2c_no_probes[(i)] == (a))
 #define NO_PROBE_ADDR(i)	i2c_no_probes[(i)]
-#endif	/* defined(CONFIG_SYS_I2C_LEGACY) */
+#endif	/* CONFIG_IS_ENABLED(SYS_I2C_LEGACY) */
 #endif

 #define DISP_LINE_LEN	16
@ -195,54 +195,6 @@ void i2c_init_board(void)
 {
 }

-/* TODO: Implement architecture-specific get/set functions */
-
-/**
- * i2c_get_bus_speed() - Return I2C bus speed
- *
- * This function is the default implementation of function for retrieveing
- * the current I2C bus speed in Hz.
- *
- * A driver implementing runtime switching of I2C bus speed must override
- * this function to report the speed correctly. Simple or legacy drivers
- * can use this fallback.
- *
- * Returns I2C bus speed in Hz.
- */
-#if !defined(CONFIG_SYS_I2C_LEGACY) && !CONFIG_IS_ENABLED(DM_I2C)
-/*
- * TODO: Implement architecture-specific get/set functions
- * Should go away, if we switched completely to new multibus support
- */
-__weak
-unsigned int i2c_get_bus_speed(void)
-{
-	return CONFIG_SYS_I2C_SPEED;
-}
-
-/**
- * i2c_set_bus_speed() - Configure I2C bus speed
- * @speed:	Newly set speed of the I2C bus in Hz
- *
- * This function is the default implementation of function for setting
- * the I2C bus speed in Hz.
- *
- * A driver implementing runtime switching of I2C bus speed must override
- * this function to report the speed correctly. Simple or legacy drivers
- * can use this fallback.
- *
- * Returns zero on success, negative value on error.
- */
-__weak
-int i2c_set_bus_speed(unsigned int speed)
-{
-	if (speed != CONFIG_SYS_I2C_SPEED)
-		return -1;
-
-	return 0;
-}
-#endif
-
 /**
 * get_alen() - Small parser helper function to get address length
 *
@ -922,7 +874,7 @@ static int mod_i2c_mem(struct cmd_tbl *cmdtp, int incrflag, int flag, int argc,
 				if (ret)
 					return i2c_report_err(ret,
 							      I2C_ERR_WRITE);
-#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
+#if CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS > 0
 				udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 #endif
 				if (incrflag)
@ -1725,7 +1677,7 @@ static void show_bus(struct udevice *bus)
 *
 * Returns zero always.
 */
-#if defined(CONFIG_SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
 static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc,
 			   char *const argv[])
 {
@ -1811,7 +1763,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc,
 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
 * on error.
 */
-#if defined(CONFIG_SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) || \
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) || \
 		CONFIG_IS_ENABLED(DM_I2C)
 static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc,
 			  char *const argv[])
@ -1834,7 +1786,7 @@ static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc,
 		printf("Current bus is %d\n", bus_no);
 	} else {
 		bus_no = dectoul(argv[1], NULL);
-#if defined(CONFIG_SYS_I2C_LEGACY)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 		if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) {
 			printf("Invalid bus %d\n", bus_no);
 			return -1;
@ -1852,7 +1804,7 @@ static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc,

 	return ret ? CMD_RET_FAILURE : 0;
 }
-#endif  /* defined(CONFIG_SYS_I2C_LEGACY) */
+#endif  /* CONFIG_IS_ENABLED(SYS_I2C_LEGACY) */

 /**
 * do_i2c_bus_speed() - Handle the "i2c speed" command-line command
@ -1951,20 +1903,18 @@ static int do_i2c_reset(struct cmd_tbl *cmdtp, int flag, int argc,
 		printf("Error: Not supported by the driver\n");
 		return CMD_RET_FAILURE;
 	}
-#elif defined(CONFIG_SYS_I2C_LEGACY)
+#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 	i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr);
-#else
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 	return 0;
 }

 static struct cmd_tbl cmd_i2c_sub[] = {
-#if defined(CONFIG_SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
 	U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""),
 #endif
 	U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
-#if defined(CONFIG_SYS_I2C_LEGACY) || \
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || \
 	defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C)
 	U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
 #endif  /* CONFIG_I2C_MULTI_BUS */
@ -2036,12 +1986,12 @@ static int do_i2c(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 /***************************************************/
 #ifdef CONFIG_SYS_LONGHELP
 static char i2c_help_text[] =
-#if defined(CONFIG_SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
 	"bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n"
 	"i2c " /* That's the prefix for the crc32 command below. */
 #endif
 	"crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
-#if defined(CONFIG_SYS_I2C_LEGACY) || \
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || \
 	defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C)
 	"i2c dev [dev] - show or set current I2C bus\n"
 #endif  /* CONFIG_I2C_MULTI_BUS */
--- a/common/Kconfig
+++ b/common/Kconfig
@ -548,6 +548,12 @@ config MISC_INIT_R
 	help
 	  Enabling this option calls 'misc_init_r' function

+config ID_EEPROM
+	bool "Enable I2C connected system identifier EEPROM"
+	help
+	  A number of different systems and vendors enable a vendor-specified
+	  EEPROM that contains various identifying features.
+
 config PCI_INIT_R
 	bool "Enumerate PCI buses during init"
 	depends on PCI
--- a/common/board_f.c
+++ b/common/board_f.c
@ -244,7 +244,7 @@ __weak int dram_init_banksize(void)
 	return 0;
 }

-#if defined(CONFIG_SYS_I2C_LEGACY)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 static int init_func_i2c(void)
 {
 	puts("I2C:   ");
@ -871,7 +871,7 @@ static const init_fnc_t init_sequence_f[] = {
 	misc_init_f,
 #endif
 	INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_SYS_I2C_LEGACY)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 	init_func_i2c,
 #endif
 #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
--- a/common/board_r.c
+++ b/common/board_r.c
@ -720,7 +720,7 @@ static init_fnc_t init_sequence_r[] = {
 #endif
 	INIT_FUNC_WATCHDOG_RESET
 	cpu_secondary_init_r,
-#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
+#if defined(CONFIG_ID_EEPROM)
 	mac_read_from_eeprom,
 #endif
 	INIT_FUNC_WATCHDOG_RESET
--- a/common/stdio.c
+++ b/common/stdio.c
@ -336,7 +336,7 @@ int stdio_add_devices(void)
 				       dev->name);
 		}
 	}
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 	i2c_init_all();
 #endif
 	if (IS_ENABLED(CONFIG_DM_VIDEO)) {
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@ -13,6 +13,9 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
 CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_MII=y
 CONFIG_SUN4I_EMAC=y
 CONFIG_AXP_ALDO3_VOLT=2800
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@ -10,6 +10,9 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=1
 CONFIG_USB1_VBUS_PIN="PB10"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_MII=y
 CONFIG_SUN4I_EMAC=y
 CONFIG_AXP152_POWER=y
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@ -13,6 +13,9 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
 CONFIG_VIDEO_LCD_POWER="PB10"
 CONFIG_VIDEO_LCD_BL_PWM="PB2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_CONS_INDEX=2
 CONFIG_USB_EHCI_HCD=y
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@ -20,6 +20,9 @@ CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_CONS_INDEX=2
 CONFIG_USB_EHCI_HCD=y
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@ -19,6 +19,9 @@ CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SCSI_AHCI=y
 CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_PHY_REALTEK=y
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@ -17,6 +17,9 @@ CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SCSI_AHCI=y
 CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_PHY_REALTEK=y
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@ -11,6 +11,9 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
 CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
--- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
+++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
@ -13,6 +13,9 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
 CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@ -14,6 +14,9 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
 CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@ -15,6 +15,9 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
 CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_PHY_REALTEK=y
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
--- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
@ -16,6 +16,9 @@ CONFIG_AHCI=y
 CONFIG_SPL_I2C=y
 CONFIG_SCSI_AHCI=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_PHY_ADDR=3
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
--- a/configs/A20-Olimex-SOM204-EVB_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB_defconfig
@ -15,6 +15,9 @@ CONFIG_AHCI=y
 CONFIG_SPL_I2C=y
 CONFIG_SCSI_AHCI=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_PHY_ADDR=3
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@ -15,4 +15,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7"
 CONFIG_VIDEO_LCD_BL_PWM="PB2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_USB_MUSB_HOST=y
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@ -16,5 +16,8 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
 CONFIG_VIDEO_LCD_BL_PWM="PB2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_CONS_INDEX=2
 CONFIG_USB_MUSB_HOST=y
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@ -9,6 +9,9 @@ CONFIG_USB1_VBUS_PIN="PB10"
 CONFIG_VIDEO_COMPOSITE=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_AXP152_POWER=y
 CONFIG_CONS_INDEX=2
 CONFIG_USB_EHCI_HCD=y
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@ -7,6 +7,9 @@ CONFIG_DRAM_CLK=432
 CONFIG_USB1_VBUS_PIN="PG13"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_AXP152_POWER=y
 CONFIG_CONS_INDEX=2
 CONFIG_USB_EHCI_HCD=y
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@ -13,6 +13,10 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
 CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_RGMII=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_AXP_DLDO4_VOLT=2500
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@ -12,6 +12,9 @@ CONFIG_AHCI=y
 CONFIG_SPL_I2C=y
 CONFIG_NETCONSOLE=y
 CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@ -14,6 +14,9 @@ CONFIG_AHCI=y
 CONFIG_SPL_I2C=y
 CONFIG_NETCONSOLE=y
 CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@ -10,6 +10,9 @@ CONFIG_CHIP_DIP_SCAN=y
 CONFIG_SPL_I2C=y
 CONFIG_CMD_DFU=y
 CONFIG_DFU_RAM=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
 # CONFIG_MMC is not set
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
--- a/Show More
+++ b/Show More