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ARM: dts: renesas: Add R8A77980 V3H DTs and headers

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Import R8A77980 V3H DTs and headers from Linux 5.2.7 , commit 5697a9d3d55f.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut 2019-07-29 19:59:44 +02:00 committed by Marek Vasut
parent ca6da6dd93
commit a811e19b91
4 changed files with 1723 additions and 0 deletions
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24
arch/arm/dts/r8a77980-u-boot.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RCar R8A77980 SoC
*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
#include "r8a779x-u-boot.dtsi"
&extalr_clk {
u-boot,dm-pre-reloc;
};
/ {
soc {
rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r8a77980", "renesas,rpc";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
};
};

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arch/arm/dts/r8a77980.dtsi Normal file
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51
include/dt-bindings/clock/r8a77980-cpg-mssr.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a77980 CPG Core Clocks */
#define R8A77980_CLK_Z2 0
#define R8A77980_CLK_ZR 1
#define R8A77980_CLK_ZTR 2
#define R8A77980_CLK_ZTRD2 3
#define R8A77980_CLK_ZT 4
#define R8A77980_CLK_ZX 5
#define R8A77980_CLK_S0D1 6
#define R8A77980_CLK_S0D2 7
#define R8A77980_CLK_S0D3 8
#define R8A77980_CLK_S0D4 9
#define R8A77980_CLK_S0D6 10
#define R8A77980_CLK_S0D12 11
#define R8A77980_CLK_S0D24 12
#define R8A77980_CLK_S1D1 13
#define R8A77980_CLK_S1D2 14
#define R8A77980_CLK_S1D4 15
#define R8A77980_CLK_S2D1 16
#define R8A77980_CLK_S2D2 17
#define R8A77980_CLK_S2D4 18
#define R8A77980_CLK_S3D1 19
#define R8A77980_CLK_S3D2 20
#define R8A77980_CLK_S3D4 21
#define R8A77980_CLK_LB 22
#define R8A77980_CLK_CL 23
#define R8A77980_CLK_ZB3 24
#define R8A77980_CLK_ZB3D2 25
#define R8A77980_CLK_ZB3D4 26
#define R8A77980_CLK_SD0H 27
#define R8A77980_CLK_SD0 28
#define R8A77980_CLK_RPC 29
#define R8A77980_CLK_RPCD2 30
#define R8A77980_CLK_MSO 31
#define R8A77980_CLK_CANFD 32
#define R8A77980_CLK_CSI0 33
#define R8A77980_CLK_CP 34
#define R8A77980_CLK_CPEX 35
#define R8A77980_CLK_R 36
#define R8A77980_CLK_OSC 37
#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */

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include/dt-bindings/power/r8a77980-sysc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__
#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A77980_PD_A2SC2 0
#define R8A77980_PD_A2SC3 1
#define R8A77980_PD_A2SC4 2
#define R8A77980_PD_A2DP0 3
#define R8A77980_PD_A2DP1 4
#define R8A77980_PD_CA53_CPU0 5
#define R8A77980_PD_CA53_CPU1 6
#define R8A77980_PD_CA53_CPU2 7
#define R8A77980_PD_CA53_CPU3 8
#define R8A77980_PD_A2CN 10
#define R8A77980_PD_A3VIP0 11
#define R8A77980_PD_A2IR5 12
#define R8A77980_PD_CR7 13
#define R8A77980_PD_A2IR4 15
#define R8A77980_PD_CA53_SCU 21
#define R8A77980_PD_A2IR0 23
#define R8A77980_PD_A3IR 24
#define R8A77980_PD_A3VIP1 25
#define R8A77980_PD_A3VIP2 26
#define R8A77980_PD_A2IR1 27
#define R8A77980_PD_A2IR2 28
#define R8A77980_PD_A2IR3 29
#define R8A77980_PD_A2SC0 30
#define R8A77980_PD_A2SC1 31
/* Always-on power area */
#define R8A77980_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */