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clk: aspeed: Get HCLK frequency support

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User can get correct HCLK frequency during driver probe stage
by adding the following configuration in the device tree.
"clocks = <&scu ASPEED_CLK_AHB>".

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Chin-Ting Kuo 2022-08-19 17:01:02 +08:00 committed by Tom Rini
parent b3d9c0b6d5
commit a7e8220474
1 changed files with 23 additions and 0 deletions
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23
drivers/clk/aspeed/clk_ast2500.c
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@ -30,6 +30,12 @@
#define D2PLL_DEFAULT_RATE (250 * 1000 * 1000)
/*
* AXI/AHB clock selection, taken from Aspeed SDK
*/
#define SCU_HWSTRAP_AXIAHB_DIV_SHIFT 9
#define SCU_HWSTRAP_AXIAHB_DIV_MASK (0x7 << SCU_HWSTRAP_AXIAHB_DIV_SHIFT)
DECLARE_GLOBAL_DATA_PTR;
/*
@ -86,6 +92,20 @@ static ulong ast2500_get_clkin(struct ast2500_scu *scu)
? 25 * 1000 * 1000 : 24 * 1000 * 1000;
}
static u32 ast2500_get_hclk(ulong clkin, struct ast2500_scu *scu)
{
u32 hpll_reg = readl(&scu->h_pll_param);
ulong axi_div = 2;
u32 rate;
ulong ahb_div = 1 + ((readl(&scu->hwstrap)
& SCU_HWSTRAP_AXIAHB_DIV_MASK)
>> SCU_HWSTRAP_AXIAHB_DIV_SHIFT);
rate = ast2500_get_hpll_rate(clkin, hpll_reg);
return (rate / axi_div / ahb_div);
}
/**
* Get current rate or uart clock
*
@ -147,6 +167,9 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = rate / apb_div;
}
break;
case ASPEED_CLK_AHB:
rate = ast2500_get_hclk(clkin, priv->scu);
break;
case ASPEED_CLK_SDIO:
{
ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)