Merge branch 'master' of git://git.denx.de/u-boot-coldfire
This commit is contained in:
commit
a6dd10c70b
@ -200,6 +200,10 @@ config TARGET_AMCORE
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bool "Support AMCORE"
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bool "Support AMCORE"
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select M5307
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select M5307
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||||||
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config TARGET_STMARK2
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bool "Support stmark2"
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select M54418
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endchoice
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endchoice
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source "board/BuS/eb_cpu5282/Kconfig"
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source "board/BuS/eb_cpu5282/Kconfig"
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@ -223,5 +227,6 @@ source "board/freescale/m54455evb/Kconfig"
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source "board/freescale/m547xevb/Kconfig"
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source "board/freescale/m547xevb/Kconfig"
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source "board/freescale/m548xevb/Kconfig"
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source "board/freescale/m548xevb/Kconfig"
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source "board/sysam/amcore/Kconfig"
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source "board/sysam/amcore/Kconfig"
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source "board/sysam/stmark2/Kconfig"
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endmenu
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endmenu
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@ -205,6 +205,7 @@ void cpu_init_f(void)
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/* FlexBus Chipselect */
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/* FlexBus Chipselect */
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init_fbcs();
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init_fbcs();
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#ifdef CONFIG_SYS_CS0_BASE
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/*
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/*
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* now the flash base address is no longer at 0 (Newer ColdFire family
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* now the flash base address is no longer at 0 (Newer ColdFire family
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* boot at address 0 instead of 0xFFnn_nnnn). The vector table must
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* boot at address 0 instead of 0xFFnn_nnnn). The vector table must
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@ -212,6 +213,7 @@ void cpu_init_f(void)
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*/
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*/
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if (CONFIG_SYS_CS0_BASE != 0)
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if (CONFIG_SYS_CS0_BASE != 0)
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setvbr(CONFIG_SYS_CS0_BASE);
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setvbr(CONFIG_SYS_CS0_BASE);
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#endif
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icache_enable();
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icache_enable();
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}
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}
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@ -159,6 +159,7 @@ asm_dram_init:
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move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
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move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
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clr.l %sp@-
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clr.l %sp@-
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#ifdef CONFIG_SYS_CS0_BASE
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/* Must disable global address */
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/* Must disable global address */
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move.l #0xFC008000, %a1
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move.l #0xFC008000, %a1
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move.l #(CONFIG_SYS_CS0_BASE), (%a1)
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move.l #(CONFIG_SYS_CS0_BASE), (%a1)
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@ -166,6 +167,7 @@ asm_dram_init:
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move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
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move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
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move.l #0xFC008004, %a1
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move.l #0xFC008004, %a1
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move.l #(CONFIG_SYS_CS0_MASK), (%a1)
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move.l #(CONFIG_SYS_CS0_MASK), (%a1)
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#endif
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#endif /* CONFIG_CF_SBF */
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#endif /* CONFIG_CF_SBF */
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#ifdef CONFIG_MCF5441x
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#ifdef CONFIG_MCF5441x
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@ -176,177 +178,12 @@ asm_dram_init:
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#if defined(CONFIG_CF_SBF)
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#if defined(CONFIG_CF_SBF)
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move.b #23, (%a1) /* dspi */
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move.b #23, (%a1) /* dspi */
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#endif
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#endif
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move.b #46, (%a1) /* DDR */
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#endif /* CONFIG_MCF5441x */
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/* slew settings */
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/* mandatory board level ddr-sdram init,
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move.l #0xEC094060, %a1
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* for both 5441x and 5445x
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move.b #0, (%a1)
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*/
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bsr sbf_dram_init
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/* use vco instead of cpu*2 clock for ddr clock */
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move.l #0xEC09001A, %a1
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move.w #0xE01D, (%a1)
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/* DDR settings */
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move.l #0xFC0B8180, %a1
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move.l #0x00000000, (%a1)
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move.l #0x40000000, (%a1)
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move.l #0xFC0B81AC, %a1
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move.l #0x01030203, (%a1)
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move.l #0xFC0B8000, %a1
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move.l #0x01010101, (%a1)+ /* 0x00 */
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move.l #0x00000101, (%a1)+ /* 0x04 */
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move.l #0x01010100, (%a1)+ /* 0x08 */
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move.l #0x01010000, (%a1)+ /* 0x0C */
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move.l #0x00010101, (%a1)+ /* 0x10 */
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move.l #0xFC0B8018, %a1
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move.l #0x00010100, (%a1)+ /* 0x18 */
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move.l #0x00000001, (%a1)+ /* 0x1C */
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move.l #0x01000001, (%a1)+ /* 0x20 */
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move.l #0x00000100, (%a1)+ /* 0x24 */
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move.l #0x00010001, (%a1)+ /* 0x28 */
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move.l #0x00000200, (%a1)+ /* 0x2C */
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move.l #0x01000002, (%a1)+ /* 0x30 */
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move.l #0x00000000, (%a1)+ /* 0x34 */
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move.l #0x00000100, (%a1)+ /* 0x38 */
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move.l #0x02000100, (%a1)+ /* 0x3C */
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move.l #0x02000407, (%a1)+ /* 0x40 */
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move.l #0x02030007, (%a1)+ /* 0x44 */
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move.l #0x02000100, (%a1)+ /* 0x48 */
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move.l #0x0A030203, (%a1)+ /* 0x4C */
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move.l #0x00020708, (%a1)+ /* 0x50 */
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move.l #0x00050008, (%a1)+ /* 0x54 */
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move.l #0x04030002, (%a1)+ /* 0x58 */
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move.l #0x00000004, (%a1)+ /* 0x5C */
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move.l #0x020A0000, (%a1)+ /* 0x60 */
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move.l #0x0C00000E, (%a1)+ /* 0x64 */
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move.l #0x00002004, (%a1)+ /* 0x68 */
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move.l #0x00000000, (%a1)+ /* 0x6C */
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move.l #0x00100010, (%a1)+ /* 0x70 */
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move.l #0x00100010, (%a1)+ /* 0x74 */
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move.l #0x00000000, (%a1)+ /* 0x78 */
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move.l #0x07990000, (%a1)+ /* 0x7C */
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move.l #0xFC0B80A0, %a1
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move.l #0x00000000, (%a1)+ /* 0xA0 */
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||||||
move.l #0x00C80064, (%a1)+ /* 0xA4 */
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move.l #0x44520002, (%a1)+ /* 0xA8 */
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move.l #0x00C80023, (%a1)+ /* 0xAC */
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move.l #0xFC0B80B4, %a1
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move.l #0x0000C350, (%a1) /* 0xB4 */
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||||||
move.l #0xFC0B80E0, %a1
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move.l #0x04000000, (%a1)+ /* 0xE0 */
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move.l #0x03000304, (%a1)+ /* 0xE4 */
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move.l #0x40040000, (%a1)+ /* 0xE8 */
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move.l #0xC0004004, (%a1)+ /* 0xEC */
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move.l #0x0642C000, (%a1)+ /* 0xF0 */
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move.l #0x00000642, (%a1)+ /* 0xF4 */
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move.l #0xFC0B8024, %a1
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tpf
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move.l #0x01000100, (%a1) /* 0x24 */
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||||||
move.l #0x2000, %d1
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jsr asm_delay
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#endif /* CONFIG_MCF5441x */
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||||||
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#ifdef CONFIG_MCF5445x
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/* Dram Initialization a1, a2, and d0 */
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/* mscr sdram */
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move.l #0xFC0A4074, %a1
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move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
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nop
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/* SDRAM Chip 0 and 1 */
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move.l #0xFC0B8110, %a1
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move.l #0xFC0B8114, %a2
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/* calculate the size */
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move.l #0x13, %d1
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move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
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#ifdef CONFIG_SYS_SDRAM_BASE1
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lsr.l #1, %d2
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#endif
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dramsz_loop:
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lsr.l #1, %d2
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||||||
add.l #1, %d1
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cmp.l #1, %d2
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bne dramsz_loop
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#ifdef CONFIG_SYS_NAND_BOOT
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beq asm_nand_chk_status
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#endif
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/* SDRAM Chip 0 and 1 */
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move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
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or.l %d1, (%a1)
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#ifdef CONFIG_SYS_SDRAM_BASE1
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move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
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or.l %d1, (%a2)
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||||||
#endif
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||||||
nop
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||||||
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||||||
/* dram cfg1 and cfg2 */
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||||||
move.l #0xFC0B8008, %a1
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||||||
move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
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||||||
nop
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||||||
move.l #0xFC0B800C, %a2
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||||||
move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
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||||||
nop
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|
||||||
|
|
||||||
move.l #0xFC0B8000, %a1 /* Mode */
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||||||
move.l #0xFC0B8004, %a2 /* Ctrl */
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|
||||||
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|
||||||
/* Issue PALL */
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|
||||||
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
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|
||||||
nop
|
|
||||||
|
|
||||||
#ifdef CONFIG_M54455EVB
|
|
||||||
/* Issue LEMR */
|
|
||||||
move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
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|
||||||
nop
|
|
||||||
move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
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|
||||||
nop
|
|
||||||
#endif
|
|
||||||
|
|
||||||
move.l #1000, %d1
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|
||||||
jsr asm_delay
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|
||||||
|
|
||||||
/* Issue PALL */
|
|
||||||
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
|
|
||||||
nop
|
|
||||||
|
|
||||||
/* Perform two refresh cycles */
|
|
||||||
move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
|
|
||||||
nop
|
|
||||||
move.l %d0, (%a2)
|
|
||||||
move.l %d0, (%a2)
|
|
||||||
nop
|
|
||||||
|
|
||||||
#ifdef CONFIG_M54455EVB
|
|
||||||
move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
|
|
||||||
nop
|
|
||||||
#elif defined(CONFIG_M54451EVB)
|
|
||||||
/* Issue LEMR */
|
|
||||||
move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
|
|
||||||
nop
|
|
||||||
move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
move.l #500, %d1
|
|
||||||
jsr asm_delay
|
|
||||||
|
|
||||||
move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
|
|
||||||
and.l #0x7FFFFFFF, %d1
|
|
||||||
#ifdef CONFIG_M54455EVB
|
|
||||||
or.l #0x10000C00, %d1
|
|
||||||
#elif defined(CONFIG_M54451EVB)
|
|
||||||
or.l #0x10000C00, %d1
|
|
||||||
#endif
|
|
||||||
move.l %d1, (%a2)
|
|
||||||
nop
|
|
||||||
|
|
||||||
move.l #2000, %d1
|
|
||||||
jsr asm_delay
|
|
||||||
#endif /* CONFIG_MCF5445x */
|
|
||||||
|
|
||||||
#ifdef CONFIG_CF_SBF
|
#ifdef CONFIG_CF_SBF
|
||||||
/*
|
/*
|
||||||
@ -507,6 +344,7 @@ asm_nand_init:
|
|||||||
movec %d0, %ACR2
|
movec %d0, %ACR2
|
||||||
movec %d0, %ACR3
|
movec %d0, %ACR3
|
||||||
|
|
||||||
|
#ifdef CONFIG_SYS_CS0_BASE
|
||||||
/* Must disable global address */
|
/* Must disable global address */
|
||||||
move.l #0xFC008000, %a1
|
move.l #0xFC008000, %a1
|
||||||
move.l #(CONFIG_SYS_CS0_BASE), (%a1)
|
move.l #(CONFIG_SYS_CS0_BASE), (%a1)
|
||||||
@ -514,6 +352,7 @@ asm_nand_init:
|
|||||||
move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
|
move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
|
||||||
move.l #0xFC008004, %a1
|
move.l #0xFC008004, %a1
|
||||||
move.l #(CONFIG_SYS_CS0_MASK), (%a1)
|
move.l #(CONFIG_SYS_CS0_MASK), (%a1)
|
||||||
|
#endif
|
||||||
|
|
||||||
/* NAND port configuration */
|
/* NAND port configuration */
|
||||||
move.l #0xEC094048, %a1
|
move.l #0xEC094048, %a1
|
||||||
@ -537,7 +376,7 @@ asm_nand_init:
|
|||||||
move.l #0x000e0000, (%a1)
|
move.l #0x000e0000, (%a1)
|
||||||
|
|
||||||
move.l #0x2000, %d1
|
move.l #0x2000, %d1
|
||||||
jsr asm_delay
|
bsr asm_delay
|
||||||
|
|
||||||
/* setup nand */
|
/* setup nand */
|
||||||
move.l #0xFC0FFF00, %a1
|
move.l #0xFC0FFF00, %a1
|
||||||
@ -565,7 +404,7 @@ asm_nand_read:
|
|||||||
move.l %d0, (%a0)
|
move.l %d0, (%a0)
|
||||||
|
|
||||||
move.l #0x200, %d1
|
move.l #0x200, %d1
|
||||||
jsr asm_delay
|
bsr asm_delay
|
||||||
|
|
||||||
asm_nand_chk_status:
|
asm_nand_chk_status:
|
||||||
move.l #0xFC0FFF38, %a4 /* isr */
|
move.l #0xFC0FFF38, %a4 /* isr */
|
||||||
@ -595,6 +434,7 @@ asm_nand_copy:
|
|||||||
|
|
||||||
#endif /* CONFIG_SYS_NAND_BOOT */
|
#endif /* CONFIG_SYS_NAND_BOOT */
|
||||||
|
|
||||||
|
.globl asm_delay
|
||||||
asm_delay:
|
asm_delay:
|
||||||
nop
|
nop
|
||||||
subq.l #1, %d1
|
subq.l #1, %d1
|
||||||
|
@ -33,12 +33,13 @@ void icache_enable(void)
|
|||||||
|
|
||||||
*cf_icache_status = 1;
|
*cf_icache_status = 1;
|
||||||
|
|
||||||
#ifdef CONFIG_CF_V4
|
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
|
||||||
__asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2));
|
__asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2));
|
||||||
__asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
|
__asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
|
||||||
#elif defined(CONFIG_CF_V4e)
|
#if defined(CONFIG_CF_V4E)
|
||||||
__asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
|
__asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
|
||||||
__asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
|
__asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
|
||||||
|
#endif
|
||||||
#else
|
#else
|
||||||
__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
|
__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
|
||||||
__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
|
__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
|
||||||
@ -54,16 +55,16 @@ void icache_disable(void)
|
|||||||
*cf_icache_status = 0;
|
*cf_icache_status = 0;
|
||||||
icache_invalid();
|
icache_invalid();
|
||||||
|
|
||||||
#ifdef CONFIG_CF_V4
|
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
|
||||||
__asm__ __volatile__("movec %0, %%acr2"::"r"(temp));
|
__asm__ __volatile__("movec %0, %%acr2"::"r"(temp));
|
||||||
__asm__ __volatile__("movec %0, %%acr3"::"r"(temp));
|
__asm__ __volatile__("movec %0, %%acr3"::"r"(temp));
|
||||||
#elif defined(CONFIG_CF_V4e)
|
#if defined(CONFIG_CF_V4E)
|
||||||
__asm__ __volatile__("movec %0, %%acr6"::"r"(temp));
|
__asm__ __volatile__("movec %0, %%acr6"::"r"(temp));
|
||||||
__asm__ __volatile__("movec %0, %%acr7"::"r"(temp));
|
__asm__ __volatile__("movec %0, %%acr7"::"r"(temp));
|
||||||
|
#endif
|
||||||
#else
|
#else
|
||||||
__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
|
__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
|
||||||
__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
|
__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -87,13 +88,13 @@ void dcache_enable(void)
|
|||||||
dcache_invalid();
|
dcache_invalid();
|
||||||
*cf_dcache_status = 1;
|
*cf_dcache_status = 1;
|
||||||
|
|
||||||
#ifdef CONFIG_CF_V4
|
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
|
||||||
__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
|
__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
|
||||||
__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
|
__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
|
||||||
#elif defined(CONFIG_CF_V4e)
|
#if defined(CONFIG_CF_V4E)
|
||||||
__asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
|
__asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
|
||||||
__asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
|
__asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
|
||||||
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR));
|
__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR));
|
||||||
@ -108,19 +109,19 @@ void dcache_disable(void)
|
|||||||
|
|
||||||
__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
|
__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
|
||||||
|
|
||||||
#ifdef CONFIG_CF_V4
|
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
|
||||||
__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
|
__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
|
||||||
__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
|
__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
|
||||||
#elif defined(CONFIG_CF_V4e)
|
#if defined(CONFIG_CF_V4E)
|
||||||
__asm__ __volatile__("movec %0, %%acr4"::"r"(temp));
|
__asm__ __volatile__("movec %0, %%acr4"::"r"(temp));
|
||||||
__asm__ __volatile__("movec %0, %%acr5"::"r"(temp));
|
__asm__ __volatile__("movec %0, %%acr5"::"r"(temp));
|
||||||
|
#endif
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
void dcache_invalid(void)
|
void dcache_invalid(void)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_CF_V4
|
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
|
||||||
u32 temp;
|
u32 temp;
|
||||||
|
|
||||||
temp = CONFIG_SYS_DCACHE_INV;
|
temp = CONFIG_SYS_DCACHE_INV;
|
||||||
|
@ -5,3 +5,5 @@
|
|||||||
#
|
#
|
||||||
|
|
||||||
obj-y = m54418twr.o
|
obj-y = m54418twr.o
|
||||||
|
extra-y += sbf_dram_init.o
|
||||||
|
|
||||||
|
86
board/freescale/m54418twr/sbf_dram_init.S
Normal file
86
board/freescale/m54418twr/sbf_dram_init.S
Normal file
@ -0,0 +1,86 @@
|
|||||||
|
/*
|
||||||
|
* Board-specific sbf ddr/sdram init.
|
||||||
|
*
|
||||||
|
* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
.global sbf_dram_init
|
||||||
|
.text
|
||||||
|
|
||||||
|
sbf_dram_init:
|
||||||
|
move.l #0xFC04002D, %a1
|
||||||
|
move.b #46, (%a1) /* DDR */
|
||||||
|
|
||||||
|
/* slew settings */
|
||||||
|
move.l #0xEC094060, %a1
|
||||||
|
move.b #0, (%a1)
|
||||||
|
|
||||||
|
/* use vco instead of cpu*2 clock for ddr clock */
|
||||||
|
move.l #0xEC09001A, %a1
|
||||||
|
move.w #0xE01D, (%a1)
|
||||||
|
|
||||||
|
/* DDR settings */
|
||||||
|
move.l #0xFC0B8180, %a1
|
||||||
|
move.l #0x00000000, (%a1)
|
||||||
|
move.l #0x40000000, (%a1)
|
||||||
|
|
||||||
|
move.l #0xFC0B81AC, %a1
|
||||||
|
move.l #0x01030203, (%a1)
|
||||||
|
|
||||||
|
move.l #0xFC0B8000, %a1
|
||||||
|
move.l #0x01010101, (%a1)+ /* 0x00 */
|
||||||
|
move.l #0x00000101, (%a1)+ /* 0x04 */
|
||||||
|
move.l #0x01010100, (%a1)+ /* 0x08 */
|
||||||
|
move.l #0x01010000, (%a1)+ /* 0x0C */
|
||||||
|
move.l #0x00010101, (%a1)+ /* 0x10 */
|
||||||
|
move.l #0xFC0B8018, %a1
|
||||||
|
move.l #0x00010100, (%a1)+ /* 0x18 */
|
||||||
|
move.l #0x00000001, (%a1)+ /* 0x1C */
|
||||||
|
move.l #0x01000001, (%a1)+ /* 0x20 */
|
||||||
|
move.l #0x00000100, (%a1)+ /* 0x24 */
|
||||||
|
move.l #0x00010001, (%a1)+ /* 0x28 */
|
||||||
|
move.l #0x00000200, (%a1)+ /* 0x2C */
|
||||||
|
move.l #0x01000002, (%a1)+ /* 0x30 */
|
||||||
|
move.l #0x00000000, (%a1)+ /* 0x34 */
|
||||||
|
move.l #0x00000100, (%a1)+ /* 0x38 */
|
||||||
|
move.l #0x02000100, (%a1)+ /* 0x3C */
|
||||||
|
move.l #0x02000407, (%a1)+ /* 0x40 */
|
||||||
|
move.l #0x02030007, (%a1)+ /* 0x44 */
|
||||||
|
move.l #0x02000100, (%a1)+ /* 0x48 */
|
||||||
|
move.l #0x0A030203, (%a1)+ /* 0x4C */
|
||||||
|
move.l #0x00020708, (%a1)+ /* 0x50 */
|
||||||
|
move.l #0x00050008, (%a1)+ /* 0x54 */
|
||||||
|
move.l #0x04030002, (%a1)+ /* 0x58 */
|
||||||
|
move.l #0x00000004, (%a1)+ /* 0x5C */
|
||||||
|
move.l #0x020A0000, (%a1)+ /* 0x60 */
|
||||||
|
move.l #0x0C00000E, (%a1)+ /* 0x64 */
|
||||||
|
move.l #0x00002004, (%a1)+ /* 0x68 */
|
||||||
|
move.l #0x00000000, (%a1)+ /* 0x6C */
|
||||||
|
move.l #0x00100010, (%a1)+ /* 0x70 */
|
||||||
|
move.l #0x00100010, (%a1)+ /* 0x74 */
|
||||||
|
move.l #0x00000000, (%a1)+ /* 0x78 */
|
||||||
|
move.l #0x07990000, (%a1)+ /* 0x7C */
|
||||||
|
move.l #0xFC0B80A0, %a1
|
||||||
|
move.l #0x00000000, (%a1)+ /* 0xA0 */
|
||||||
|
move.l #0x00C80064, (%a1)+ /* 0xA4 */
|
||||||
|
move.l #0x44520002, (%a1)+ /* 0xA8 */
|
||||||
|
move.l #0x00C80023, (%a1)+ /* 0xAC */
|
||||||
|
move.l #0xFC0B80B4, %a1
|
||||||
|
move.l #0x0000C350, (%a1) /* 0xB4 */
|
||||||
|
move.l #0xFC0B80E0, %a1
|
||||||
|
move.l #0x04000000, (%a1)+ /* 0xE0 */
|
||||||
|
move.l #0x03000304, (%a1)+ /* 0xE4 */
|
||||||
|
move.l #0x40040000, (%a1)+ /* 0xE8 */
|
||||||
|
move.l #0xC0004004, (%a1)+ /* 0xEC */
|
||||||
|
move.l #0x0642C000, (%a1)+ /* 0xF0 */
|
||||||
|
move.l #0x00000642, (%a1)+ /* 0xF4 */
|
||||||
|
move.l #0xFC0B8024, %a1
|
||||||
|
tpf
|
||||||
|
move.l #0x01000100, (%a1) /* 0x24 */
|
||||||
|
|
||||||
|
move.l #0x2000, %d1
|
||||||
|
bsr asm_delay
|
||||||
|
|
||||||
|
rts
|
@ -6,3 +6,4 @@
|
|||||||
#
|
#
|
||||||
|
|
||||||
obj-y = m54451evb.o
|
obj-y = m54451evb.o
|
||||||
|
extra-y += sbf_dram_init.o
|
||||||
|
97
board/freescale/m54451evb/sbf_dram_init.S
Normal file
97
board/freescale/m54451evb/sbf_dram_init.S
Normal file
@ -0,0 +1,97 @@
|
|||||||
|
/*
|
||||||
|
* Board-specific sbf ddr/sdram init.
|
||||||
|
*
|
||||||
|
* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <config.h>
|
||||||
|
|
||||||
|
.global sbf_dram_init
|
||||||
|
.text
|
||||||
|
|
||||||
|
sbf_dram_init:
|
||||||
|
/* Dram Initialization a1, a2, and d0 */
|
||||||
|
/* mscr sdram */
|
||||||
|
move.l #0xFC0A4074, %a1
|
||||||
|
move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
|
||||||
|
nop
|
||||||
|
|
||||||
|
/* SDRAM Chip 0 and 1 */
|
||||||
|
move.l #0xFC0B8110, %a1
|
||||||
|
move.l #0xFC0B8114, %a2
|
||||||
|
|
||||||
|
/* calculate the size */
|
||||||
|
move.l #0x13, %d1
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
|
||||||
|
#ifdef CONFIG_SYS_SDRAM_BASE1
|
||||||
|
lsr.l #1, %d2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
dramsz_loop:
|
||||||
|
lsr.l #1, %d2
|
||||||
|
add.l #1, %d1
|
||||||
|
cmp.l #1, %d2
|
||||||
|
bne dramsz_loop
|
||||||
|
#ifdef CONFIG_SYS_NAND_BOOT
|
||||||
|
beq asm_nand_chk_status
|
||||||
|
#endif
|
||||||
|
/* SDRAM Chip 0 and 1 */
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
|
||||||
|
or.l %d1, (%a1)
|
||||||
|
#ifdef CONFIG_SYS_SDRAM_BASE1
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
|
||||||
|
or.l %d1, (%a2)
|
||||||
|
#endif
|
||||||
|
nop
|
||||||
|
|
||||||
|
/* dram cfg1 and cfg2 */
|
||||||
|
move.l #0xFC0B8008, %a1
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
|
||||||
|
nop
|
||||||
|
move.l #0xFC0B800C, %a2
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
|
||||||
|
nop
|
||||||
|
|
||||||
|
move.l #0xFC0B8000, %a1 /* Mode */
|
||||||
|
move.l #0xFC0B8004, %a2 /* Ctrl */
|
||||||
|
|
||||||
|
/* Issue PALL */
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
|
||||||
|
nop
|
||||||
|
|
||||||
|
move.l #1000, %d1
|
||||||
|
bsr asm_delay
|
||||||
|
|
||||||
|
/* Issue PALL */
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
|
||||||
|
nop
|
||||||
|
|
||||||
|
/* Perform two refresh cycles */
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
|
||||||
|
nop
|
||||||
|
move.l %d0, (%a2)
|
||||||
|
move.l %d0, (%a2)
|
||||||
|
nop
|
||||||
|
|
||||||
|
/* Issue LEMR */
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
|
||||||
|
nop
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
|
||||||
|
|
||||||
|
move.l #500, %d1
|
||||||
|
bsr asm_delay
|
||||||
|
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
|
||||||
|
and.l #0x7FFFFFFF, %d1
|
||||||
|
|
||||||
|
or.l #0x10000C00, %d1
|
||||||
|
|
||||||
|
move.l %d1, (%a2)
|
||||||
|
nop
|
||||||
|
|
||||||
|
move.l #2000, %d1
|
||||||
|
bsr asm_delay
|
||||||
|
|
||||||
|
rts
|
@ -6,3 +6,4 @@
|
|||||||
#
|
#
|
||||||
|
|
||||||
obj-y = m54455evb.o
|
obj-y = m54455evb.o
|
||||||
|
extra-y += sbf_dram_init.o
|
||||||
|
101
board/freescale/m54455evb/sbf_dram_init.S
Normal file
101
board/freescale/m54455evb/sbf_dram_init.S
Normal file
@ -0,0 +1,101 @@
|
|||||||
|
/*
|
||||||
|
* Board-specific sbf ddr/sdram init.
|
||||||
|
*
|
||||||
|
* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <config.h>
|
||||||
|
|
||||||
|
.global sbf_dram_init
|
||||||
|
.text
|
||||||
|
|
||||||
|
sbf_dram_init:
|
||||||
|
/* Dram Initialization a1, a2, and d0 */
|
||||||
|
/* mscr sdram */
|
||||||
|
move.l #0xFC0A4074, %a1
|
||||||
|
move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
|
||||||
|
nop
|
||||||
|
|
||||||
|
/* SDRAM Chip 0 and 1 */
|
||||||
|
move.l #0xFC0B8110, %a1
|
||||||
|
move.l #0xFC0B8114, %a2
|
||||||
|
|
||||||
|
/* calculate the size */
|
||||||
|
move.l #0x13, %d1
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
|
||||||
|
#ifdef CONFIG_SYS_SDRAM_BASE1
|
||||||
|
lsr.l #1, %d2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
dramsz_loop:
|
||||||
|
lsr.l #1, %d2
|
||||||
|
add.l #1, %d1
|
||||||
|
cmp.l #1, %d2
|
||||||
|
bne dramsz_loop
|
||||||
|
#ifdef CONFIG_SYS_NAND_BOOT
|
||||||
|
beq asm_nand_chk_status
|
||||||
|
#endif
|
||||||
|
/* SDRAM Chip 0 and 1 */
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
|
||||||
|
or.l %d1, (%a1)
|
||||||
|
#ifdef CONFIG_SYS_SDRAM_BASE1
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
|
||||||
|
or.l %d1, (%a2)
|
||||||
|
#endif
|
||||||
|
nop
|
||||||
|
|
||||||
|
/* dram cfg1 and cfg2 */
|
||||||
|
move.l #0xFC0B8008, %a1
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
|
||||||
|
nop
|
||||||
|
move.l #0xFC0B800C, %a2
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
|
||||||
|
nop
|
||||||
|
|
||||||
|
move.l #0xFC0B8000, %a1 /* Mode */
|
||||||
|
move.l #0xFC0B8004, %a2 /* Ctrl */
|
||||||
|
|
||||||
|
/* Issue PALL */
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
|
||||||
|
nop
|
||||||
|
|
||||||
|
/* Issue LEMR */
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
|
||||||
|
nop
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
|
||||||
|
nop
|
||||||
|
|
||||||
|
move.l #1000, %d1
|
||||||
|
bsr asm_delay
|
||||||
|
|
||||||
|
/* Issue PALL */
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
|
||||||
|
nop
|
||||||
|
|
||||||
|
/* Perform two refresh cycles */
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
|
||||||
|
nop
|
||||||
|
move.l %d0, (%a2)
|
||||||
|
move.l %d0, (%a2)
|
||||||
|
nop
|
||||||
|
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
|
||||||
|
nop
|
||||||
|
|
||||||
|
move.l #500, %d1
|
||||||
|
bsr asm_delay
|
||||||
|
|
||||||
|
move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
|
||||||
|
and.l #0x7FFFFFFF, %d1
|
||||||
|
|
||||||
|
or.l #0x10000C00, %d1
|
||||||
|
|
||||||
|
move.l %d1, (%a2)
|
||||||
|
nop
|
||||||
|
|
||||||
|
move.l #2000, %d1
|
||||||
|
bsr asm_delay
|
||||||
|
|
||||||
|
rts
|
15
board/sysam/stmark2/Kconfig
Normal file
15
board/sysam/stmark2/Kconfig
Normal file
@ -0,0 +1,15 @@
|
|||||||
|
if TARGET_STMARK2
|
||||||
|
|
||||||
|
config SYS_CPU
|
||||||
|
default "mcf5445x"
|
||||||
|
|
||||||
|
config SYS_BOARD
|
||||||
|
default "stmark2"
|
||||||
|
|
||||||
|
config SYS_VENDOR
|
||||||
|
default "sysam"
|
||||||
|
|
||||||
|
config SYS_CONFIG_NAME
|
||||||
|
default "stmark2"
|
||||||
|
|
||||||
|
endif
|
6
board/sysam/stmark2/MAINTAINERS
Normal file
6
board/sysam/stmark2/MAINTAINERS
Normal file
@ -0,0 +1,6 @@
|
|||||||
|
STMARK2 BOARD
|
||||||
|
M: Angelo Dureghello <angelo@sysam.it>
|
||||||
|
S: Maintained
|
||||||
|
F: board/sysam/stmark2/
|
||||||
|
F: include/configs/stmark2.h
|
||||||
|
F: configs/stmark2_defconfig
|
8
board/sysam/stmark2/Makefile
Normal file
8
board/sysam/stmark2/Makefile
Normal file
@ -0,0 +1,8 @@
|
|||||||
|
#
|
||||||
|
# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
|
||||||
|
obj-y = stmark2.o
|
||||||
|
extra-y += sbf_dram_init.o
|
119
board/sysam/stmark2/sbf_dram_init.S
Normal file
119
board/sysam/stmark2/sbf_dram_init.S
Normal file
@ -0,0 +1,119 @@
|
|||||||
|
/*
|
||||||
|
* Board-specific early ddr/sdram init.
|
||||||
|
*
|
||||||
|
* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
.equ PPMCR0, 0xfc04002d
|
||||||
|
.equ MSCR_SDRAMC, 0xec094060
|
||||||
|
.equ MISCCR2, 0xec09001a
|
||||||
|
.equ DDR_RCR, 0xfc0b8180
|
||||||
|
.equ DDR_PADCR, 0xfc0b81ac
|
||||||
|
.equ DDR_CR00, 0xfc0b8000
|
||||||
|
.equ DDR_CR06, 0xfc0b8018
|
||||||
|
.equ DDR_CR09, 0xfc0b8024
|
||||||
|
.equ DDR_CR40, 0xfc0b80a0
|
||||||
|
.equ DDR_CR45, 0xfc0b80b4
|
||||||
|
.equ DDR_CR56, 0xfc0b80e0
|
||||||
|
|
||||||
|
.global sbf_dram_init
|
||||||
|
.text
|
||||||
|
|
||||||
|
sbf_dram_init:
|
||||||
|
/* CD46 = DDR on */
|
||||||
|
move.l #PPMCR0, %a1
|
||||||
|
move.b #46, (%a1)
|
||||||
|
|
||||||
|
/* stmark 2, max drive strength */
|
||||||
|
move.l #MSCR_SDRAMC, %a1
|
||||||
|
move.b #1, (%a1)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* use cpu clock, seems more realiable
|
||||||
|
*
|
||||||
|
* DDR2 clock is serviced from DDR controller as input clock / 2
|
||||||
|
* so, if clock comes from
|
||||||
|
* vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured)
|
||||||
|
* cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured)
|
||||||
|
*
|
||||||
|
* .
|
||||||
|
* / \ DDR2 can't be clocked lower than 125Mhz
|
||||||
|
* / ! \ DDR2 init must pass further i/dcache enable test
|
||||||
|
* /_____\
|
||||||
|
* WARNING
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* cpu / 2 = 125 Mhz for 480 Mhz pll */
|
||||||
|
move.l #MISCCR2, %a1
|
||||||
|
move.w #0xa01d, (%a1)
|
||||||
|
|
||||||
|
/* DDR force sw reset settings */
|
||||||
|
move.l #DDR_RCR, %a1
|
||||||
|
move.l #0x00000000, (%a1)
|
||||||
|
move.l #0x40000000, (%a1)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good,
|
||||||
|
* 500/700 mV are ok
|
||||||
|
*/
|
||||||
|
move.l #DDR_PADCR, %a1
|
||||||
|
move.l #0x01030203, (%a1) /* as freescale tower */
|
||||||
|
|
||||||
|
move.l #DDR_CR00, %a1
|
||||||
|
move.l #0x01010101, (%a1)+ /* 0x00 */
|
||||||
|
move.l #0x00000101, (%a1)+ /* 0x04 */
|
||||||
|
move.l #0x01010100, (%a1)+ /* 0x08 */
|
||||||
|
move.l #0x01010000, (%a1)+ /* 0x0C */
|
||||||
|
move.l #0x00010101, (%a1)+ /* 0x10 */
|
||||||
|
move.l #DDR_CR06, %a1
|
||||||
|
move.l #0x00010100, (%a1)+ /* 0x18 */
|
||||||
|
move.l #0x00000001, (%a1)+ /* 0x1C */
|
||||||
|
move.l #0x01000001, (%a1)+ /* 0x20 */
|
||||||
|
move.l #0x00000100, (%a1)+ /* 0x24 */
|
||||||
|
move.l #0x00010001, (%a1)+ /* 0x28 */
|
||||||
|
move.l #0x00000200, (%a1)+ /* 0x2C */
|
||||||
|
move.l #0x01000002, (%a1)+ /* 0x30 */
|
||||||
|
move.l #0x00000000, (%a1)+ /* 0x34 */
|
||||||
|
move.l #0x00000100, (%a1)+ /* 0x38 */
|
||||||
|
move.l #0x02000100, (%a1)+ /* 0x3C */
|
||||||
|
move.l #0x02000407, (%a1)+ /* 0x40 */
|
||||||
|
move.l #0x02030007, (%a1)+ /* 0x44 */
|
||||||
|
move.l #0x02000100, (%a1)+ /* 0x48 */
|
||||||
|
move.l #0x0A030203, (%a1)+ /* 0x4C */
|
||||||
|
move.l #0x00020708, (%a1)+ /* 0x50 */
|
||||||
|
move.l #0x00050008, (%a1)+ /* 0x54 */
|
||||||
|
move.l #0x04030002, (%a1)+ /* 0x58 */
|
||||||
|
move.l #0x00000004, (%a1)+ /* 0x5C */
|
||||||
|
move.l #0x020A0000, (%a1)+ /* 0x60 */
|
||||||
|
move.l #0x0C00000E, (%a1)+ /* 0x64 */
|
||||||
|
move.l #0x00002004, (%a1)+ /* 0x68 */
|
||||||
|
move.l #0x00000000, (%a1)+ /* 0x6C */
|
||||||
|
move.l #0x00100010, (%a1)+ /* 0x70 */
|
||||||
|
move.l #0x00100010, (%a1)+ /* 0x74 */
|
||||||
|
move.l #0x00000000, (%a1)+ /* 0x78 */
|
||||||
|
move.l #0x07990000, (%a1)+ /* 0x7C */
|
||||||
|
move.l #DDR_CR40, %a1
|
||||||
|
move.l #0x00000000, (%a1)+ /* 0xA0 */
|
||||||
|
move.l #0x00C80064, (%a1)+ /* 0xA4 */
|
||||||
|
move.l #0x44520002, (%a1)+ /* 0xA8 */
|
||||||
|
move.l #0x00C80023, (%a1)+ /* 0xAC */
|
||||||
|
move.l #DDR_CR45, %a1
|
||||||
|
move.l #0x0000C350, (%a1) /* 0xB4 */
|
||||||
|
move.l #DDR_CR56, %a1
|
||||||
|
move.l #0x04000000, (%a1)+ /* 0xE0 */
|
||||||
|
move.l #0x03000304, (%a1)+ /* 0xE4 */
|
||||||
|
move.l #0x40040000, (%a1)+ /* 0xE8 */
|
||||||
|
move.l #0xC0004004, (%a1)+ /* 0xEC */
|
||||||
|
move.l #0x0642C000, (%a1)+ /* 0xF0 */
|
||||||
|
move.l #0x00000642, (%a1)+ /* 0xF4 */
|
||||||
|
move.l #DDR_CR09, %a1
|
||||||
|
tpf
|
||||||
|
move.l #0x01000100, (%a1) /* 0x24 */
|
||||||
|
|
||||||
|
move.l #0x2000, %d1
|
||||||
|
bsr asm_delay
|
||||||
|
|
||||||
|
|
||||||
|
rts
|
47
board/sysam/stmark2/stmark2.c
Normal file
47
board/sysam/stmark2/stmark2.c
Normal file
@ -0,0 +1,47 @@
|
|||||||
|
/*
|
||||||
|
* Board-specific init.
|
||||||
|
*
|
||||||
|
* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <spi.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/immap.h>
|
||||||
|
#include <mmc.h>
|
||||||
|
#include <fsl_esdhc.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
int checkboard(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* need to to:
|
||||||
|
* Check serial flash size. if 2mb evb, else 8mb demo
|
||||||
|
*/
|
||||||
|
puts("Board: ");
|
||||||
|
puts("Sysam stmark2\n");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int dram_init(void)
|
||||||
|
{
|
||||||
|
u32 dramsize;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Serial Boot: The dram is already initialized in start.S
|
||||||
|
* only require to return DRAM size
|
||||||
|
*/
|
||||||
|
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
|
||||||
|
|
||||||
|
gd->ram_size = dramsize;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int testdram(void)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
26
configs/stmark2_defconfig
Normal file
26
configs/stmark2_defconfig
Normal file
@ -0,0 +1,26 @@
|
|||||||
|
CONFIG_M68K=y
|
||||||
|
CONFIG_SYS_TEXT_BASE=0x47E00000
|
||||||
|
CONFIG_TARGET_STMARK2=y
|
||||||
|
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000"
|
||||||
|
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||||
|
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
|
||||||
|
CONFIG_HUSH_PARSER=y
|
||||||
|
CONFIG_SYS_PROMPT="stmark2 $ "
|
||||||
|
# CONFIG_CMD_BDI is not set
|
||||||
|
# CONFIG_CMD_CONSOLE is not set
|
||||||
|
# CONFIG_CMD_IMLS is not set
|
||||||
|
# CONFIG_CMD_EXPORTENV is not set
|
||||||
|
# CONFIG_CMD_IMPORTENV is not set
|
||||||
|
CONFIG_CMD_LOADB=y
|
||||||
|
# CONFIG_CMD_LOADS is not set
|
||||||
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
CONFIG_CMD_SF=y
|
||||||
|
CONFIG_CMD_SPI=y
|
||||||
|
# CONFIG_CMD_FPGA is not set
|
||||||
|
# CONFIG_CMD_SETEXPR is not set
|
||||||
|
# CONFIG_CMD_NET is not set
|
||||||
|
# CONFIG_CMD_NFS is not set
|
||||||
|
CONFIG_CMD_CACHE=y
|
||||||
|
CONFIG_SPI_FLASH=y
|
||||||
|
CONFIG_SPI_FLASH_MTD=y
|
||||||
|
CONFIG_REGEX=y
|
@ -24,6 +24,8 @@
|
|||||||
#define CONFIG_SYS_UART_PORT (0)
|
#define CONFIG_SYS_UART_PORT (0)
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
|
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
|
||||||
|
|
||||||
|
#define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*)
|
||||||
|
|
||||||
#undef CONFIG_WATCHDOG
|
#undef CONFIG_WATCHDOG
|
||||||
|
|
||||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||||
|
@ -23,6 +23,8 @@
|
|||||||
#define CONFIG_MCFUART
|
#define CONFIG_MCFUART
|
||||||
#define CONFIG_SYS_UART_PORT (0)
|
#define CONFIG_SYS_UART_PORT (0)
|
||||||
|
|
||||||
|
#define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*)
|
||||||
|
|
||||||
#undef CONFIG_WATCHDOG
|
#undef CONFIG_WATCHDOG
|
||||||
|
|
||||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||||
|
@ -23,6 +23,8 @@
|
|||||||
#define CONFIG_MCFUART
|
#define CONFIG_MCFUART
|
||||||
#define CONFIG_SYS_UART_PORT (0)
|
#define CONFIG_SYS_UART_PORT (0)
|
||||||
|
|
||||||
|
#define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*)
|
||||||
|
|
||||||
#undef CONFIG_WATCHDOG
|
#undef CONFIG_WATCHDOG
|
||||||
|
|
||||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||||
|
199
include/configs/stmark2.h
Normal file
199
include/configs/stmark2.h
Normal file
@ -0,0 +1,199 @@
|
|||||||
|
/*
|
||||||
|
* Sysam stmark2 board configuration
|
||||||
|
*
|
||||||
|
* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __STMARK2_CONFIG_H
|
||||||
|
#define __STMARK2_CONFIG_H
|
||||||
|
|
||||||
|
#define CONFIG_STMARK2
|
||||||
|
#define CONFIG_HOSTNAME stmark2
|
||||||
|
|
||||||
|
#define CONFIG_MCFUART
|
||||||
|
#define CONFIG_SYS_UART_PORT 0
|
||||||
|
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
|
||||||
|
|
||||||
|
#define LDS_BOARD_TEXT \
|
||||||
|
board/sysam/stmark2/sbf_dram_init.o (.text*)
|
||||||
|
|
||||||
|
#define CONFIG_TIMESTAMP
|
||||||
|
|
||||||
|
#define CONFIG_BOOTARGS \
|
||||||
|
"console=ttyS0,115200 root=/dev/ram0 rw " \
|
||||||
|
"rootfstype=ramfs " \
|
||||||
|
"rdinit=/bin/init " \
|
||||||
|
"devtmpfs.mount=1"
|
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND \
|
||||||
|
"sf probe 0:1 50000000; " \
|
||||||
|
"sf read ${loadaddr} 0x100000 ${kern_size}; " \
|
||||||
|
"bootm ${loadaddr}"
|
||||||
|
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
"kern_size=0x700000\0" \
|
||||||
|
"loadaddr=0x40001000\0" \
|
||||||
|
"-(rootfs)\0" \
|
||||||
|
"update_uboot=loady ${loadaddr}; " \
|
||||||
|
"sf probe 0:1 50000000; " \
|
||||||
|
"sf erase 0 0x80000; " \
|
||||||
|
"sf write ${loadaddr} 0 ${filesize}\0" \
|
||||||
|
"update_kernel=loady ${loadaddr}; " \
|
||||||
|
"setenv kern_size ${filesize}; saveenv; " \
|
||||||
|
"sf probe 0:1 50000000; " \
|
||||||
|
"sf erase 0x100000 0x700000; " \
|
||||||
|
"sf write ${loadaddr} 0x100000 ${filesize}\0" \
|
||||||
|
"update_rootfs=loady ${loadaddr}; " \
|
||||||
|
"sf probe 0:1 50000000; " \
|
||||||
|
"sf erase 0x00800000 0x100000; " \
|
||||||
|
"sf write ${loadaddr} 0x00800000 ${filesize}\0" \
|
||||||
|
""
|
||||||
|
|
||||||
|
/* Realtime clock */
|
||||||
|
#undef CONFIG_MCFRTC
|
||||||
|
#define CONFIG_RTC_MCFRRTC
|
||||||
|
#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
|
||||||
|
|
||||||
|
/* spi not partitions */
|
||||||
|
#define CONFIG_CMD_MTDPARTS
|
||||||
|
#define CONFIG_MTD_DEVICE
|
||||||
|
#define CONFIG_JFFS2_CMDLINE
|
||||||
|
#define CONFIG_JFFS2_DEV "nor0"
|
||||||
|
#define MTDIDS_DEFAULT "nor0=spi-flash.0"
|
||||||
|
#define MTDPARTS_DEFAULT \
|
||||||
|
"mtdparts=spi-flash.0:" \
|
||||||
|
"1m(u-boot)," \
|
||||||
|
"7m(kernel)," \
|
||||||
|
"-(rootfs)"
|
||||||
|
|
||||||
|
/* Timer */
|
||||||
|
#define CONFIG_MCFTMR
|
||||||
|
#undef CONFIG_MCFPIT
|
||||||
|
|
||||||
|
/* DSPI and Serial Flash */
|
||||||
|
#define CONFIG_CF_SPI
|
||||||
|
#define CONFIG_CF_DSPI
|
||||||
|
#define CONFIG_SF_DEFAULT_SPEED 50000000
|
||||||
|
#define CONFIG_SERIAL_FLASH
|
||||||
|
#define CONFIG_HARD_SPI
|
||||||
|
#define CONFIG_SPI_FLASH_ISSI
|
||||||
|
#define CONFIG_ENV_SPI_BUS 0
|
||||||
|
#define CONFIG_ENV_SPI_CS 1
|
||||||
|
|
||||||
|
#define CONFIG_SYS_SBFHDR_SIZE 0x7
|
||||||
|
|
||||||
|
#define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
|
||||||
|
DSPI_CTAR_PCSSCK_1CLK | \
|
||||||
|
DSPI_CTAR_PASC(0) | \
|
||||||
|
DSPI_CTAR_PDT(0) | \
|
||||||
|
DSPI_CTAR_CSSCK(0) | \
|
||||||
|
DSPI_CTAR_ASC(0) | \
|
||||||
|
DSPI_CTAR_DT(1) | \
|
||||||
|
DSPI_CTAR_BR(6))
|
||||||
|
#define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
|
||||||
|
#define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
|
||||||
|
|
||||||
|
/* Input, PCI, Flexbus, and VCO */
|
||||||
|
#define CONFIG_EXTRA_CLOCK
|
||||||
|
|
||||||
|
#define CONFIG_PRAM 2048 /* 2048 KB */
|
||||||
|
#define CONFIG_SYS_LONGHELP
|
||||||
|
#define CONFIG_AUTO_COMPLETE
|
||||||
|
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||||
|
|
||||||
|
/* Print Buffer Size */
|
||||||
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||||
|
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||||
|
#define CONFIG_SYS_MAXARGS 16
|
||||||
|
/* Boot Argument Buffer Size */
|
||||||
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||||
|
|
||||||
|
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
|
||||||
|
#define CONFIG_SYS_MBAR 0xFC000000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Definitions for initial stack pointer and data area (in internal SRAM)
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
|
||||||
|
/* End of used area in internal SRAM */
|
||||||
|
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
|
||||||
|
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
|
||||||
|
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
|
||||||
|
GENERATED_GBL_DATA_SIZE) - 32)
|
||||||
|
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||||
|
#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Start addresses for the final memory configuration
|
||||||
|
* (Set up by the startup code)
|
||||||
|
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||||
|
#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
|
||||||
|
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
|
||||||
|
#define CONFIG_SYS_DRAM_TEST
|
||||||
|
|
||||||
|
#if defined(CONFIG_CF_SBF)
|
||||||
|
#define CONFIG_SERIAL_BOOT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SERIAL_BOOT)
|
||||||
|
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
|
||||||
|
#else
|
||||||
|
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
|
||||||
|
/* Reserve 256 kB for Monitor */
|
||||||
|
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
|
||||||
|
/* Reserve 256 kB for malloc() */
|
||||||
|
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* For booting Linux, the board info and command line data
|
||||||
|
* have to be in the first 8 MB of memory, since this is
|
||||||
|
* the maximum mapped by the Linux kernel during initialization ??
|
||||||
|
*/
|
||||||
|
/* Initial Memory map for Linux */
|
||||||
|
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
|
||||||
|
(CONFIG_SYS_SDRAM_SIZE << 20))
|
||||||
|
|
||||||
|
/* Configuration for environment
|
||||||
|
* Environment is embedded in u-boot in the second sector of the flash
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(CONFIG_CF_SBF)
|
||||||
|
#define CONFIG_ENV_IS_IN_SPI_FLASH 1
|
||||||
|
#define CONFIG_ENV_SPI_CS 1
|
||||||
|
#define CONFIG_ENV_OFFSET 0x40000
|
||||||
|
#define CONFIG_ENV_SIZE 0x2000
|
||||||
|
#define CONFIG_ENV_SECT_SIZE 0x10000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#undef CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
|
/* Cache Configuration */
|
||||||
|
#define CONFIG_SYS_CACHELINE_SIZE 16
|
||||||
|
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||||
|
CONFIG_SYS_INIT_RAM_SIZE - 8)
|
||||||
|
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||||
|
CONFIG_SYS_INIT_RAM_SIZE - 4)
|
||||||
|
#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
|
||||||
|
#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
|
||||||
|
#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
|
||||||
|
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
|
||||||
|
CF_ACR_EN | CF_ACR_SM_ALL)
|
||||||
|
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
|
||||||
|
CF_CACR_ICINVA | CF_CACR_EUSP)
|
||||||
|
#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
|
||||||
|
CF_CACR_DEC | CF_CACR_DDCM_P | \
|
||||||
|
CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
|
||||||
|
|
||||||
|
#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||||
|
CONFIG_SYS_INIT_RAM_SIZE - 12)
|
||||||
|
|
||||||
|
#endif /* __STMARK2_CONFIG_H */
|
@ -2294,6 +2294,7 @@ CONFIG_STM32_GPIO
|
|||||||
CONFIG_STM32_HSE_HZ
|
CONFIG_STM32_HSE_HZ
|
||||||
CONFIG_STM32_HZ
|
CONFIG_STM32_HZ
|
||||||
CONFIG_STM32_SERIAL
|
CONFIG_STM32_SERIAL
|
||||||
|
CONFIG_STMARK2
|
||||||
CONFIG_STRIDER
|
CONFIG_STRIDER
|
||||||
CONFIG_STRIDER_CON
|
CONFIG_STRIDER_CON
|
||||||
CONFIG_STRIDER_CON_DP
|
CONFIG_STRIDER_CON_DP
|
||||||
|
Loading…
Reference in New Issue
Block a user