ARM: UniPhier: move DDR related configuration to Kconfig
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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b603c68129
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a69e037e46
@ -32,4 +32,27 @@ config CMD_PINMON
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The boot mode pins are latched when the system reset is deasserted
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The boot mode pins are latched when the system reset is deasserted
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and determine which device the system should load a boot image from.
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and determine which device the system should load a boot image from.
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config DRAM_INIT
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bool
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default SPL_BUILD
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choice
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prompt "DDR3 Frequency select"
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depends on DRAM_INIT
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config DDR_FREQ_1600
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bool "DDR3 1600"
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depends on MACH_PH1_PRO4 || MACH_PH1_LD4
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config DDR_FREQ_1333
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bool "DDR3 1333"
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depends on MACH_PH1_LD4 || MACH_PH1_SLD8
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endchoice
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config DDR_FREQ
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int
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default 1333 if DDR_FREQ_1333
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default 1600 if DDR_FREQ_1600
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endmenu
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endmenu
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@ -16,7 +16,7 @@ int dram_init(void)
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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#ifdef CONFIG_DRAM_INIT
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led_write(B, 4, , );
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led_write(B, 4, , );
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{
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{
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@ -7,5 +7,4 @@ obj-y += platdevice.o
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obj-y += boot-mode.o
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obj-y += boot-mode.o
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obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
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obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
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sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
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sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
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obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
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obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
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umc_init.o
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@ -149,10 +149,6 @@ int umc_init(void)
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CONFIG_SDRAM1_SIZE / 0x08000000);
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CONFIG_SDRAM1_SIZE / 0x08000000);
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}
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}
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#if CONFIG_DDR_FREQ != 1333 && CONFIG_DDR_FREQ != 1600
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#error Unsupported DDR Frequency.
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#endif
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#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
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#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
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(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
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(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
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CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
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CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
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@ -7,5 +7,4 @@ obj-y += platdevice.o
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obj-y += boot-mode.o
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obj-y += boot-mode.o
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obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \
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obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \
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sg_init.o pll_init.o clkrst_init.o pinctrl.o
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sg_init.o pll_init.o clkrst_init.o pinctrl.o
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obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
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obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
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umc_init.o
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@ -122,10 +122,6 @@ int umc_init(void)
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CONFIG_SDRAM1_SIZE / 0x08000000);
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CONFIG_SDRAM1_SIZE / 0x08000000);
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}
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}
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#if CONFIG_DDR_FREQ != 1600
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#error Unsupported DDR frequency.
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#endif
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#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
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#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
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(CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
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(CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
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((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
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((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
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@ -7,5 +7,4 @@ obj-y += platdevice.o
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obj-y += boot-mode.o
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obj-y += boot-mode.o
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obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
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obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
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sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
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sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
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obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
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obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
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umc_init.o
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@ -129,10 +129,6 @@ int umc_init(void)
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CONFIG_SDRAM1_SIZE / 0x08000000);
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CONFIG_SDRAM1_SIZE / 0x08000000);
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}
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}
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#if CONFIG_DDR_FREQ != 1333
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#error Unsupported DDR frequency.
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#endif
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#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
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#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
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(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
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(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
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CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
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CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
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@ -37,8 +37,6 @@
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#define CONFIG_DDR_NUM_CH0 1
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#define CONFIG_DDR_NUM_CH0 1
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#define CONFIG_DDR_NUM_CH1 1
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#define CONFIG_DDR_NUM_CH1 1
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#define CONFIG_DDR_FREQ 1600
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/*
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/*
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* Memory Size & Mapping
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* Memory Size & Mapping
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*/
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*/
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@ -37,8 +37,6 @@
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#define CONFIG_DDR_NUM_CH0 2
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#define CONFIG_DDR_NUM_CH0 2
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#define CONFIG_DDR_NUM_CH1 2
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#define CONFIG_DDR_NUM_CH1 2
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#define CONFIG_DDR_FREQ 1600
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#define CONFIG_UNIPHIER_SMP
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#define CONFIG_UNIPHIER_SMP
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/*
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/*
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@ -37,8 +37,6 @@
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#define CONFIG_DDR_NUM_CH0 1
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#define CONFIG_DDR_NUM_CH0 1
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#define CONFIG_DDR_NUM_CH1 1
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#define CONFIG_DDR_NUM_CH1 1
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#define CONFIG_DDR_FREQ 1333
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/* #define CONFIG_DDR_STANDARD */
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/* #define CONFIG_DDR_STANDARD */
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/*
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/*
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