ARM: UniPhier: move DDR related configuration to Kconfig

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada 2014-11-06 20:16:42 +09:00
parent b603c68129
commit a69e037e46
11 changed files with 27 additions and 25 deletions

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@ -32,4 +32,27 @@ config CMD_PINMON
The boot mode pins are latched when the system reset is deasserted The boot mode pins are latched when the system reset is deasserted
and determine which device the system should load a boot image from. and determine which device the system should load a boot image from.
config DRAM_INIT
bool
default SPL_BUILD
choice
prompt "DDR3 Frequency select"
depends on DRAM_INIT
config DDR_FREQ_1600
bool "DDR3 1600"
depends on MACH_PH1_PRO4 || MACH_PH1_LD4
config DDR_FREQ_1333
bool "DDR3 1333"
depends on MACH_PH1_LD4 || MACH_PH1_SLD8
endchoice
config DDR_FREQ
int
default 1333 if DDR_FREQ_1333
default 1600 if DDR_FREQ_1600
endmenu endmenu

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@ -16,7 +16,7 @@ int dram_init(void)
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE; gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) #ifdef CONFIG_DRAM_INIT
led_write(B, 4, , ); led_write(B, 4, , );
{ {

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@ -7,5 +7,4 @@ obj-y += platdevice.o
obj-y += boot-mode.o obj-y += boot-mode.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
umc_init.o

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@ -149,10 +149,6 @@ int umc_init(void)
CONFIG_SDRAM1_SIZE / 0x08000000); CONFIG_SDRAM1_SIZE / 0x08000000);
} }
#if CONFIG_DDR_FREQ != 1333 && CONFIG_DDR_FREQ != 1600
#error Unsupported DDR Frequency.
#endif
#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ #if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1

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@ -7,5 +7,4 @@ obj-y += platdevice.o
obj-y += boot-mode.o obj-y += boot-mode.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \ obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \
sg_init.o pll_init.o clkrst_init.o pinctrl.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
umc_init.o

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@ -122,10 +122,6 @@ int umc_init(void)
CONFIG_SDRAM1_SIZE / 0x08000000); CONFIG_SDRAM1_SIZE / 0x08000000);
} }
#if CONFIG_DDR_FREQ != 1600
#error Unsupported DDR frequency.
#endif
#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \ #if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
(CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \ (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \ ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \

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@ -7,5 +7,4 @@ obj-y += platdevice.o
obj-y += boot-mode.o obj-y += boot-mode.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
umc_init.o

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@ -129,10 +129,6 @@ int umc_init(void)
CONFIG_SDRAM1_SIZE / 0x08000000); CONFIG_SDRAM1_SIZE / 0x08000000);
} }
#if CONFIG_DDR_FREQ != 1333
#error Unsupported DDR frequency.
#endif
#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ #if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1

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@ -37,8 +37,6 @@
#define CONFIG_DDR_NUM_CH0 1 #define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1 #define CONFIG_DDR_NUM_CH1 1
#define CONFIG_DDR_FREQ 1600
/* /*
* Memory Size & Mapping * Memory Size & Mapping
*/ */

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@ -37,8 +37,6 @@
#define CONFIG_DDR_NUM_CH0 2 #define CONFIG_DDR_NUM_CH0 2
#define CONFIG_DDR_NUM_CH1 2 #define CONFIG_DDR_NUM_CH1 2
#define CONFIG_DDR_FREQ 1600
#define CONFIG_UNIPHIER_SMP #define CONFIG_UNIPHIER_SMP
/* /*

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@ -37,8 +37,6 @@
#define CONFIG_DDR_NUM_CH0 1 #define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1 #define CONFIG_DDR_NUM_CH1 1
#define CONFIG_DDR_FREQ 1333
/* #define CONFIG_DDR_STANDARD */ /* #define CONFIG_DDR_STANDARD */
/* /*