From e23544cffe7057d678846498ec0fbf21eff9bc95 Mon Sep 17 00:00:00 2001 From: Andy Chiu Date: Tue, 1 Nov 2022 11:57:59 +0800 Subject: [PATCH 01/16] net: xilinx_axi: add PCS/PMA PHY If we bridge an external PHY to Xilinx's PCS/PMA PHY and would like to get and set the real status of the PHY facing the external world. Then we should phy_connect() to the external PHY instead of the PCS/PMA one. Thus, we add a pcs-handle DT entry, which have been merged in Linux, and leave the configuration of it to the driver itself. Unlike Linux, where the PCS/PMA PHY is managed by phylink, managing the PCS/PMA PHY is only internal to the driver in U-Boot. The PCS/PMA PHY pressents only when the phy-mode is configured as SGMII or 1000Base-X, so it is always 1 Gbps and full-duplex and we may skip passing link information out. Signed-off-by: Andy Chiu Reviewed-by: Greentime Hu Link: https://lore.kernel.org/r/20221101035800.912644-2-andy.chiu@sifive.com Signed-off-by: Michal Simek --- drivers/net/xilinx_axi_emac.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 5f5bc650be..5a4d838812 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -109,6 +109,7 @@ struct axidma_plat { struct eth_pdata eth_pdata; struct axidma_reg *dmatx; struct axidma_reg *dmarx; + int pcsaddr; int phyaddr; u8 eth_hasnobuf; int phy_of_handle; @@ -119,6 +120,7 @@ struct axidma_plat { struct axidma_priv { struct axidma_reg *dmatx; struct axidma_reg *dmarx; + int pcsaddr; int phyaddr; struct axi_regs *iobase; phy_interface_t interface; @@ -301,6 +303,13 @@ static int axiemac_phy_init(struct udevice *dev) if (IS_ENABLED(CONFIG_DM_ETH_PHY)) priv->phyaddr = eth_phy_get_addr(dev); + /* + * Set address of PCS/PMA PHY to the one pointed by phy-handle for + * backward compatibility. + */ + if (priv->phyaddr != -1 && priv->pcsaddr == 0) + priv->pcsaddr = priv->phyaddr; + if (priv->phyaddr == -1) { /* Detect the PHY address */ for (i = 31; i >= 0; i--) { @@ -348,12 +357,12 @@ static int setup_phy(struct udevice *dev) * after DMA and ethernet resets and hence * check and clear if set. */ - ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp); + ret = phyread(priv, priv->pcsaddr, MII_BMCR, &temp); if (ret) return 0; if (temp & BMCR_ISOLATE) { temp &= ~BMCR_ISOLATE; - ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp); + ret = phywrite(priv, priv->pcsaddr, MII_BMCR, temp); if (ret) return 0; } @@ -784,6 +793,7 @@ static int axi_emac_probe(struct udevice *dev) if (priv->mactype == EMAC_1G) { priv->eth_hasnobuf = plat->eth_hasnobuf; + priv->pcsaddr = plat->pcsaddr; priv->phyaddr = plat->phyaddr; priv->phy_of_handle = plat->phy_of_handle; priv->interface = pdata->phy_interface; @@ -861,6 +871,8 @@ static int axi_emac_of_to_plat(struct udevice *dev) if (plat->mactype == EMAC_1G) { plat->phyaddr = -1; + /* PHYAD 0 always redirects to the PCS/PMA PHY */ + plat->pcsaddr = 0; offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); @@ -878,6 +890,16 @@ static int axi_emac_of_to_plat(struct udevice *dev) plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node, "xlnx,eth-hasnobuf"); + + if (pdata->phy_interface == PHY_INTERFACE_MODE_SGMII || + pdata->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, + "pcs-handle"); + if (offset > 0) { + plat->pcsaddr = fdtdec_get_int(gd->fdt_blob, + offset, "reg", -1); + } + } } return 0; From f3558be91e5086f1673d47ba8c430e7640b32e71 Mon Sep 17 00:00:00 2001 From: Andy Chiu Date: Tue, 1 Nov 2022 11:58:00 +0800 Subject: [PATCH 02/16] net: xilinx_axi: check PCS/PMA PHY status in setup_phy Both PCS/PMA PHY and the external PHY need to have a valid link status in order to have Ethernet traffic. Check and wait this status at setup_phy() so that we could diagnose if there is a PHY issue. Signed-off-by: Andy Chiu Reviewed-by: Greentime Hu Link: https://lore.kernel.org/r/20221101035800.912644-3-andy.chiu@sifive.com Signed-off-by: Michal Simek --- drivers/net/xilinx_axi_emac.c | 44 +++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 5a4d838812..3e9919993d 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -342,6 +342,45 @@ static int axiemac_phy_init(struct udevice *dev) return 0; } +static int pcs_pma_startup(struct axidma_priv *priv) +{ + u32 rc, retry_cnt = 0; + u16 mii_reg; + + rc = phyread(priv, priv->pcsaddr, MII_BMCR, &mii_reg); + if (rc) + goto failed_mdio; + + if (!(mii_reg & BMCR_ANENABLE)) { + mii_reg |= BMCR_ANENABLE; + if (phywrite(priv, priv->pcsaddr, MII_BMCR, mii_reg)) + goto failed_mdio; + } + + /* + * Check the internal PHY status and warn user if the link between it + * and the external PHY is not obtained. + */ + debug("axiemac: waiting for link status of the PCS/PMA PHY"); + while (retry_cnt * 10 < PHY_ANEG_TIMEOUT) { + rc = phyread(priv, priv->pcsaddr, MII_BMSR, &mii_reg); + if ((mii_reg & BMSR_LSTATUS) && mii_reg != 0xffff && !rc) { + debug(".Done\n"); + return 0; + } + if ((retry_cnt++ % 10) == 0) + debug("."); + mdelay(10); + } + debug("\n"); + printf("axiemac: Warning, PCS/PMA PHY@%d is not ready, link is down\n", + priv->pcsaddr); + return 1; +failed_mdio: + printf("axiemac: MDIO to the PCS/PMA PHY has failed\n"); + return 1; +} + /* Setting axi emac and phy to proper setting */ static int setup_phy(struct udevice *dev) { @@ -373,6 +412,11 @@ static int setup_phy(struct udevice *dev) phydev->dev->name); return 0; } + if (priv->interface == PHY_INTERFACE_MODE_SGMII || + priv->interface == PHY_INTERFACE_MODE_1000BASEX) { + if (pcs_pma_startup(priv)) + return 0; + } if (!phydev->link) { printf("%s: No link.\n", phydev->dev->name); return 0; From d9efdc7d424ddfdc2aafeee4268435f9f46dd1db Mon Sep 17 00:00:00 2001 From: Lukas Funke Date: Fri, 28 Oct 2022 14:15:47 +0200 Subject: [PATCH 03/16] arm64: zynqmp: dynamically mark r5 cores as used When Linux boot takes over control of the pmu (by signaling PM_INIT_FINALIZE via ipi), pmu will switch off 'unused' rpu cores. The Xilinx zynqmp fsbl prevents switching off those cores by marking rpu cores as 'used' when loading code partitions to those cores. The current u-boot SPL is missing this behaviour, which results in halting rpu cores during Linux boot. This commit mimics the xilinx zynqmp fsbl behavior by marking r5 cores as used when they are released during boot. Signed-off-by: Lukas Funke Signed-off-by: Lukas Funke Link: https://lore.kernel.org/r/20221028121547.26464-2-lukas.funke-oss@weidmueller.com Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/include/mach/hardware.h | 4 ++- arch/arm/mach-zynqmp/mp.c | 26 ++++++++++++++++++++ 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index a70d6d611b..70221e0305 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -175,7 +175,9 @@ struct csu_regs { #define ZYNQMP_PMU_BASEADDR 0xFFD80000 struct pmu_regs { - u32 reserved[18]; + u32 reserved0[16]; + u32 gen_storage4; /* 0x40 */ + u32 reserved1[1]; u32 gen_storage6; /* 0x48 */ }; diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 949456d530..2891878973 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -42,6 +42,9 @@ #define ZYNQMP_MAX_CORES 6 +#define ZYNQMP_RPU0_USE_MASK BIT(1) +#define ZYNQMP_RPU1_USE_MASK BIT(2) + int is_core_valid(unsigned int core) { if (core < ZYNQMP_MAX_CORES) @@ -250,6 +253,27 @@ void initialize_tcm(bool mode) } } +static void mark_r5_used(u32 nr, u8 mode) +{ + u32 mask = 0; + + if (mode == LOCK) { + mask = ZYNQMP_RPU0_USE_MASK | ZYNQMP_RPU1_USE_MASK; + } else { + switch (nr) { + case ZYNQMP_CORE_RPU0: + mask = ZYNQMP_RPU0_USE_MASK; + break; + case ZYNQMP_CORE_RPU1: + mask = ZYNQMP_RPU1_USE_MASK; + break; + default: + return; + } + } + zynqmp_mmio_write((ulong)&pmu_base->gen_storage4, mask, mask); +} + int cpu_release(u32 nr, int argc, char *const argv[]) { if (nr <= ZYNQMP_CORE_APU3) { @@ -305,6 +329,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) write_tcm_boot_trampoline(boot_addr_uniq); dcache_enable(); set_r5_halt_mode(nr, RELEASE, LOCK); + mark_r5_used(nr, LOCK); } else if (!strncmp(argv[1], "split", 5)) { printf("R5 split mode\n"); set_r5_reset(nr, SPLIT); @@ -317,6 +342,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) write_tcm_boot_trampoline(boot_addr_uniq); dcache_enable(); set_r5_halt_mode(nr, RELEASE, SPLIT); + mark_r5_used(nr, SPLIT); } else { printf("Unsupported mode\n"); return 1; From a5e770b21ccc4d3ffc5cf50cab481cb0e35ee6ce Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Wed, 23 Nov 2022 02:04:51 -0700 Subject: [PATCH 04/16] spi: zynqmp_gqspi: Update tapdelay value The driver was using an incorrect value for GQSPI_LPBK_DLY_ADJ_DLY_1 tapdelay for Versal for frequencies above 100MHz. Change it from 2 to 1 based on the recommended value in IP spec. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20221123090451.11409-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/spi/zynqmp_gqspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 48eff777df..83a5c8aebf 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -94,7 +94,7 @@ #define GQSPI_BAUD_DIV_SHIFT 2 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5 -#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x2 +#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x1 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3 #define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3 #define GQSPI_USE_DATA_DLY 0x1 From 31e66aea373cfa98f151a44be7b4cd7b13f98b41 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Fri, 25 Nov 2022 14:16:39 +0530 Subject: [PATCH 05/16] arm64: versal: Enable REMAKE_ELF for mini_ospi/mini_qspi Enable the config REMAKE_ELF in xilinx_versal_mini_ospi_defconfig and xilinx_versal_mini_qspi_defconfig which generates u-boot.elf. This commit a8c281d4b737("Convert CONFIG_REMAKE_ELF to Kconfig") misses to enable this config in these defconfigs. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20221125084639.23835-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- configs/xilinx_versal_mini_ospi_defconfig | 1 + configs/xilinx_versal_mini_qspi_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index 2c4e21028d..abcd20ba85 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE0000 # CONFIG_EXPERT is not set +CONFIG_REMAKE_ELF=y # CONFIG_AUTOBOOT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig index 0062f6a69f..9ca9b7e68a 100644 --- a/configs/xilinx_versal_mini_qspi_defconfig +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE0000 # CONFIG_EXPERT is not set +CONFIG_REMAKE_ELF=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set # CONFIG_AUTOBOOT is not set CONFIG_LOGLEVEL=0 From 906e20a613abdcba5f558ac8e93cb6fad464f786 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Fri, 25 Nov 2022 16:14:13 +0530 Subject: [PATCH 06/16] spi: zynqmp_qspi: Add support for 64-bit read/write When we pass the 64-bit address to read/write, only lower 32-bit address is getting updated. Program the upper 32-bit address in the DMA destination memory address MSBs register, which can handle upto 44-bit destination address. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20221125104413.26140-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- drivers/spi/zynqmp_gqspi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 83a5c8aebf..335b458cb9 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -662,7 +662,7 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv, static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, u32 gen_fifo_cmd, u32 *buf) { - u32 addr; + unsigned long addr; u32 size; u32 actuallen = priv->len; u32 totallen = priv->len; @@ -678,7 +678,9 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, totallen -= priv->len; /* Save remaining bytes length to read */ actuallen = priv->len; /* Actual number of bytes reading */ - writel((unsigned long)buf, &dma_regs->dmadst); + writel(lower_32_bits((unsigned long)buf), &dma_regs->dmadst); + writel(upper_32_bits((unsigned long)buf) & GENMASK(11, 0), + &dma_regs->dmadstmsb); writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize); writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier); addr = (unsigned long)buf; From f3538a3cbe8aa29e5b7188e223f926da79788d63 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 Nov 2022 12:48:44 +0100 Subject: [PATCH 07/16] xilinx: Add option to select SC id instead of DUT id for SC support Reading MAC address from on board EEPROM requires different type for System Controller (SC). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/90bb7cc5463568a690b979f18c8d42556986b46d.1669204122.git.michal.simek@amd.com --- board/xilinx/Kconfig | 9 +++++++++ board/xilinx/common/fru.h | 1 + board/xilinx/common/fru_ops.c | 6 +++++- 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 746a2332ad..7b31d7eaed 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -82,3 +82,12 @@ config CMD_FRU information present in the device. The FRU Information is used to primarily to provide "inventory" information about the boards that the FRU Information Device is located on. + +config FRU_SC + bool "FRU system controller decoding" + help + Xilinx System Controller (SC) FRU format is describing boards from two + angles. One from DUT and then from SC. DUT is default option for + the main CPU. SC behaves more or less as slave and have different ID. + If you build U-Boot for SC you should enable this option to get proper + MAC address. diff --git a/board/xilinx/common/fru.h b/board/xilinx/common/fru.h index 59f6b722cf..586c41b66e 100644 --- a/board/xilinx/common/fru.h +++ b/board/xilinx/common/fru.h @@ -90,6 +90,7 @@ struct fru_table { #define FRU_MULTIREC_MAC_OFFSET 4 #define FRU_LAST_REC BIT(7) #define FRU_DUT_MACID 0x31 +#define FRU_SC_MACID 0x11 /* This should be minimum of fields */ #define FRU_BOARD_AREA_TOTAL_FIELDS 5 diff --git a/board/xilinx/common/fru_ops.c b/board/xilinx/common/fru_ops.c index 49846ae3d6..c4f009affc 100644 --- a/board/xilinx/common/fru_ops.c +++ b/board/xilinx/common/fru_ops.c @@ -239,8 +239,12 @@ static int fru_parse_multirec(unsigned long addr) if (mrc.rec_type == FRU_MULTIREC_TYPE_OEM) { struct fru_multirec_mac *mac = (void *)addr + hdr_len; + u32 type = FRU_DUT_MACID; - if (mac->ver == FRU_DUT_MACID) { + if (CONFIG_IS_ENABLED(FRU_SC)) + type = FRU_SC_MACID; + + if (mac->ver == type) { mac_len = mrc.len - FRU_MULTIREC_MAC_OFFSET; memcpy(&fru_data.mac.macid, mac->macid, mac_len); } From 2e3c10eea0b7f31bc608cc1fc2f24db9d346dee2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 Nov 2022 09:27:08 +0100 Subject: [PATCH 08/16] xilinx: Remove unused ZYNQ_MAC_IN_EEPROM/ZYNQ_GEM_I2C_MAC_OFFSET entries The commit ba74bcf3e07b ("xilinx: common: Remove zynq_board_read_rom_ethaddr()") removed zynq_board_read_rom_ethaddr() because xlnx,eeprom link via DT chosen node is no longer used. But forget to remove Kconfig entries which are used by this code only. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f97451ed33409838efea4071553b6da795cfc578.1669192026.git.michal.simek@amd.com --- board/xilinx/Kconfig | 17 ----------------- ...azedev_cc_v1_0_ultrazedev_som_v1_0_defconfig | 2 -- configs/syzygy_hub_defconfig | 2 -- configs/xilinx_zynqmp_virt_defconfig | 2 -- 4 files changed, 23 deletions(-) diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 7b31d7eaed..4f0776e8bd 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -58,23 +58,6 @@ config BOOT_SCRIPT_OFFSET help Specifies distro boot script offset in NAND/QSPI/NOR flash. -config ZYNQ_MAC_IN_EEPROM - bool "Reading MAC address from EEPROM" - help - Enable this option if your MAC address is saved in eeprom and - xlnx,eeprom DT property in chosen node points to it. - -if ZYNQ_MAC_IN_EEPROM - -config ZYNQ_GEM_I2C_MAC_OFFSET - hex "Set the I2C MAC offset" - default 0x0 - depends on DM_I2C - help - Set the MAC offset for i2C. - -endif - config CMD_FRU bool "FRU information for product" help diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig index 943b4da21d..ce07f1633e 100644 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -8,8 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0" CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_ZYNQ_MAC_IN_EEPROM=y -CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xfa CONFIG_ZYNQMP_PSU_INIT_ENABLED=y CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_DEBUG_UART=y diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index acce95ec02..179cb52212 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -9,8 +9,6 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-syzygy-hub" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y -CONFIG_ZYNQ_MAC_IN_EEPROM=y -CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 9696e418da..4732c39bdb 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -13,8 +13,6 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x1E80000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_ZYNQ_MAC_IN_EEPROM=y -CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_CMD_FRU=y CONFIG_ZYNQMP_USB=y CONFIG_SYS_LOAD_ADDR=0x8000000 From 9129a6b49a4d74f20b824a03b63da2d59139927f Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Sat, 3 Dec 2022 22:49:39 +0100 Subject: [PATCH 09/16] board/xilinx/zynqmp/MAINTAINERS: change e-mail address for Luca Ceresoli My Bootlin address is the preferred one now. Signed-off-by: Luca Ceresoli Signed-off-by: Luca Ceresoli Link: https://lore.kernel.org/r/20221203214939.56608-1-luca@lucaceresoli.net Signed-off-by: Michal Simek --- board/xilinx/zynqmp/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index 17a2766413..07b91b81c9 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -11,7 +11,7 @@ F: configs/xilinx_zynqmp* F: configs/avnet_ultra96_rev1_defconfig ARM ZYNQMP AVNET ULTRAZED EV BOARD -M: Luca Ceresoli +M: Luca Ceresoli S: Maintained F: arch/arm/dts/avnet-ultrazedev-* F: configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig From 74673ca705829bd6321ff9e4ebf1dc0742bc2647 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 2 Dec 2022 09:18:06 +0100 Subject: [PATCH 10/16] arm64: zynqmp: Do not include psu_init to U-Boot by default The commit ed35de617013 ("Convert CONFIG_ZYNQMP_PSU_INIT_ENABLED to Kconfig") converted CONFIG_ZYNQMP_PSU_INIT_ENABLED symbol and enabled it by default which is not correct configuration. Intention of this config was to have it enabled by default for SPL and provide an option to users to also do low level initialization directly from U-Boot. That's why it is necessary to define second symbol with SPL marking in it and properly use symbols depends on usage in Makefile. Also disable ZYNQMP_PSU_INIT_ENABLED from boards which enables it by default. CONFIG_SPL_ZYNQMP_PSU_INIT_ENABLED is enabled by default when SPL is enabled. Reported-by: Venkatesh Yadav Abbarapu Reviewed-by: Luca Ceresoli Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d5fcbd66b05bf0d7ef594e66464ee23b48c5e4cc.1669969083.git.michal.simek@amd.com --- arch/arm/mach-zynqmp/Kconfig | 9 ++++++++- arch/arm/mach-zynqmp/Makefile | 2 +- board/xilinx/zynqmp/Makefile | 6 +----- ...vnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig | 1 - configs/xilinx_zynqmp_mini_defconfig | 1 - configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 - configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 - configs/xilinx_zynqmp_mini_nand_defconfig | 1 - configs/xilinx_zynqmp_mini_nand_single_defconfig | 1 - configs/xilinx_zynqmp_mini_qspi_defconfig | 1 - 10 files changed, 10 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 66045067d2..fd6f07715a 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -142,7 +142,14 @@ config ZYNQMP_PSU_INIT_ENABLED bool "Include psu_init" select BOARD_EARLY_INIT_F help - Include psu_init to full u-boot. SPL include psu_init by default. + Include psu_init to full u-boot. + +config SPL_ZYNQMP_PSU_INIT_ENABLED + bool "Include psu_init in SPL" + default y if SPL + select BOARD_EARLY_INIT_F + help + Include psu_init by default in SPL. config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED bool "Overwrite SPL bootmode" diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index 4f9f6b56a9..bb1830c846 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -8,4 +8,4 @@ obj-y += cpu.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o -obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o +obj-$(CONFIG_$(SPL_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index a914028753..732f909fc2 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -31,11 +31,7 @@ $(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/ endif endif -ifdef_any_of = $(filter-out undefined,$(foreach v,$(1),$(origin $(v)))) - -ifneq ($(call ifdef_any_of, CONFIG_ZYNQMP_PSU_INIT_ENABLED CONFIG_SPL_BUILD),) -obj-y += $(init-objs) -endif +obj-$(CONFIG_$(SPL_)ZYNQMP_PSU_INIT_ENABLED) += $(init-objs) ifdef CONFIG_SPL_BUILD ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"") diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig index ce07f1633e..0a3d710a8b 100644 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -8,7 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0" CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_ZYNQMP_PSU_INIT_ENABLED=y CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x00000000 diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index 245b6a42b9..959b14859f 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -7,7 +7,6 @@ CONFIG_SYS_MALLOC_LEN=0x1a00 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini" CONFIG_SYS_MEM_RSVD_FOR_MMU=y -CONFIG_ZYNQMP_PSU_INIT_ENABLED=y # CONFIG_CMD_ZYNQMP is not set CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_SYS_MEMTEST_START=0x00000000 diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index adf1dae66e..3aa4b6d5b7 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -10,7 +10,6 @@ CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc0" CONFIG_SPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL=y -CONFIG_ZYNQMP_PSU_INIT_ENABLED=y # CONFIG_CMD_ZYNQMP is not set CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index 9d799ad0e3..ecbb7c4f1d 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -10,7 +10,6 @@ CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc1" CONFIG_SPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL=y -CONFIG_ZYNQMP_PSU_INIT_ENABLED=y # CONFIG_CMD_ZYNQMP is not set CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index 29040a39e9..0b1ee4560d 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -7,7 +7,6 @@ CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" -CONFIG_ZYNQMP_PSU_INIT_ENABLED=y # CONFIG_CMD_ZYNQMP is not set CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig index 7c17c061d4..c25d5cb371 100644 --- a/configs/xilinx_zynqmp_mini_nand_single_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig @@ -7,7 +7,6 @@ CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" -CONFIG_ZYNQMP_PSU_INIT_ENABLED=y # CONFIG_CMD_ZYNQMP is not set CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 513b51998d..af88565be0 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -10,7 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi" CONFIG_SPL=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_ZYNQMP_NO_DDR=y -CONFIG_ZYNQMP_PSU_INIT_ENABLED=y # CONFIG_CMD_ZYNQMP is not set # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0x8000000 From 92e690053630f8884133305a66ab03ea1a09bf5c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 29 Nov 2022 16:09:42 +0100 Subject: [PATCH 11/16] arm64: zynqmp: Do not enable IPI by default ZynqMP mini configurations are not using IPI driver and enabling this is adding additional ~1200 Bytes (depends on configuration). This ends up in situation that there is no enough space in OCM for relocation that's why disable this driver for all mini configurations. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c71bab3927cb71ae517d9c21f59f3d5cf0caf712.1669734580.git.michal.simek@amd.com --- arch/arm/Kconfig | 4 ++-- configs/xilinx_zynqmp_mini_defconfig | 1 + configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 + configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 + configs/xilinx_zynqmp_mini_nand_defconfig | 1 + configs/xilinx_zynqmp_mini_nand_single_defconfig | 1 + configs/xilinx_zynqmp_mini_qspi_defconfig | 1 + 7 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f95ed71b24..3f68d0988b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1302,7 +1302,7 @@ config ARCH_ZYNQMP select DM select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART select DM_ETH if NET - select DM_MAILBOX + imply DM_MAILBOX select DM_MMC if MMC select DM_SERIAL select DM_SPI if SPI @@ -1319,7 +1319,7 @@ config ARCH_ZYNQMP imply SPL_FIRMWARE if SPL select SPL_SEPARATE_BSS if SPL select SUPPORT_SPL - select ZYNQMP_IPI + imply ZYNQMP_IPI if DM_MAILBOX select SOC_DEVICE imply BOARD_LATE_INIT imply CMD_DM diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index 959b14859f..d8b3aab94f 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -58,6 +58,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_DM_MAILBOX is not set # CONFIG_MMC is not set CONFIG_ARM_DCC=y CONFIG_PANIC_HANG=y diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index 3aa4b6d5b7..a1ee98dfc2 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -70,6 +70,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y +# CONFIG_DM_MAILBOX is not set CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index ecbb7c4f1d..88c95d4ce2 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -70,6 +70,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y +# CONFIG_DM_MAILBOX is not set CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index 0b1ee4560d..0e035348db 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_DM_MAILBOX is not set # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig index c25d5cb371..5255419c75 100644 --- a/configs/xilinx_zynqmp_mini_nand_single_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_DM_MAILBOX is not set # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index af88565be0..6861f73980 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -75,6 +75,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y # CONFIG_GPIO is not set # CONFIG_I2C is not set # CONFIG_INPUT is not set +# CONFIG_DM_MAILBOX is not set # CONFIG_MMC is not set # CONFIG_SPI_FLASH_SMART_HWCAPS is not set # CONFIG_SPI_FLASH_UNLOCK_ALL is not set From 6a664a7bd40261c38874beac264a1fb5b4ae1a5d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 29 Nov 2022 13:23:20 +0100 Subject: [PATCH 12/16] ARM: zynq: Add missing twd timer for mini configurations The commit b7e0750d8872 ("zynq: Convert arm twd timer to DM driver") switched timer to DM but missing to add nodes to all mini configurations. Based on it missing timer end up in non functional system where any delay doesn't work. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/2020fc7e3d4760e890265485b3c7e18eb1caf8be.1669724598.git.michal.simek@amd.com --- arch/arm/dts/zynq-cse-nand.dts | 7 +++++++ arch/arm/dts/zynq-cse-nor.dts | 7 +++++++ arch/arm/dts/zynq-cse-qspi.dtsi | 7 +++++++ 3 files changed, 21 insertions(+) diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts index 32cb3bffcb..27adfb9216 100644 --- a/arch/arm/dts/zynq-cse-nand.dts +++ b/arch/arm/dts/zynq-cse-nand.dts @@ -86,6 +86,13 @@ reg = <0x100 0x100>; }; }; + + scutimer: timer@f8f00600 { + u-boot,dm-pre-reloc; + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8f00600 0x20>; + clock-frequency = <333333333>; + }; }; }; diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts index 197fbd717a..f22a149f79 100644 --- a/arch/arm/dts/zynq-cse-nor.dts +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -85,6 +85,13 @@ #address-cells = <1>; #size-cells = <1>; }; + + scutimer: timer@f8f00600 { + u-boot,dm-pre-reloc; + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8f00600 0x20>; + clock-frequency = <333333333>; + }; }; }; diff --git a/arch/arm/dts/zynq-cse-qspi.dtsi b/arch/arm/dts/zynq-cse-qspi.dtsi index 38410eeca8..f7ac92b802 100644 --- a/arch/arm/dts/zynq-cse-qspi.dtsi +++ b/arch/arm/dts/zynq-cse-qspi.dtsi @@ -116,6 +116,13 @@ reg = <0x100 0x100>; }; }; + + scutimer: timer@f8f00600 { + u-boot,dm-pre-reloc; + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8f00600 0x20>; + clock-frequency = <333333333>; + }; }; }; From 0d1a55fcbc009535c480a954198b1e3630864bfc Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Tue, 29 Nov 2022 04:41:34 -0700 Subject: [PATCH 13/16] spi: cadence-qspi: Remove condition for calling enable linear mode cadence_qspi_apb_enable_linear_mode() has a weak function defined, so no need to gaurd this under if (CONFIG_IS_ENABLED(ARCH_VERSAL)). In cadence_qspi_apb_write_execute(), enable linear mode is called twice by mistake, remove extra one. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20221129114134.18909-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/spi/cadence_qspi_apb.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index cfae5dcbda..d1f89138ef 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -735,8 +735,7 @@ int cadence_qspi_apb_read_execute(struct cadence_spi_priv *priv, void *buf = op->data.buf.in; size_t len = op->data.nbytes; - if (CONFIG_IS_ENABLED(ARCH_VERSAL)) - cadence_qspi_apb_enable_linear_mode(true); + cadence_qspi_apb_enable_linear_mode(true); if (priv->use_dac_mode && (from + len < priv->ahbsize)) { if (len < 256 || @@ -905,9 +904,6 @@ int cadence_qspi_apb_write_execute(struct cadence_spi_priv *priv, const void *buf = op->data.buf.out; size_t len = op->data.nbytes; - if (CONFIG_IS_ENABLED(ARCH_VERSAL)) - cadence_qspi_apb_enable_linear_mode(true); - /* * Some flashes like the Cypress Semper flash expect a dummy 4-byte * address (all 0s) with the read status register command in DTR mode. From 7d13f72d74c7ed7e60d8e603a52de34061ff3dd0 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Tue, 29 Nov 2022 11:18:31 +0100 Subject: [PATCH 14/16] arm64: versal-net: Enable defconfig for Micron octal flashes Micron mt35 series octal flashes are under config option CONFIG_SPI_FLASH_MT35XU. Enable it in default defconfig for octal flashes to be detected. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/dfaf73a72c7b408f1b8530f411c405d3dcf9f854.1669717110.git.michal.simek@amd.com --- configs/xilinx_versal_net_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 431a8de9fc..2fdf99f7cb 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -87,6 +87,7 @@ CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set From b40d154ced47d43005f683f7e089b9c016c8ea3d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 2 Dec 2022 14:06:15 +0100 Subject: [PATCH 15/16] xilinx: zynqmp: Fix SPL_FS_LOAD_PAYLOAD_NAME usage SPL_FS_LOAD_PAYLOAD_NAME depends on SPL to be enabled. If SPL is not enabled code still expects SPL_FS_LOAD_PAYLOAD_NAME to be present. That's why setup proper dependency in the code. And by doing so also change the logic around dfu_alt_info string composition to be simpler. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/3989c390a4acae13a1b05c040e14fb3d68bced02.1669986373.git.michal.simek@amd.com --- board/xilinx/zynqmp/zynqmp.c | 45 +++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 5fe0873fe2..579708d2e0 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -611,8 +611,7 @@ enum env_location env_get_location(enum env_operation op, int prio) void set_dfu_alt_info(char *interface, char *devstr) { - int multiboot; - int bootseq = 0; + int multiboot, bootseq = 0, len = 0; ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); @@ -634,29 +633,33 @@ void set_dfu_alt_info(char *interface, char *devstr) case SD1_LSHFT_MODE: case SD_MODE1: bootseq = mmc_get_env_dev(); - if (!multiboot) - snprintf(buf, DFU_ALT_BUF_LEN, - "mmc %d=boot.bin fat %d 1;" - "%s fat %d 1", - bootseq, bootseq, - CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq); - else - snprintf(buf, DFU_ALT_BUF_LEN, - "mmc %d=boot%04d.bin fat %d 1;" - "%s fat %d 1", - bootseq, multiboot, bootseq, - CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, "mmc %d=boot", + bootseq); + + if (multiboot) + len += snprintf(buf + len, DFU_ALT_BUF_LEN, + "%04d", multiboot); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1", + bootseq); +#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) + len += snprintf(buf + len, DFU_ALT_BUF_LEN, ";%s fat %d 1", + CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq); +#endif break; -#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS) case QSPI_MODE_24BIT: case QSPI_MODE_32BIT: - snprintf(buf, DFU_ALT_BUF_LEN, - "sf 0:0=boot.bin raw %x 0x1500000;" - "%s raw 0x%x 0x500000", - multiboot * SZ_32K, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, - CONFIG_SYS_SPI_U_BOOT_OFFS); - break; + len += snprintf(buf + len, DFU_ALT_BUF_LEN, + "sf 0:0=boot.bin raw %x 0x1500000", + multiboot * SZ_32K); +#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) && defined(CONFIG_SYS_SPI_U_BOOT_OFFS) + len += snprintf(buf + len, DFU_ALT_BUF_LEN, + ";%s raw 0x%x 0x500000", + CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, + CONFIG_SYS_SPI_U_BOOT_OFFS); #endif + break; default: return; } From 7ad3c09e7911e71c9a16a30aa052093a8f9b7e7c Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Mon, 21 Nov 2022 22:18:33 -0700 Subject: [PATCH 16/16] mtd: spi-nor-core: Invert logic to reflect sst26 flash unlocked flash_is_locked is changed to flash_is_unlocked with commit 513c6071ce73 ("mtd: spi: Convert is_locked callback to is_unlocked"). sst26_is_locked() is also changed to sst26_is_unlocked() but the logic remained same. Invert the logic for the flash lock/unlock to work properly. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Reviewed-by: Jan Kiszka Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20221122051833.13306-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/mtd/spi/spi-nor-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 78de3c5281..1ea8363d9f 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1600,7 +1600,7 @@ static int sst26_is_unlocked(struct spi_nor *nor, loff_t ofs, uint64_t len) ofs -= ofs & (SZ_64K - 1); len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len; - return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK); + return !sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK); } static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,