arm: armada-xp: Add basic support for the maxBCM board

The maxBCM board is equipped with the Marvell Armada-XP MV78460 SoC. It
integrates an SPI NOR flash and an Marvell 88E6185 switch.

Signed-off-by: Stefan Roese <sr@denx.de>

arch/arm/Kconfig

@@ -144,6 +144,9 @@ config KIRKWOOD
 config TARGET_DB_MV784MP_GP
 	bool "Support db-mv784mp-gp"
 
+config TARGET_MAXBCM
+	bool "Support maxbcm"
+
 config TARGET_DEVKIT3250
 	bool "Support devkit3250"
 
@@ -652,6 +655,7 @@ source "board/jornada/Kconfig"
 source "board/karo/tx25/Kconfig"
 source "board/logicpd/imx27lite/Kconfig"
 source "board/logicpd/imx31_litekit/Kconfig"
+source "board/maxbcm/Kconfig"
 source "board/mpl/vcma9/Kconfig"
 source "board/olimex/mx23_olinuxino/Kconfig"
 source "board/palmld/Kconfig"

board/maxbcm/Kconfig

@@ -0,0 +1,19 @@
+if TARGET_MAXBCM
+
+config SYS_CPU
+	string
+	default "armv7"
+
+config SYS_BOARD
+	string
+	default "maxbcm"
+
+config SYS_SOC
+	string
+	default "armada-xp"
+
+config SYS_CONFIG_NAME
+	string
+	default "maxbcm"
+
+endif

board/maxbcm/MAINTAINERS

@@ -0,0 +1,6 @@
+MAXBCM BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/maxbcm/
+F:	include/configs/maxbcm.h
+F:	configs/maxbcm_defconfig

board/maxbcm/Makefile

@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= maxbcm.o

board/maxbcm/kwbimage.cfg

@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/maxbcm/binary.0 0000005b 00000068

board/maxbcm/maxbcm.c

@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/mbus.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Base addresses for the external device chip selects */
+#define DEV_CS0_BASE		0xe0000000
+#define DEV_CS1_BASE		0xe1000000
+#define DEV_CS2_BASE		0xe2000000
+#define DEV_CS3_BASE		0xe3000000
+
+/* Needed for dynamic (board-specific) mbus configuration */
+extern struct mvebu_mbus_state mbus_state;
+
+int board_early_init_f(void)
+{
+	/*
+	 * Don't configure MPP (pin multiplexing) and GPIO here,
+	 * its already done in bin_hdr
+	 */
+
+	/*
+	 * Setup some board specific mbus address windows
+	 */
+	mbus_dt_setup_win(&mbus_state, DEV_CS0_BASE, 16 << 20,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0);
+	mbus_dt_setup_win(&mbus_state, DEV_CS1_BASE, 16 << 20,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
+	mbus_dt_setup_win(&mbus_state, DEV_CS2_BASE, 16 << 20,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2);
+	mbus_dt_setup_win(&mbus_state, DEV_CS3_BASE, 16 << 20,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: maxBCM\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E6185 switch */
+void reset_phy(void)
+{
+	u16 devadr = CONFIG_PHY_BASE_ADDR;
+	char *name = "neta0";
+	u16 reg;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* todo: fill this with the real setup / config code */
+
+	printf("88E6185 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */

configs/maxbcm_defconfig

@@ -0,0 +1,2 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MAXBCM=y

include/configs/maxbcm.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_DB_MV7846MP_GP_H
+#define _CONFIG_DB_MV7846MP_GP_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_ARMADA_XP		/* SOC Family Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define	CONFIG_SYS_TEXT_BASE	0x04000000
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#define CONFIG_CMD_TIME
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE		MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED		1000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+#define CONFIG_SPI_FLASH_STMICRO
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
+
+#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
+#define CONFIG_PHY_BASE_ADDR	0x0
+#define CONFIG_SYS_NETA_INTERFACE_TYPE	PHY_INTERFACE_MODE_SGMII
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+#define CONFIG_RESET_PHY_R
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
+#define CONFIG_SYS_ALT_MEMTEST
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#endif /* _CONFIG_DB_MV7846MP_GP_H */