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ram: stm32mp1: add support of STM32MP13x

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Add support for new compatible "st,stm32mp13-ddr" to manage the
DDR sub system (Controller and PHY) in STM32MP13x SOC:
- only one AXI port
- support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2)

The STM32MP15x SOC have 2 AXI ports and 32 bits support.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Patrick Delaunay
2022-05-20 18:24:50 +02:00
parent ae3e2c2bf7
commit a46dce2817
2 changed files with 57 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt
View File

@@ -3,7 +3,8 @@ ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
--------------------
Required properties:
--------------------
- compatible : Should be "st,stm32mp1-ddr"
- compatible : Should be "st,stm32mp1-ddr" for STM32MP15x
Should be "st,stm32mp13-ddr" for STM32MP13x
- reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
- clocks : controller clocks handle
- clock-names : associated controller clock names
@@ -13,6 +14,8 @@ Required properties:
the next attributes are DDR parameters, they are generated by DDR tools
included in STM32 Cube tool
They are required only in SPL, when TFABOOT is not activated.
info attributes:
----------------
- st,mem-name : name for DDR configuration, simple string for information
@@ -24,7 +27,7 @@ controlleur attributes:
-----------------------
- st,ctl-reg : controleur values depending of the DDR type
(DDR3/LPDDR2/LPDDR3)
for STM32MP15x: 25 values are requested in this order
for STM32MP15x and STM32MP13x: 25 values are requested in this order
MSTR
MRCTRL0
MRCTRL1
@@ -53,7 +56,7 @@ controlleur attributes:
- st,ctl-timing : controleur values depending of frequency and timing parameter
of DDR
for STM32MP15x: 12 values are requested in this order
for STM32MP15x and STM32MP13x: 12 values are requested in this order
RFSHTMG
DRAMTMG0
DRAMTMG1
@@ -68,7 +71,7 @@ controlleur attributes:
ODTCFG
- st,ctl-map : controleur values depending of address mapping
for STM32MP15x: 9 values are requested in this order
for STM32MP15x and STM32MP13x: 9 values are requested in this order
ADDRMAP1
ADDRMAP2
ADDRMAP3
@@ -99,6 +102,19 @@ controlleur attributes:
PCFGWQOS0_1
PCFGWQOS1_1
for STM32MP13x: 11 values are requested in this order
SCHED
SCHED1
PERFHPR1
PERFLPR1
PERFWR1
PCFGR_0
PCFGW_0
PCFGQOS0_0
PCFGQOS1_0
PCFGWQOS0_0
PCFGWQOS1_0
phyc attributes:
----------------
- st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
@@ -115,8 +131,19 @@ phyc attributes:
DX2GCR
DX3GCR
for STM32MP13x: 9 values are requested in this order
PGCR
ACIOCR
DXCCR
DSGCR
DCR
ODTCR
ZQ0CR1
DX0GCR
DX1GCR
- st,phy-timing : phy values depending of frequency and timing parameter of DDR
for STM32MP15x: 10 values are requested in this order
for STM32MP15x and STM32MP13x: 10 values are requested in this order
PTR0
PTR1
PTR2
@@ -128,16 +155,18 @@ phyc attributes:
MR2
MR3
for STM32MP13x: 6 values are requested in this order
DX0DLLCR
DX0DQTR
DX0DQSTR
DX1DLLCR
DX1DQTR
DX1DQSTR
Example:
/ {
soc {
u-boot,dm-spl;
ddr: ddr@0x5A003000{
u-boot,dm-spl;
u-boot,dm-pre-reloc;
compatible = "st,stm32mp1-ddr";
reg = <0x5A003000 0x550