From 16bacd5e5f49397d2456be0636c9ea64c621ce56 Mon Sep 17 00:00:00 2001 From: Stefan Chulski Date: Mon, 3 May 2021 08:08:44 +0200 Subject: [PATCH 01/11] phy: introduce 1000BaseX and 2500BaseX modes Signed-off-by: Stefan Chulski Signed-off-by: Stefan Roese --- include/phy_interface.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/phy_interface.h b/include/phy_interface.h index 841ade311e..ebb18ecd40 100644 --- a/include/phy_interface.h +++ b/include/phy_interface.h @@ -25,6 +25,8 @@ typedef enum { PHY_INTERFACE_MODE_RGMII_RXID, PHY_INTERFACE_MODE_RGMII_TXID, PHY_INTERFACE_MODE_RTBI, + PHY_INTERFACE_MODE_1000BASEX, + PHY_INTERFACE_MODE_2500BASEX, PHY_INTERFACE_MODE_XGMII, PHY_INTERFACE_MODE_XAUI, PHY_INTERFACE_MODE_RXAUI, @@ -55,6 +57,8 @@ static const char * const phy_interface_strings[] = { [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", [PHY_INTERFACE_MODE_RTBI] = "rtbi", + [PHY_INTERFACE_MODE_1000BASEX] = "1000base-x", + [PHY_INTERFACE_MODE_2500BASEX] = "2500base-x", [PHY_INTERFACE_MODE_XGMII] = "xgmii", [PHY_INTERFACE_MODE_XAUI] = "xaui", [PHY_INTERFACE_MODE_RXAUI] = "rxaui", From 8d3aa376a9e4b410adf4d45cf529c0c2e748165f Mon Sep 17 00:00:00 2001 From: Stefan Chulski Date: Mon, 3 May 2021 08:08:45 +0200 Subject: [PATCH 02/11] net: mvpp2: add CP115 port1 10G/5G SFI support 1. Differ between Port1 RGMII and SFI modes in Netcomplex config. 2. Remove XPCS config from SFI mode. Port1 doesn't XPCS domain, XPCS config should be removed. Access to Port1 XPCS can cause stall. 3. Add Port1 MPCS configurations. Signed-off-by: Stefan Chulski Signed-off-by: Stefan Roese --- drivers/net/mvpp2.c | 75 ++++++++++----------------------------------- 1 file changed, 17 insertions(+), 58 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 1cf522b8fe..015f5329de 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -520,8 +520,9 @@ do { \ /* Net Complex */ enum mv_netc_topology { MV_NETC_GE_MAC2_SGMII = BIT(0), - MV_NETC_GE_MAC3_SGMII = BIT(1), - MV_NETC_GE_MAC3_RGMII = BIT(2), + MV_NETC_GE_MAC2_RGMII = BIT(1), + MV_NETC_GE_MAC3_SGMII = BIT(2), + MV_NETC_GE_MAC3_RGMII = BIT(3), }; enum mv_netc_phase { @@ -3208,56 +3209,31 @@ static int gop_gpcs_reset(struct mvpp2_port *port, int reset) return 0; } -/* Set the internal mux's to the required PCS in the PI */ -static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes) -{ - u32 val; - int lane; - - switch (num_of_lanes) { - case 1: - lane = 0; - break; - case 2: - lane = 1; - break; - case 4: - lane = 2; - break; - default: - return -1; - } - - /* configure XG MAC mode */ - val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); - val &= ~MVPP22_XPCS_PCSMODE_MASK; - val &= ~MVPP22_XPCS_LANEACTIVE_MASK; - val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS; - writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); - - return 0; -} - static int gop_mpcs_mode(struct mvpp2_port *port) { u32 val; /* configure PCS40G COMMON CONTROL */ - val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL); + val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET + + PCS40G_COMMON_CONTROL); val &= ~FORWARD_ERROR_CORRECTION_MASK; - writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL); + writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET + + PCS40G_COMMON_CONTROL); /* configure PCS CLOCK RESET */ - val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET); + val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET + + PCS_CLOCK_RESET); val &= ~CLK_DIVISION_RATIO_MASK; val |= 1 << CLK_DIVISION_RATIO_OFFS; - writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET); + writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET + + PCS_CLOCK_RESET); val &= ~CLK_DIV_PHASE_SET_MASK; val |= MAC_CLK_RESET_MASK; val |= RX_SD_CLK_RESET_MASK; val |= TX_SD_CLK_RESET_MASK; - writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET); + writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET + + PCS_CLOCK_RESET); return 0; } @@ -3300,22 +3276,6 @@ static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes) return 0; } -/* Set PCS to reset or exit from reset */ -static int gop_xpcs_reset(struct mvpp2_port *port, int reset) -{ - u32 val; - - /* read - modify - write */ - val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); - if (reset) - val &= ~MVPP22_XPCS_PCSRESET; - else - val |= MVPP22_XPCS_PCSRESET; - writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); - - return 0; -} - /* Set the MAC to reset or exit from reset */ static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset) { @@ -3387,14 +3347,10 @@ static int gop_port_init(struct mvpp2_port *port) num_of_act_lanes = 2; mac_num = 0; /* configure PCS */ - gop_xpcs_mode(port, num_of_act_lanes); gop_mpcs_mode(port); /* configure MAC */ gop_xlg_mac_mode_cfg(port, num_of_act_lanes); - /* pcs unreset */ - gop_xpcs_reset(port, 0); - /* mac unreset */ gop_xlg_mac_reset(port, 0); break; @@ -3465,6 +3421,9 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type) if (gop_id == 2) { if (phy_type == PHY_INTERFACE_MODE_SGMII) val |= MV_NETC_GE_MAC2_SGMII; + else if (phy_type == PHY_INTERFACE_MODE_RGMII || + phy_type == PHY_INTERFACE_MODE_RGMII_ID) + val |= MV_NETC_GE_MAC2_RGMII; } if (gop_id == 3) { @@ -3656,7 +3615,7 @@ static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase) if (c & MV_NETC_GE_MAC2_SGMII) gop_netc_mac_to_sgmii(priv, 2, phase); - else + else if (c & MV_NETC_GE_MAC2_RGMII) gop_netc_mac_to_xgmii(priv, 2, phase); if (c & MV_NETC_GE_MAC3_SGMII) { From 8299abc5ff0b5c2403a3f085376247d4cd8c37d1 Mon Sep 17 00:00:00 2001 From: Stefan Chulski Date: Mon, 3 May 2021 08:08:46 +0200 Subject: [PATCH 03/11] net: mvpp2: add 1000BaseX and 2500BaseX ppv2 support Signed-off-by: Stefan Chulski Signed-off-by: Stefan Roese Reviewed-by: Ramon Fried --- drivers/net/mvpp2.c | 117 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 112 insertions(+), 5 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 015f5329de..847007d5b4 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -2880,6 +2880,10 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port) case PHY_INTERFACE_MODE_SGMII: val |= MVPP2_GMAC_INBAND_AN_MASK; break; + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + val &= ~MVPP2_GMAC_INBAND_AN_MASK; + break; case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: val |= MVPP2_GMAC_PORT_RGMII_MASK; @@ -2940,7 +2944,9 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port) else val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; - if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) + if (port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) val |= MVPP2_GMAC_PCS_LB_EN_MASK; else val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; @@ -3051,10 +3057,10 @@ static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port) val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); /* - * Configure GIG MAC to 1000Base-X mode connected to a fiber + * Configure GIG MAC to SGMII mode connected to a fiber * transceiver */ - val |= MVPP2_GMAC_PORT_TYPE_MASK; + val &= ~MVPP2_GMAC_PORT_TYPE_MASK; writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); /* configure AN 0x9268 */ @@ -3106,6 +3112,89 @@ static void gop_gmac_sgmii_cfg(struct mvpp2_port *port) writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); } +static void gop_gmac_2500basex_cfg(struct mvpp2_port *port) +{ + u32 val, thresh; + + /* + * Configure minimal level of the Tx FIFO before the lower part + * starts to read a packet + */ + thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH; + val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); + val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; + val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh); + writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); + + /* Disable bypass of sync module */ + val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); + val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK; + /* configure DP clock select according to mode */ + val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK; + /* configure QSGMII bypass according to mode */ + val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); + + val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); + /* + * Configure GIG MAC to 2500Base-X mode connected to a fiber + * transceiver + */ + val |= MVPP2_GMAC_PORT_TYPE_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); + + /* In 2500BaseX mode, we can't negotiate speed + * and we do not want InBand autoneg + * bypass enabled (link interrupt storm risk + * otherwise). + */ + val = MVPP2_GMAC_EN_PCS_AN | + MVPP2_GMAC_CONFIG_GMII_SPEED | + MVPP2_GMAC_CONFIG_FULL_DUPLEX | + MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG; + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); +} + +static void gop_gmac_1000basex_cfg(struct mvpp2_port *port) +{ + u32 val, thresh; + + /* + * Configure minimal level of the Tx FIFO before the lower part + * starts to read a packet + */ + thresh = MVPP2_SGMII_TX_FIFO_MIN_TH; + val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); + val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; + val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh); + writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); + + /* Disable bypass of sync module */ + val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); + val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK; + /* configure DP clock select according to mode */ + val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK; + /* configure QSGMII bypass according to mode */ + val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); + + val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); + /* configure GIG MAC to 1000BASEX mode */ + val |= MVPP2_GMAC_PORT_TYPE_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); + + /* In 1000BaseX mode, we can't negotiate speed (it's + * only 1000), and we do not want InBand autoneg + * bypass enabled (link interrupt storm risk + * otherwise). + */ + val = MVPP2_GMAC_EN_PCS_AN | + MVPP2_GMAC_CONFIG_GMII_SPEED | + MVPP2_GMAC_CONFIG_FULL_DUPLEX | + MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG; + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); +} + static void gop_gmac_rgmii_cfg(struct mvpp2_port *port) { u32 val, thresh; @@ -3157,6 +3246,12 @@ static int gop_gmac_mode_cfg(struct mvpp2_port *port) gop_gmac_sgmii_cfg(port); break; + case PHY_INTERFACE_MODE_1000BASEX: + gop_gmac_1000basex_cfg(port); + + case PHY_INTERFACE_MODE_2500BASEX: + gop_gmac_2500basex_cfg(port); + case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: gop_gmac_rgmii_cfg(port); @@ -3329,6 +3424,8 @@ static int gop_port_init(struct mvpp2_port *port) break; case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: /* configure PCS */ gop_gpcs_mode_cfg(port, 1); @@ -3386,6 +3483,8 @@ static void gop_port_enable(struct mvpp2_port *port, int enable) case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: if (enable) mvpp2_port_enable(port); else @@ -3419,7 +3518,9 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type) u32 val = 0; if (gop_id == 2) { - if (phy_type == PHY_INTERFACE_MODE_SGMII) + if (phy_type == PHY_INTERFACE_MODE_SGMII || + phy_type == PHY_INTERFACE_MODE_1000BASEX || + phy_type == PHY_INTERFACE_MODE_2500BASEX) val |= MV_NETC_GE_MAC2_SGMII; else if (phy_type == PHY_INTERFACE_MODE_RGMII || phy_type == PHY_INTERFACE_MODE_RGMII_ID) @@ -3427,7 +3528,9 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type) } if (gop_id == 3) { - if (phy_type == PHY_INTERFACE_MODE_SGMII) + if (phy_type == PHY_INTERFACE_MODE_SGMII || + phy_type == PHY_INTERFACE_MODE_1000BASEX || + phy_type == PHY_INTERFACE_MODE_2500BASEX) val |= MV_NETC_GE_MAC3_SGMII; else if (phy_type == PHY_INTERFACE_MODE_RGMII || phy_type == PHY_INTERFACE_MODE_RGMII_ID) @@ -4423,6 +4526,8 @@ static void mvpp2_start_dev(struct mvpp2_port *port) case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: mvpp2_gmac_max_rx_size_set(port); default: break; @@ -5159,6 +5264,8 @@ static int mvpp2_start(struct udevice *dev) case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: mvpp2_port_power_up(port); default: break; From be45eb5064190c79e916cd702910318194f9c8a2 Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Mon, 3 May 2021 08:08:47 +0200 Subject: [PATCH 04/11] net: mvpp2: remove redundant SMI address configuration Because the mvpp2 driver now relies on the PHYLIB and the external MDIO driver, configuring low level SMI bus settings is redundant. Signed-off-by: Marcin Wojtas Reviewed-by: Kostya Porotchkin Reviewed-by: Stefan Chulski Signed-off-by: Stefan Roese Reviewed-by: Ramon Fried --- drivers/net/mvpp2.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 847007d5b4..2043bdf10a 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -5292,14 +5292,6 @@ static int mvpp2_write_hwaddr(struct udevice *dev) return mvpp2_prs_update_mac_da(port, port->dev_addr); } -static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port) -{ - writel(port->phyaddr, port->priv->iface_base + - MVPP22_SMI_PHY_ADDR_REG(port->gop_id)); - - return 0; -} - static int mvpp2_base_probe(struct udevice *dev) { struct mvpp2 *priv = dev_get_priv(dev); @@ -5422,10 +5414,6 @@ static int mvpp2_probe(struct udevice *dev) port->base = priv->iface_base + MVPP22_PORT_BASE + port->gop_id * MVPP22_PORT_OFFSET; - /* Set phy address of the port */ - if (port->phyaddr < PHY_MAX_ADDR) - mvpp22_smi_phy_addr_cfg(port); - /* GoP Init */ gop_port_init(port); } From 08f462dd1eb86a81493e12e2bbb974158cee52b3 Mon Sep 17 00:00:00 2001 From: Stefan Chulski Date: Mon, 3 May 2021 08:08:48 +0200 Subject: [PATCH 05/11] net: mvpp2: Fix 2.5G GMII_SPEED configurations GMII_SPEED should be enabled for 2.5G speed Signed-off-by: Stefan Chulski Reviewed-by: Yan Markman Reviewed-by: Kostya Porotchkin Signed-off-by: Stefan Roese --- drivers/net/mvpp2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 2043bdf10a..ec7cb89a94 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -4445,7 +4445,8 @@ static void mvpp2_link_event(struct mvpp2_port *port) if (phydev->duplex) val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; - if (phydev->speed == SPEED_1000) + if (phydev->speed == SPEED_1000 || + phydev->speed == 2500) val |= MVPP2_GMAC_CONFIG_GMII_SPEED; else if (phydev->speed == SPEED_100) val |= MVPP2_GMAC_CONFIG_MII_SPEED; From 7589be8d3841062d933aa851186a7d3cb60f97b7 Mon Sep 17 00:00:00 2001 From: Ben Peled Date: Mon, 3 May 2021 08:08:49 +0200 Subject: [PATCH 06/11] net: mvpp2: AN Bypass in 1000 and 2500 basex mode Signed-off-by: Ben Peled Reviewed-by: Stefan Chulski Reviewed-by: Kostya Porotchkin Signed-off-by: Stefan Roese --- drivers/net/mvpp2.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index ec7cb89a94..879289452b 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -3148,7 +3148,8 @@ static void gop_gmac_2500basex_cfg(struct mvpp2_port *port) * bypass enabled (link interrupt storm risk * otherwise). */ - val = MVPP2_GMAC_EN_PCS_AN | + val = MVPP2_GMAC_AN_BYPASS_EN | + MVPP2_GMAC_EN_PCS_AN | MVPP2_GMAC_CONFIG_GMII_SPEED | MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG; @@ -3188,7 +3189,8 @@ static void gop_gmac_1000basex_cfg(struct mvpp2_port *port) * bypass enabled (link interrupt storm risk * otherwise). */ - val = MVPP2_GMAC_EN_PCS_AN | + val = MVPP2_GMAC_AN_BYPASS_EN | + MVPP2_GMAC_EN_PCS_AN | MVPP2_GMAC_CONFIG_GMII_SPEED | MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG; From cf51a0d5fce0f040748365aa6f3eb9a5b70884ea Mon Sep 17 00:00:00 2001 From: Ben Peled Date: Mon, 3 May 2021 08:08:50 +0200 Subject: [PATCH 07/11] net: mvpp2: remove unused define MVPP22_SMI_PHY_ADDR_REG Signed-off-by: Ben Peled Reviewed-by: Stefan Chulski Reviewed-by: Kostya Porotchkin Signed-off-by: Stefan Roese Reviewed-by: Ramon Fried --- drivers/net/mvpp2.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 879289452b..61a0ea0894 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -490,9 +490,6 @@ do { \ #define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04) #define MVPP22_SMI_POLLING_EN BIT(10) -#define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \ - (0x4 * (port))) - #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff /* Descriptor ring Macros */ From d757c859c758330bccf460d6c192109fc94b1443 Mon Sep 17 00:00:00 2001 From: Ben Peled Date: Mon, 3 May 2021 08:08:51 +0200 Subject: [PATCH 08/11] net: mvpp2: fix missing switch case break Signed-off-by: Ben Peled Reviewed-by: Stefan Chulski Reviewed-by: Kostya Porotchkin Signed-off-by: Stefan Roese Reviewed-by: Ramon Fried --- drivers/net/mvpp2.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 61a0ea0894..3d920e85ff 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -3247,9 +3247,11 @@ static int gop_gmac_mode_cfg(struct mvpp2_port *port) case PHY_INTERFACE_MODE_1000BASEX: gop_gmac_1000basex_cfg(port); + break; case PHY_INTERFACE_MODE_2500BASEX: gop_gmac_2500basex_cfg(port); + break; case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: From 27844000ef5f6717570789cace60af76f739f564 Mon Sep 17 00:00:00 2001 From: Stefan Chulski Date: Mon, 3 May 2021 08:08:52 +0200 Subject: [PATCH 09/11] net: mvpp2: allow MDIO registration for fixed links Currently, there are 2 valid cases for interface, PHY and mdio relation: - If an interface has PHY handler, it'll call mdio_mii_bus_get_from_phy(), which will register MDIO bus. - If we want to use fixed-link for an interface, PHY handle is not defined in the DTS, and no MDIO is registered. There is a third case, for some boards (with switch), the MDIO is used for switch configuration, but the interface itself uses fixed link. This patch allows this option by checking if fixed-link subnode is defined, in this case, MDIO bus is registers, but the PHY address is set to PHY_MAX_ADDR for this interface, so this interface will not try to access the PHY later on. Signed-off-by: Stefan Chulski Signed-off-by: Stefan Roese --- drivers/net/mvpp2.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 3d920e85ff..c5bfe41281 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -4787,16 +4787,25 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) u32 id; u32 phyaddr = 0; int phy_mode = -1; + int fixed_link = 0; int ret; phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy"); + fixed_link = fdt_subnode_offset(gd->fdt_blob, port_node, "fixed-link"); if (phy_node > 0) { int parent; - phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0); - if (phyaddr < 0) { - dev_err(dev, "could not find phy address\n"); - return -1; + + if (fixed_link != -FDT_ERR_NOTFOUND) { + /* phy_addr is set to invalid value for fixed links */ + phyaddr = PHY_MAX_ADDR; + } else { + phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, + "reg", 0); + if (phyaddr < 0) { + dev_err(dev, "could not find phy address\n"); + return -1; + } } parent = fdt_parent_offset(gd->fdt_blob, phy_node); ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent, From d24efc621c4953eaca3c59da0a9c228354044912 Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Mon, 3 May 2021 08:08:53 +0200 Subject: [PATCH 10/11] net: mvpp2: add explicit sgmii-2500 support Until now the mvpp2 driver used an extra 'phy-speed' DT property in order to differentiate between the SGMII and SGMII @2.5GHz. As there is a dedicated PHY_INTERFACE_MODE_SGMII_2500 flag to mark the latter start using it and drop the custom flag. Signed-off-by: Marcin Wojtas Reviewed-by: Stefan Chulski Reviewed-by: Nadav Haklai Tested-by: Nadav Haklai Signed-off-by: Stefan Roese Reviewed-by: Ramon Fried --- drivers/net/mvpp2.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index c5bfe41281..4c0a7b0a9f 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -976,8 +976,6 @@ struct mvpp2_port { unsigned int duplex; unsigned int speed; - unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */ - struct mvpp2_bm_pool *pool_long; struct mvpp2_bm_pool *pool_short; @@ -2875,6 +2873,7 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port) switch (port->phy_interface) { case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_SGMII_2500: val |= MVPP2_GMAC_INBAND_AN_MASK; break; case PHY_INTERFACE_MODE_1000BASEX: @@ -2942,6 +2941,7 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port) val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; if (port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_SGMII_2500 || port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) val |= MVPP2_GMAC_PCS_LB_EN_MASK; @@ -3239,12 +3239,11 @@ static int gop_gmac_mode_cfg(struct mvpp2_port *port) /* Set TX FIFO thresholds */ switch (port->phy_interface) { case PHY_INTERFACE_MODE_SGMII: - if (port->phy_speed == 2500) - gop_gmac_sgmii2_5_cfg(port); - else - gop_gmac_sgmii_cfg(port); + gop_gmac_sgmii_cfg(port); + break; + case PHY_INTERFACE_MODE_SGMII_2500: + gop_gmac_sgmii2_5_cfg(port); break; - case PHY_INTERFACE_MODE_1000BASEX: gop_gmac_1000basex_cfg(port); break; @@ -3425,6 +3424,7 @@ static int gop_port_init(struct mvpp2_port *port) break; case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: /* configure PCS */ @@ -3484,6 +3484,7 @@ static void gop_port_enable(struct mvpp2_port *port, int enable) case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: if (enable) @@ -3520,6 +3521,7 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type) if (gop_id == 2) { if (phy_type == PHY_INTERFACE_MODE_SGMII || + phy_type == PHY_INTERFACE_MODE_SGMII_2500 || phy_type == PHY_INTERFACE_MODE_1000BASEX || phy_type == PHY_INTERFACE_MODE_2500BASEX) val |= MV_NETC_GE_MAC2_SGMII; @@ -3530,6 +3532,7 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type) if (gop_id == 3) { if (phy_type == PHY_INTERFACE_MODE_SGMII || + phy_type == PHY_INTERFACE_MODE_SGMII_2500 || phy_type == PHY_INTERFACE_MODE_1000BASEX || phy_type == PHY_INTERFACE_MODE_2500BASEX) val |= MV_NETC_GE_MAC3_SGMII; @@ -4528,6 +4531,7 @@ static void mvpp2_start_dev(struct mvpp2_port *port) case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: mvpp2_gmac_max_rx_size_set(port); @@ -4838,15 +4842,6 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) &port->phy_tx_disable_gpio, GPIOD_IS_OUT); #endif - /* - * ToDo: - * Not sure if this DT property "phy-speed" will get accepted, so - * this might change later - */ - /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */ - port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node, - "phy-speed", 1000); - port->id = id; if (port->priv->hw_version == MVPP21) port->first_rxq = port->id * rxq_number; @@ -5275,6 +5270,7 @@ static int mvpp2_start(struct udevice *dev) case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: mvpp2_port_power_up(port); From c350601348b7c3adc958f676c699de66b39ada0e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 27 Apr 2021 11:48:28 +0200 Subject: [PATCH 11/11] arm: mvebu: armada-3720-uDPU.dts: Change back to phy-mode "2500base-x" With commit 8678776df6f5 (arm: mvebu: armada-3720-uDPU: fix PHY mode definition to sgmii-2500) the PHY mode was switch to "sgmii-2500", even when this is functionally incorrect since "2500base-x" was not supported in U-Boot at that time. As this mode is now supported (at least present in the headers), this patch moves back to the orinal version. Signed-off-by: Stefan Roese Cc: Jakov Petrina Cc: Vladimir Vid Cc: Luka Perkov --- arch/arm/dts/armada-3720-uDPU.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts index 4b30f3cea8..4bf6d2eac7 100644 --- a/arch/arm/dts/armada-3720-uDPU.dts +++ b/arch/arm/dts/armada-3720-uDPU.dts @@ -126,14 +126,14 @@ ð0 { pinctrl-0 = <&pcie_pins>; status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; managed = "in-band-status"; phy = <ðphy0>; }; ð1 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; managed = "in-band-status"; phy = <ðphy1>; };