mtd: rpc: Add Renesas RPC Hyperflash driver
Add driver for the RPC block in Hyperflash mode. This driver allows access to a CFI Hyperflash attached to the RPC block and does not support RPC in SPI mode. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut
parent
cf39f3f304
commit
a405a55ba8
@ -40,6 +40,13 @@ config FLASH_PIC32
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This enables access to Microchip PIC32 internal non-CFI flash
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chips through PIC32 Non-Volatile-Memory Controller.
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config RENESAS_RPC_HF
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bool "Renesas RCar Gen3 RPC Hyperflash driver"
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depends on RCAR_GEN3 && MTD
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help
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This enables access to Hyperflash memory through the Renesas
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RCar Gen3 RPC controller.
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endmenu
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source "drivers/mtd/nand/Kconfig"
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@ -20,3 +20,4 @@ obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
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obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o
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obj-$(CONFIG_ST_SMI) += st_smi.o
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obj-$(CONFIG_STM32_FLASH) += stm32_flash.o
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obj-$(CONFIG_RENESAS_RPC_HF) += renesas_rpc_hf.o
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398
drivers/mtd/renesas_rpc_hf.c
Normal file
398
drivers/mtd/renesas_rpc_hf.c
Normal file
@ -0,0 +1,398 @@
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/*
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* Renesas RCar Gen3 RPC Hyperflash driver
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*
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* Copyright (C) 2016 Renesas Electronics Corporation
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* Copyright (C) 2016 Cogent Embedded, Inc.
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* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/of_access.h>
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#include <errno.h>
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#include <fdt_support.h>
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#include <flash.h>
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#include <mtd.h>
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#include <wait_bit.h>
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#include <mtd/cfi_flash.h>
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#define RPC_CMNCR 0x0000 /* R/W */
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#define RPC_CMNCR_MD BIT(31)
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#define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
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#define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
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#define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
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#define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
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#define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \
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RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3))
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#define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
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#define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12)
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#define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14)
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#define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \
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RPC_CMNCR_IO3FV(3))
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#define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0)
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#define RPC_SSLDR 0x0004 /* R/W */
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#define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
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#define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
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#define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
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#define RPC_DRCR 0x000C /* R/W */
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#define RPC_DRCR_SSLN BIT(24)
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#define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16)
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#define RPC_DRCR_RCF BIT(9)
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#define RPC_DRCR_RBE BIT(8)
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#define RPC_DRCR_SSLE BIT(0)
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#define RPC_DRCMR 0x0010 /* R/W */
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#define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16)
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#define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
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#define RPC_DREAR 0x0014 /* R/W */
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#define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16)
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#define RPC_DREAR_EAC(v) (((v) & 0x7) << 0)
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#define RPC_DROPR 0x0018 /* R/W */
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#define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24)
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#define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16)
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#define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8)
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#define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0)
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#define RPC_DRENR 0x001C /* R/W */
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#define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
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#define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28)
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#define RPC_DRENR_ADB(o) (((o) & 0x3) << 24)
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#define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20)
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#define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16)
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#define RPC_DRENR_DME BIT(15)
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#define RPC_DRENR_CDE BIT(14)
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#define RPC_DRENR_OCDE BIT(12)
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#define RPC_DRENR_ADE(v) (((v) & 0xF) << 8)
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#define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4)
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#define RPC_SMCR 0x0020 /* R/W */
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#define RPC_SMCR_SSLKP BIT(8)
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#define RPC_SMCR_SPIRE BIT(2)
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#define RPC_SMCR_SPIWE BIT(1)
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#define RPC_SMCR_SPIE BIT(0)
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#define RPC_SMCMR 0x0024 /* R/W */
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#define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16)
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#define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
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#define RPC_SMADR 0x0028 /* R/W */
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#define RPC_SMOPR 0x002C /* R/W */
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#define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
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#define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
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#define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
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#define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
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#define RPC_SMENR 0x0030 /* R/W */
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#define RPC_SMENR_CDB(o) (((o) & 0x3) << 30)
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#define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28)
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#define RPC_SMENR_ADB(o) (((o) & 0x3) << 24)
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#define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20)
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#define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16)
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#define RPC_SMENR_DME BIT(15)
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#define RPC_SMENR_CDE BIT(14)
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#define RPC_SMENR_OCDE BIT(12)
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#define RPC_SMENR_ADE(v) (((v) & 0xF) << 8)
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#define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4)
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#define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0)
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#define RPC_SMRDR0 0x0038 /* R */
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#define RPC_SMRDR1 0x003C /* R */
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#define RPC_SMWDR0 0x0040 /* R/W */
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#define RPC_SMWDR1 0x0044 /* R/W */
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#define RPC_CMNSR 0x0048 /* R */
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#define RPC_CMNSR_SSLF BIT(1)
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#define RPC_CMNSR_TEND BIT(0)
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#define RPC_DRDMCR 0x0058 /* R/W */
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#define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0)
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#define RPC_DRDRENR 0x005C /* R/W */
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#define RPC_DRDRENR_HYPE (0x5 << 12)
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#define RPC_DRDRENR_ADDRE BIT(8)
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#define RPC_DRDRENR_OPDRE BIT(4)
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#define RPC_DRDRENR_DRDRE BIT(0)
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#define RPC_SMDMCR 0x0060 /* R/W */
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#define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0)
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#define RPC_SMDRENR 0x0064 /* R/W */
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#define RPC_SMDRENR_HYPE (0x5 << 12)
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#define RPC_SMDRENR_ADDRE BIT(8)
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#define RPC_SMDRENR_OPDRE BIT(4)
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#define RPC_SMDRENR_SPIDRE BIT(0)
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#define RPC_PHYCNT 0x007C /* R/W */
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#define RPC_PHYCNT_CAL BIT(31)
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#define PRC_PHYCNT_OCTA_AA BIT(22)
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#define PRC_PHYCNT_OCTA_SA BIT(23)
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#define PRC_PHYCNT_EXDS BIT(21)
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#define RPC_PHYCNT_OCT BIT(20)
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#define RPC_PHYCNT_WBUF2 BIT(4)
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#define RPC_PHYCNT_WBUF BIT(2)
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#define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
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#define RPC_PHYINT 0x0088 /* R/W */
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#define RPC_PHYINT_RSTEN BIT(18)
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#define RPC_PHYINT_WPEN BIT(17)
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#define RPC_PHYINT_INTEN BIT(16)
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#define RPC_PHYINT_RST BIT(2)
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#define RPC_PHYINT_WP BIT(1)
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#define RPC_PHYINT_INT BIT(0)
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#define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */
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#define RPC_WBUF_SIZE 0x100
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static phys_addr_t rpc_base;
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enum rpc_hf_size {
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RPC_HF_SIZE_16BIT = RPC_SMENR_SPIDE(0x8),
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RPC_HF_SIZE_32BIT = RPC_SMENR_SPIDE(0xC),
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RPC_HF_SIZE_64BIT = RPC_SMENR_SPIDE(0xF),
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};
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static int rpc_hf_wait_tend(void)
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{
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void __iomem *reg = (void __iomem *)rpc_base + RPC_CMNSR;
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return wait_for_bit_le32(reg, RPC_CMNSR_TEND, true, 1000, 0);
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}
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static int rpc_hf_mode(bool man)
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{
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int ret;
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ret = rpc_hf_wait_tend();
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if (ret)
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return ret;
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clrsetbits_le32(rpc_base + RPC_PHYCNT,
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RPC_PHYCNT_WBUF | RPC_PHYCNT_WBUF2 |
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RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3),
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RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3));
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clrsetbits_le32(rpc_base + RPC_CMNCR,
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RPC_CMNCR_MD | RPC_CMNCR_BSZ(3),
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RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ |
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(man ? RPC_CMNCR_MD : 0) | RPC_CMNCR_BSZ(1));
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if (man)
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return 0;
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writel(RPC_DRCR_RBURST(0x1F) | RPC_DRCR_RCF | RPC_DRCR_RBE,
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rpc_base + RPC_DRCR);
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writel(RPC_DRCMR_CMD(0xA0), rpc_base + RPC_DRCMR);
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writel(RPC_DRENR_CDB(2) | RPC_DRENR_OCDB(2) | RPC_DRENR_ADB(2) |
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RPC_DRENR_SPIDB(2) | RPC_DRENR_CDE | RPC_DRENR_OCDE |
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RPC_DRENR_ADE(4), rpc_base + RPC_DRENR);
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writel(RPC_DRDMCR_DMCYC(0xE), rpc_base + RPC_DRDMCR);
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writel(RPC_DRDRENR_HYPE | RPC_DRDRENR_ADDRE | RPC_DRDRENR_DRDRE,
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rpc_base + RPC_DRDRENR);
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/* Dummy read */
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readl(rpc_base + RPC_DRCR);
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return 0;
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}
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static int rpc_hf_xfer(void *addr, u64 wdata, u64 *rdata,
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enum rpc_hf_size size, bool write)
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{
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int ret;
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u32 val;
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ret = rpc_hf_mode(1);
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if (ret)
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return ret;
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/* Submit HF address, SMCMR CMD[7] ~= CA Bit# 47 (R/nW) */
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writel(write ? 0 : RPC_SMCMR_CMD(0x80), rpc_base + RPC_SMCMR);
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writel((uintptr_t)addr >> 1, rpc_base + RPC_SMADR);
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writel(0x0, rpc_base + RPC_SMOPR);
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writel(RPC_SMDRENR_HYPE | RPC_SMDRENR_ADDRE | RPC_SMDRENR_SPIDRE,
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rpc_base + RPC_SMDRENR);
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val = RPC_SMENR_CDB(2) | RPC_SMENR_OCDB(2) |
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RPC_SMENR_ADB(2) | RPC_SMENR_SPIDB(2) |
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RPC_SMENR_CDE | RPC_SMENR_OCDE | RPC_SMENR_ADE(4) | size;
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if (write) {
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writel(val, rpc_base + RPC_SMENR);
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if (size == RPC_HF_SIZE_64BIT)
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writeq(cpu_to_be64(wdata), rpc_base + RPC_SMWDR0);
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else
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writel(cpu_to_be32(wdata), rpc_base + RPC_SMWDR0);
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writel(RPC_SMCR_SPIWE | RPC_SMCR_SPIE, rpc_base + RPC_SMCR);
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} else {
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val |= RPC_SMENR_DME;
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writel(RPC_SMDMCR_DMCYC(0xE), rpc_base + RPC_SMDMCR);
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writel(val, rpc_base + RPC_SMENR);
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writel(RPC_SMCR_SPIRE | RPC_SMCR_SPIE, rpc_base + RPC_SMCR);
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ret = rpc_hf_wait_tend();
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if (ret)
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return ret;
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if (size == RPC_HF_SIZE_64BIT)
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*rdata = be64_to_cpu(readq(rpc_base + RPC_SMRDR0));
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else
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*rdata = be32_to_cpu(readl(rpc_base + RPC_SMRDR0));
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}
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return rpc_hf_mode(0);
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}
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static void rpc_hf_write_cmd(void *addr, u64 wdata, enum rpc_hf_size size)
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{
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int ret;
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ret = rpc_hf_xfer(addr, wdata, NULL, size, 1);
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if (ret)
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printf("RPC: Write failed, ret=%i\n", ret);
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}
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static u64 rpc_hf_read_reg(void *addr, enum rpc_hf_size size)
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{
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u64 rdata = 0;
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int ret;
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ret = rpc_hf_xfer(addr, 0, &rdata, size, 0);
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if (ret)
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printf("RPC: Read failed, ret=%i\n", ret);
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return rdata;
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}
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void flash_write8(u8 value, void *addr)
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{
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rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_16BIT);
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}
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void flash_write16(u16 value, void *addr)
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{
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rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_16BIT);
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}
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void flash_write32(u32 value, void *addr)
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{
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rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_32BIT);
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}
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void flash_write64(u64 value, void *addr)
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{
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rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_64BIT);
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}
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u8 flash_read8(void *addr)
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{
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return rpc_hf_read_reg(addr, RPC_HF_SIZE_16BIT);
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}
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u16 flash_read16(void *addr)
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{
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return rpc_hf_read_reg(addr, RPC_HF_SIZE_16BIT);
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}
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u32 flash_read32(void *addr)
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{
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return rpc_hf_read_reg(addr, RPC_HF_SIZE_32BIT);
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}
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u64 flash_read64(void *addr)
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{
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return rpc_hf_read_reg(addr, RPC_HF_SIZE_64BIT);
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}
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static int rpc_hf_bind(struct udevice *parent)
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{
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const void *fdt = gd->fdt_blob;
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ofnode node;
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int ret, off;
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/*
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* Check if there are any SPI NOR child nodes, if so, do NOT bind
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* as this controller will be operated by the QSPI driver instead.
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*/
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dev_for_each_subnode(node, parent) {
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off = ofnode_to_offset(node);
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ret = fdt_node_check_compatible(fdt, off, "spi-flash");
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if (!ret)
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return -ENODEV;
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ret = fdt_node_check_compatible(fdt, off, "jedec,spi-nor");
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if (!ret)
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return -ENODEV;
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}
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return 0;
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}
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static int rpc_hf_probe(struct udevice *dev)
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{
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void *blob = (void *)gd->fdt_blob;
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const fdt32_t *cell;
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int node = dev_of_offset(dev);
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int parent, addrc, sizec, len, ret;
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struct clk clk;
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phys_addr_t flash_base;
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parent = fdt_parent_offset(blob, node);
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fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
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cell = fdt_getprop(blob, node, "reg", &len);
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if (!cell)
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return -ENOENT;
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if (addrc != 2 || sizec != 2)
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return -EINVAL;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0) {
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||||
dev_err(dev, "Failed to get RPC clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_enable(&clk);
|
||||
clk_free(&clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to enable RPC clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
rpc_base = fdt_translate_address(blob, node, cell);
|
||||
flash_base = fdt_translate_address(blob, node, cell + addrc + sizec);
|
||||
|
||||
flash_info[0].dev = dev;
|
||||
flash_info[0].base = flash_base;
|
||||
cfi_flash_num_flash_banks = 1;
|
||||
gd->bd->bi_flashstart = flash_base;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id rpc_hf_ids[] = {
|
||||
{ .compatible = "renesas,rpc" },
|
||||
{}
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rpc_hf) = {
|
||||
.name = "rpc_hf",
|
||||
.id = UCLASS_MTD,
|
||||
.of_match = rpc_hf_ids,
|
||||
.bind = rpc_hf_bind,
|
||||
.probe = rpc_hf_probe,
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user