MIPS: sync processor and register definitions with linux-4.4
Update definitions for processor, registers as well as assemby macros. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Daniel Schwierzeck
parent
23ff8633fd
commit
a3ab2ae7f6
@ -1,8 +1,4 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
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* Copyright (C) 1999 by Silicon Graphics, Inc.
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* Copyright (C) 2001 MIPS Technologies, Inc.
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@ -13,6 +9,8 @@
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* Some of the routines below contain useless nops that will be optimized
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* away by gas in -O mode. These nops are however required to fill delay
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* slots in noreorder mode.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __ASM_ASM_H
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#define __ASM_ASM_H
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@ -33,58 +31,58 @@
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* Not used for the kernel but here seems to be the right place.
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*/
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#ifdef __PIC__
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#define CPRESTORE(register) \
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#define CPRESTORE(register) \
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.cprestore register
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#define CPADD(register) \
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#define CPADD(register) \
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.cpadd register
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#define CPLOAD(register) \
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.cpload register
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#define CPLOAD(register) \
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.cpload register
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#else
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#define CPRESTORE(register)
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#define CPADD(register)
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#define CPLOAD(register)
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#endif
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#define ENTRY(symbol) \
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.globl symbol; \
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.type symbol, @function; \
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.ent symbol, 0; \
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#define ENTRY(symbol) \
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.globl symbol; \
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.type symbol, @function; \
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.ent symbol, 0; \
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symbol:
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/*
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* LEAF - declare leaf routine
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*/
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#define LEAF(symbol) \
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.globl symbol; \
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.align 2; \
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.type symbol, @function; \
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.ent symbol, 0; \
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#define LEAF(symbol) \
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.globl symbol; \
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.align 2; \
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.type symbol, @function; \
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.ent symbol, 0; \
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.section .text.symbol, "x"; \
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symbol: .frame sp, 0, ra
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/*
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* NESTED - declare nested routine entry point
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*/
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#define NESTED(symbol, framesize, rpc) \
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.globl symbol; \
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.align 2; \
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.type symbol, @function; \
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.ent symbol, 0; \
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#define NESTED(symbol, framesize, rpc) \
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.globl symbol; \
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.align 2; \
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.type symbol, @function; \
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.ent symbol, 0; \
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.section .text.symbol, "x"; \
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symbol: .frame sp, framesize, rpc
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/*
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* END - mark end of function
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*/
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#define END(function) \
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.end function; \
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#define END(function) \
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.end function; \
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.size function, .-function
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/*
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* EXPORT - export definition of symbol
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*/
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#define EXPORT(symbol) \
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.globl symbol; \
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.globl symbol; \
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symbol:
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/*
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@ -98,16 +96,16 @@ symbol:
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/*
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* ABS - export absolute symbol
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*/
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#define ABS(symbol,value) \
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.globl symbol; \
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#define ABS(symbol,value) \
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.globl symbol; \
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symbol = value
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#define PANIC(msg) \
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#define PANIC(msg) \
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.set push; \
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.set reorder; \
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PTR_LA a0, 8f; \
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jal panic; \
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9: b 9b; \
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.set reorder; \
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PTR_LA a0, 8f; \
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jal panic; \
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9: b 9b; \
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.set pop; \
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TEXT(msg)
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@ -115,31 +113,31 @@ symbol = value
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* Print formatted string
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*/
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#ifdef CONFIG_PRINTK
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#define PRINT(string) \
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#define PRINT(string) \
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.set push; \
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.set reorder; \
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PTR_LA a0, 8f; \
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jal printk; \
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.set reorder; \
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PTR_LA a0, 8f; \
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jal printk; \
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.set pop; \
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TEXT(string)
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#else
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#define PRINT(string)
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#endif
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#define TEXT(msg) \
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#define TEXT(msg) \
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.pushsection .data; \
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8: .asciiz msg; \
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8: .asciiz msg; \
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.popsection;
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/*
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* Build text tables
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*/
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#define TTABLE(string) \
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#define TTABLE(string) \
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.pushsection .text; \
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.word 1f; \
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.word 1f; \
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.popsection \
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.pushsection .data; \
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1: .asciiz string; \
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1: .asciiz string; \
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.popsection
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/*
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@ -151,21 +149,29 @@ symbol = value
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*/
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#ifdef CONFIG_CPU_HAS_PREFETCH
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#define PREF(hint,addr) \
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#define PREF(hint, addr) \
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.set push; \
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.set mips4; \
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.set arch=r5000; \
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pref hint, addr; \
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.set pop
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#define PREFX(hint,addr) \
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#define PREFE(hint, addr) \
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.set push; \
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.set mips4; \
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.set mips0; \
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.set eva; \
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prefe hint, addr; \
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.set pop
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#define PREFX(hint, addr) \
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.set push; \
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.set arch=r5000; \
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prefx hint, addr; \
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.set pop
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#else /* !CONFIG_CPU_HAS_PREFETCH */
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#define PREF(hint, addr)
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#define PREFE(hint, addr)
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#define PREFX(hint, addr)
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#endif /* !CONFIG_CPU_HAS_PREFETCH */
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@ -174,42 +180,42 @@ symbol = value
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* MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
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*/
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#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
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#define MOVN(rd, rs, rt) \
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#define MOVN(rd, rs, rt) \
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.set push; \
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.set reorder; \
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beqz rt, 9f; \
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move rd, rs; \
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beqz rt, 9f; \
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move rd, rs; \
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.set pop; \
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9:
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#define MOVZ(rd, rs, rt) \
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#define MOVZ(rd, rs, rt) \
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.set push; \
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.set reorder; \
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bnez rt, 9f; \
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move rd, rs; \
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bnez rt, 9f; \
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move rd, rs; \
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.set pop; \
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9:
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#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
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#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
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#define MOVN(rd, rs, rt) \
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#define MOVN(rd, rs, rt) \
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.set push; \
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.set noreorder; \
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bnezl rt, 9f; \
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move rd, rs; \
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bnezl rt, 9f; \
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move rd, rs; \
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.set pop; \
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9:
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#define MOVZ(rd, rs, rt) \
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#define MOVZ(rd, rs, rt) \
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.set push; \
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.set noreorder; \
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beqzl rt, 9f; \
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move rd, rs; \
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beqzl rt, 9f; \
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move rd, rs; \
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.set pop; \
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9:
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#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
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#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
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(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
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#define MOVN(rd, rs, rt) \
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#define MOVN(rd, rs, rt) \
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movn rd, rs, rt
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#define MOVZ(rd, rs, rt) \
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#define MOVZ(rd, rs, rt) \
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movz rd, rs, rt
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#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
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@ -304,6 +310,7 @@ symbol = value
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#define LONG_SUBU subu
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#define LONG_L lw
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#define LONG_S sw
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#define LONG_SP swp
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#define LONG_SLL sll
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#define LONG_SLLV sllv
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#define LONG_SRL srl
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@ -326,6 +333,7 @@ symbol = value
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#define LONG_SUBU dsubu
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#define LONG_L ld
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#define LONG_S sd
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#define LONG_SP sdp
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#define LONG_SLL dsll
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#define LONG_SLLV dsllv
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#define LONG_SRL dsrl
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@ -4,6 +4,8 @@
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* of Coprocessor 0 registers.
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*
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* Copyright (c) 1998 Harald Koerfgen
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __ASM_ISADEP_H
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@ -18,7 +20,7 @@
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* kernel or user mode? (CP0_STATUS)
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*/
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#define KU_MASK 0x08
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#define KU_USER 0x08
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#define KU_USER 0x08
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#define KU_KERN 0x00
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#else
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@ -26,7 +28,7 @@
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* kernel or user mode?
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*/
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#define KU_MASK 0x18
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#define KU_USER 0x10
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#define KU_USER 0x10
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#define KU_KERN 0x00
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#endif
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File diff suppressed because it is too large
Load Diff
@ -1,12 +1,10 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 Waldorf GMBH
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* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
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* Copyright (C) 1996 Paul M. Antoine
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ASM_PROCESSOR_H
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#define _ASM_PROCESSOR_H
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@ -1,35 +1,27 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ASM_PTRACE_H
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#define _ASM_PTRACE_H
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/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
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#define FPR_BASE 32
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#define PC 64
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#define CAUSE 65
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#define BADVADDR 66
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#define MMHI 67
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#define MMLO 68
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#define FPC_CSR 69
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#define FPC_EIR 70
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#define DSP_BASE 71 /* 3 more hi / lo register pairs */
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#define DSP_CONTROL 77
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#define ACX 78
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <asm/isadep.h>
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/*
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* This struct defines the way the registers are stored on the stack during a
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* system call/exception. As usual the registers k0/k1 aren't being saved.
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*
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* If you add a register here, also add it to regoffset_table[] in
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* arch/mips/kernel/ptrace.c.
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*/
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struct pt_regs {
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#ifdef CONFIG_32BIT
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/* Pad bytes for argument save space on the stack. */
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unsigned long pad0[6];
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unsigned long pad0[8];
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#endif
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/* Saved main processor registers. */
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@ -45,34 +37,50 @@ struct pt_regs {
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unsigned long cp0_badvaddr;
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unsigned long cp0_cause;
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unsigned long cp0_epc;
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#ifdef CONFIG_MIPS_MT_SMTC
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unsigned long cp0_tcstatus;
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#endif /* CONFIG_MIPS_MT_SMTC */
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} __attribute__ ((aligned (8)));
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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unsigned long long mpl[6]; /* MTM{0-5} */
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unsigned long long mtp[6]; /* MTP{0-5} */
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#endif
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unsigned long __last[0];
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} __aligned(8);
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/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
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#define PTRACE_GETREGS 12
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#define PTRACE_SETREGS 13
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#define PTRACE_GETFPREGS 14
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#define PTRACE_SETFPREGS 15
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/* #define PTRACE_GETFPXREGS 18 */
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/* #define PTRACE_SETFPXREGS 19 */
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static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
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{
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return regs->regs[31];
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}
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#define PTRACE_OLDSETOPTIONS 21
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/*
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* Don't use asm-generic/ptrace.h it defines FP accessors that don't make
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* sense on MIPS. We rather want an error if they get invoked.
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*/
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#define PTRACE_GET_THREAD_AREA 25
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#define PTRACE_SET_THREAD_AREA 26
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static inline void instruction_pointer_set(struct pt_regs *regs,
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unsigned long val)
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{
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regs->cp0_epc = val;
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}
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/* Calls to trace a 64bit program from a 32bit program. */
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#define PTRACE_PEEKTEXT_3264 0xc0
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#define PTRACE_PEEKDATA_3264 0xc1
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#define PTRACE_POKETEXT_3264 0xc2
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#define PTRACE_POKEDATA_3264 0xc3
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#define PTRACE_GET_THREAD_AREA_3264 0xc4
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/* Query offset/name of register from its name/offset */
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extern int regs_query_register_offset(const char *name);
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#define MAX_REG_OFFSET (offsetof(struct pt_regs, __last))
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#ifdef __KERNEL__
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/**
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* regs_get_register() - get register value from its offset
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* @regs: pt_regs from which register value is gotten.
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* @offset: offset number of the register.
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*
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* regs_get_register returns the value of a register. The @offset is the
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* offset of the register in struct pt_regs address which specified by @regs.
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* If @offset is bigger than MAX_REG_OFFSET, this returns 0.
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*/
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static inline unsigned long regs_get_register(struct pt_regs *regs,
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unsigned int offset)
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{
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if (unlikely(offset > MAX_REG_OFFSET))
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return 0;
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#include <asm/isadep.h>
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return *(unsigned long *)((unsigned long)regs + offset);
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}
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/*
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* Does the process account for user or for system time?
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@ -82,6 +90,17 @@ struct pt_regs {
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#define instruction_pointer(regs) ((regs)->cp0_epc)
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#define profile_pc(regs) instruction_pointer(regs)
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#endif
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/* Helpers for working with the user stack pointer */
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static inline unsigned long user_stack_pointer(struct pt_regs *regs)
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{
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return regs->regs[29];
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}
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static inline void user_stack_pointer_set(struct pt_regs *regs,
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unsigned long val)
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{
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regs->regs[29] = val;
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}
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#endif /* _ASM_PTRACE_H */
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@ -1,11 +1,11 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
|
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* License. See the file "COPYING" in the main directory of this archive
|
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* for more details.
|
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*
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* Copyright (C) 1985 MIPS Computer Systems, Inc.
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* Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
|
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* Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
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* Copyright (C) 2011 Wind River Systems,
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* written by Ralf Baechle <ralf@linux-mips.org>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ASM_REGDEF_H
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#define _ASM_REGDEF_H
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@ -30,9 +30,13 @@
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#define t2 $10
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#define t3 $11
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#define t4 $12
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#define ta0 $12
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#define t5 $13
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#define ta1 $13
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#define t6 $14
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#define ta2 $14
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#define t7 $15
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#define ta3 $15
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#define s0 $16 /* callee saved */
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#define s1 $17
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#define s2 $18
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@ -27,7 +27,7 @@ static inline unsigned long icache_line_size(void)
|
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{
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unsigned long conf1, il;
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conf1 = read_c0_config1();
|
||||
il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT;
|
||||
il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
|
||||
if (!il)
|
||||
return 0;
|
||||
return 2 << il;
|
||||
@ -37,7 +37,7 @@ static inline unsigned long dcache_line_size(void)
|
||||
{
|
||||
unsigned long conf1, dl;
|
||||
conf1 = read_c0_config1();
|
||||
dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT;
|
||||
dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
|
||||
if (!dl)
|
||||
return 0;
|
||||
return 2 << dl;
|
||||
|
||||
@ -54,24 +54,24 @@
|
||||
mfc0 $1, CP0_CONFIG, 1
|
||||
|
||||
/* detect line size */
|
||||
srl \line_sz, $1, \off + MIPS_CONF1_DL_SHIFT - MIPS_CONF1_DA_SHIFT
|
||||
andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
|
||||
srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
|
||||
andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
|
||||
move \sz, zero
|
||||
beqz \line_sz, 10f
|
||||
li \sz, 2
|
||||
sllv \line_sz, \sz, \line_sz
|
||||
|
||||
/* detect associativity */
|
||||
srl \sz, $1, \off + MIPS_CONF1_DA_SHIFT - MIPS_CONF1_DA_SHIFT
|
||||
andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
|
||||
srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
|
||||
andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF)
|
||||
addi \sz, \sz, 1
|
||||
|
||||
/* sz *= line_sz */
|
||||
mul \sz, \sz, \line_sz
|
||||
|
||||
/* detect log32(sets) */
|
||||
srl $1, $1, \off + MIPS_CONF1_DS_SHIFT - MIPS_CONF1_DA_SHIFT
|
||||
andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
|
||||
srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF
|
||||
andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHF)
|
||||
addiu $1, $1, 1
|
||||
andi $1, $1, 0x7
|
||||
|
||||
@ -103,14 +103,14 @@ LEAF(mips_cache_reset)
|
||||
li t2, CONFIG_SYS_ICACHE_SIZE
|
||||
li t8, CONFIG_SYS_CACHELINE_SIZE
|
||||
#else
|
||||
l1_info t2, t8, MIPS_CONF1_IA_SHIFT
|
||||
l1_info t2, t8, MIPS_CONF1_IA_SHF
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_DCACHE_SIZE
|
||||
li t3, CONFIG_SYS_DCACHE_SIZE
|
||||
li t9, CONFIG_SYS_CACHELINE_SIZE
|
||||
#else
|
||||
l1_info t3, t9, MIPS_CONF1_DA_SHIFT
|
||||
l1_info t3, t9, MIPS_CONF1_DA_SHF
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
|
||||
|
||||
Loading…
Reference in New Issue
Block a user