Update for NC650 board. Add NC650 based CP850 configuration.
Signed-off-by: dzu@denx.de <dzu@denx.de>
This commit is contained in:
dzu@denx.de
Detlev Zundel
parent
8419c01304
commit
a367d42640
@ -2,6 +2,11 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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* Update for NC650 board:
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- Support rev1 and rev2 hardware
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- adapt to new NAND layer
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- add CP850 configuration based on NC650
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* MPC5200: enable snooping of DMA transactions on XLB even if no PCI
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is configured; othrwise DMA accesses aren't cache coherent which
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causes for example USB to fail.
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17
Makefile
17
Makefile
@ -633,8 +633,21 @@ NETTA2_config: unconfig
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}
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@./mkconfig -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2
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NC650_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8xx nc650
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NC650_Rev1_config \
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NC650_Rev2_config \
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CP850_config: unconfig
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@ >include/config.h
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@[ -z "$(findstring CP850,$@)" ] || \
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{ echo "#define CONFIG_CP850 1" >>include/config.h ; \
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echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \
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}
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@[ -z "$(findstring Rev1,$@)" ] || \
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{ echo "#define CONFIG_IDS852_REV1 1" >>include/config.h ; \
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}
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@[ -z "$(findstring Rev2,$@)" ] || \
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{ echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \
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}
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@./mkconfig -a NC650 ppc mpc8xx nc650
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NX823_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8xx nx823
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@ -1,4 +1,5 @@
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#
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# (C) Copyright 2006 Detlev Zundel, dzu@denx.de
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# (C) Copyright 2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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@ -25,7 +26,7 @@ include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o
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OBJS = $(BOARD).o nand.o flash.o
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$(LIB): .depend $(OBJS)
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$(AR) crv $@ $(OBJS)
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@ -1,4 +1,5 @@
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#
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# (C) Copyright 2006 Detlev Zundel, dzu@denx.de
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# (C) Copyright 2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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@ -26,3 +27,4 @@
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#
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TEXT_BASE = 0x40700000
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BOARDLIBS = drivers/nand/libnand.a
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@ -1,4 +1,5 @@
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/*
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* (C) Copyright 2006 Detlev Zundel, dzu@denx.de
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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@ -108,7 +109,16 @@ const uint nand_flash_table[] = {
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int checkboard (void)
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{
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puts ("Board: NC650\n");
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#if !defined(CONFIG_CP850)
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puts ("Board: NC650");
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#else
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puts ("Board: CP850");
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#endif
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#if defined(CONFIG_IDS852_REV1)
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puts (" with IDS852 rev 1 module\n");
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#elif defined(CONFIG_IDS852_REV2)
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puts (" with IDS852 rev 2 module\n");
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#endif
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return 0;
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}
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@ -241,13 +251,61 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
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return (get_ram_size(base, maxsize));
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}
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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void nand_init(void)
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#if defined(CONFIG_CP850)
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#define DPRAM_VARNAME "KP850DIP"
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#define PARAM_ADDR 0x7C0
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#define NAME_ADDR 0x7F8
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#define BOARD_NAME "KP01"
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#define DEFAULT_LB "241111"
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int misc_init_r(void)
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{
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extern unsigned long nand_probe(unsigned long physadr);
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int iCompatMode = 0;
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char *pParam = NULL;
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char *envlb;
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/*
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First byte in CPLD read address space signals compatibility mode
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0 - cp850
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1 - kp852
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*/
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pParam = (char*)(CFG_CPLD_BASE);
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if( *pParam != 0)
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iCompatMode = 1;
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if ( iCompatMode != 0) {
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/*
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In KP852 compatibility mode we have to write to
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DPRAM as early as possible the binary coded
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line config and board name.
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The line config is derived from the environment
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variable DPRAM_VARNAME by converting from ASCII
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to binary per character.
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*/
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if ( (envlb = getenv ( DPRAM_VARNAME )) == 0) {
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setenv( DPRAM_VARNAME, DEFAULT_LB);
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envlb = DEFAULT_LB;
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}
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/* Status string */
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printf("Mode: KP852(LB=%s)\n", envlb);
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unsigned long totlen = nand_probe(CFG_NAND_BASE);
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/* copy appl init */
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pParam = (char*)(DPRAM_BASE_ADDR + PARAM_ADDR);
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while (*envlb) {
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*(pParam++) = *(envlb++) - '0';
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}
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*pParam = '\0';
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printf ("%4lu MB\n", totlen >> 20);
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/* copy board id */
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pParam = (char*)(DPRAM_BASE_ADDR + NAME_ADDR);
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strcpy( pParam, BOARD_NAME);
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} else {
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puts("Mode: CP850\n");
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}
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return 0;
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}
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#endif
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@ -1,4 +1,5 @@
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/*
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* (C) Copyright 2006 Detlev Zundel, dzu@denx.de
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* (C) Copyright 2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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@ -65,6 +66,11 @@
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#define CFG_8XX_XIN CONFIG_8xx_OSCLK
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_AUTOBOOT_KEYED
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#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d seconds...\n"
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#define CONFIG_AUTOBOOT_DELAY_STR "ids"
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#define CONFIG_BOOT_RETRY_TIME 900
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#define CONFIG_BOOT_RETRY_MIN 30
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#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
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@ -75,7 +81,7 @@
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
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"bootm"
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_WATCHDOG /* watchdog enabled */
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#undef CONFIG_STATUS_LED /* Status LED disabled */
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@ -96,12 +102,26 @@
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#if defined(CONFIG_IDS852_REV1)
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#define SCL 0x1000 /* PA 3 */
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#define SDA 0x2000 /* PA 2 */
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#define __I2C_DIR immr->im_ioport.iop_padir
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#define __I2C_DAT immr->im_ioport.iop_padat
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#define __I2C_PAR immr->im_ioport.iop_papar
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#elif defined(CONFIG_IDS852_REV2)
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#define SCL 0x0002 /* PB 30 */
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#define SDA 0x0001 /* PB 31 */
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#define __I2C_PAR immr->im_cpm.cp_pbpar
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#define __I2C_DIR immr->im_cpm.cp_pbdir
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#define __I2C_DAT immr->im_cpm.cp_pbdat
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#endif
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#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \
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__I2C_DIR |= (SDA|SCL); }
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#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
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@ -229,17 +249,6 @@
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#define ADDR_COLUMN 1
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#define NAND_NO_RB
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#define NAND_WAIT_READY(nand) udelay(12)
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#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND(d, adr + 2)
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#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND(d, adr + 1)
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#define WRITE_NAND(d, adr) (*(volatile uint8_t *)(adr) = (uint8_t)(d))
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#define READ_NAND(adr) (*(volatile uint8_t *)(adr))
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#define NAND_DISABLE_CE(nand) /* nop */
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#define NAND_ENABLE_CE(nand) /* nop */
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#define NAND_CTL_CLRALE(nandptr) /* nop */
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#define NAND_CTL_SETALE(nandptr) /* nop */
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#define NAND_CTL_CLRCLE(nandptr) /* nop */
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#define NAND_CTL_SETCLE(nandptr) /* nop */
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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@ -312,7 +321,8 @@
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
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/*
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* BR2 and OR2 (NAND Flash) - now addressed through UPMB
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* BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1
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* rev2 only uses the chipselect
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*/
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#define CFG_NAND_BASE 0x50000000
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#define CFG_NAND_SIZE 0x04000000
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@ -337,6 +347,18 @@
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#define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
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#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
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/*
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* BR4 and OR4 (CPLD)
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*/
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#define CFG_CPLD_BASE 0x80000000 /* CPLD */
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#define CFG_CPLD_SIZE 0x10000 /* only 16 used */
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#define CFG_OR_TIMING_CPLD (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
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OR_SCY_1_CLK)
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#define CFG_BR4_PRELIM ((CFG_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
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#define CFG_OR4_PRELIM (((-CFG_CPLD_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_CPLD)
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/*
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* BR5 and OR5 (SRAM)
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*/
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@ -349,6 +371,16 @@
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#define CFG_BR5_PRELIM ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
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#define CFG_OR5_PRELIM (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)
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#if defined(CONFIG_CP850)
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/*
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* BR6 and OR6 (DPRAM) - only on CP850
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*/
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#define CFG_OR6_PRELIM 0xffff8170
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#define CFG_BR6_PRELIM 0xa0000401
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#define DPRAM_BASE_ADDR 0xa0000000
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#define CONFIG_MISC_INIT_R 1
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#endif
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/*
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* 4096 Rows from SDRAM example configuration
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@ -413,14 +445,12 @@
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#define CONFIG_JFFS2_PART_OFFSET 0x00000000
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/* mtdparts command line support */
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/*
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#define CONFIG_JFFS2_CMDLINE
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#define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand"
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#define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
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"2560k(cramfs1),2560k(cramfs2)," \
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"256k(u-boot),256k(env);" \
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"nc650-nand:4m(nand1),28m(nand2)"
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*/
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"4m(cramfs1),1m(cramfs2)," \
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"256k(u-boot),128k(env);" \
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"nc650-nand:4m(jffs1),28m(jffs2)"
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#endif /* __CONFIG_H */
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