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global: Move remaining CONFIG_*SRIO_* to CFG_*

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The rest of the unmigrated CONFIG symbols in the SRIO namespace do not
easily transition to Kconfig. In many cases they likely should come from
the device tree instead. Move these out of CONFIG namespace and in to
CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini 2022-11-16 13:10:40 -05:00
parent 97396cc9ce
commit a322afc9f9
10 changed files with 146 additions and 146 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
arch/powerpc/cpu/mpc8xxx/law.c
View File

@ -309,42 +309,42 @@ void init_laws(void)
*/ */
switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) { switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
case 0x0: /* boot from PCIE1 */ case 0x0: /* boot from PCIE1 */
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_1); LAW_TRGT_IF_PCIE_1);
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M, LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_1); LAW_TRGT_IF_PCIE_1);
break; break;
case 0x1: /* boot from PCIE2 */ case 0x1: /* boot from PCIE2 */
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_2); LAW_TRGT_IF_PCIE_2);
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M, LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_2); LAW_TRGT_IF_PCIE_2);
break; break;
case 0x2: /* boot from PCIE3 */ case 0x2: /* boot from PCIE3 */
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_3); LAW_TRGT_IF_PCIE_3);
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M, LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_3); LAW_TRGT_IF_PCIE_3);
break; break;
case 0x8: /* boot from SRIO1 */ case 0x8: /* boot from SRIO1 */
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_SIZE_1M,
LAW_TRGT_IF_RIO_1); LAW_TRGT_IF_RIO_1);
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M, LAW_SIZE_1M,
LAW_TRGT_IF_RIO_1); LAW_TRGT_IF_RIO_1);
break; break;
case 0x9: /* boot from SRIO2 */ case 0x9: /* boot from SRIO2 */
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_SIZE_1M,
LAW_TRGT_IF_RIO_2); LAW_TRGT_IF_RIO_2);
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M, LAW_SIZE_1M,
LAW_TRGT_IF_RIO_2); LAW_TRGT_IF_RIO_2);
break; break;

72
arch/powerpc/cpu/mpc8xxx/srio.c
View File

@ -240,8 +240,8 @@ void srio_init(void)
devdisr = &gur->devdisr; devdisr = &gur->devdisr;
#endif #endif
if (is_serdes_configured(SRIO1)) { if (is_serdes_configured(SRIO1)) {
set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS, set_next_law(CFG_SYS_SRIO1_MEM_PHYS,
law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE), law_size_bits(CFG_SYS_SRIO1_MEM_SIZE),
LAW_TRGT_IF_RIO_1); LAW_TRGT_IF_RIO_1);
srio1_used = 1; srio1_used = 1;
#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
@ -256,8 +256,8 @@ void srio_init(void)
#ifdef CONFIG_SRIO2 #ifdef CONFIG_SRIO2
if (is_serdes_configured(SRIO2)) { if (is_serdes_configured(SRIO2)) {
set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS, set_next_law(CFG_SYS_SRIO2_MEM_PHYS,
law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE), law_size_bits(CFG_SYS_SRIO2_MEM_SIZE),
LAW_TRGT_IF_RIO_2); LAW_TRGT_IF_RIO_2);
srio2_used = 1; srio2_used = 1;
#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
@ -301,44 +301,44 @@ void srio_boot_master(int port)
/* configure inbound window for slave's u-boot image */ /* configure inbound window for slave's u-boot image */
debug("SRIOBOOT - MASTER: Inbound window for slave's image; " debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); CFG_SRIO_PCIE_BOOT_IMAGE_SIZE);
out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar, out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar, out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12); CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar, out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
SRIO_IB_ATMU_AR SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); | atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE));
/* configure inbound window for slave's u-boot image */ /* configure inbound window for slave's u-boot image */
debug("SRIOBOOT - MASTER: Inbound window for slave's image; " debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); CFG_SRIO_PCIE_BOOT_IMAGE_SIZE);
out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar, out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar, out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12); CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar, out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar,
SRIO_IB_ATMU_AR SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); | atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE));
/* configure inbound window for slave's ucode and ENV */ /* configure inbound window for slave's ucode and ENV */
debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; " debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, (u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, (u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar, out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar,
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12); CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar, out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar,
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12); CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar, out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar,
SRIO_IB_ATMU_AR SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)); | atmu_size_mask(CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
} }
void srio_boot_master_release_slave(int port) void srio_boot_master_release_slave(int port)
@ -368,11 +368,11 @@ void srio_boot_master_release_slave(int port)
if (port - 1) if (port - 1)
out_be32((void *)&srio->atmu.port[port - 1] out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowbar, .outbw[1].rowbar,
CONFIG_SYS_SRIO2_MEM_PHYS >> 12); CFG_SYS_SRIO2_MEM_PHYS >> 12);
else else
out_be32((void *)&srio->atmu.port[port - 1] out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowbar, .outbw[1].rowbar,
CONFIG_SYS_SRIO1_MEM_PHYS >> 12); CFG_SYS_SRIO1_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1] out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowar, .outbw[1].rowar,
SRIO_OB_ATMU_AR_MAINT SRIO_OB_ATMU_AR_MAINT
@ -390,12 +390,12 @@ void srio_boot_master_release_slave(int port)
if (port - 1) if (port - 1)
out_be32((void *)&srio->atmu.port[port - 1] out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowbar, .outbw[2].rowbar,
(CONFIG_SYS_SRIO2_MEM_PHYS (CFG_SYS_SRIO2_MEM_PHYS
+ SRIO_MAINT_WIN_SIZE) >> 12); + SRIO_MAINT_WIN_SIZE) >> 12);
else else
out_be32((void *)&srio->atmu.port[port - 1] out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowbar, .outbw[2].rowbar,
(CONFIG_SYS_SRIO1_MEM_PHYS (CFG_SYS_SRIO1_MEM_PHYS
+ SRIO_MAINT_WIN_SIZE) >> 12); + SRIO_MAINT_WIN_SIZE) >> 12);
out_be32((void *)&srio->atmu.port[port - 1] out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowar, .outbw[2].rowar,
@ -407,10 +407,10 @@ void srio_boot_master_release_slave(int port)
* by the maint-outbound window * by the maint-outbound window
*/ */
if (port - 1) { if (port - 1) {
out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
+ SRIO_LCSBA1CSR_OFFSET, + SRIO_LCSBA1CSR_OFFSET,
SRIO_LCSBA1CSR); SRIO_LCSBA1CSR);
while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT while (in_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
+ SRIO_LCSBA1CSR_OFFSET) + SRIO_LCSBA1CSR_OFFSET)
!= SRIO_LCSBA1CSR) != SRIO_LCSBA1CSR)
; ;
@ -418,15 +418,15 @@ void srio_boot_master_release_slave(int port)
* And then set the BRR register * And then set the BRR register
* to release slave core * to release slave core
*/ */
out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
+ SRIO_MAINT_WIN_SIZE + SRIO_MAINT_WIN_SIZE
+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, + CFG_SRIO_PCIE_BOOT_BRR_OFFSET,
CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); CFG_SRIO_PCIE_BOOT_RELEASE_MASK);
} else { } else {
out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
+ SRIO_LCSBA1CSR_OFFSET, + SRIO_LCSBA1CSR_OFFSET,
SRIO_LCSBA1CSR); SRIO_LCSBA1CSR);
while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT while (in_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
+ SRIO_LCSBA1CSR_OFFSET) + SRIO_LCSBA1CSR_OFFSET)
!= SRIO_LCSBA1CSR) != SRIO_LCSBA1CSR)
; ;
@ -434,10 +434,10 @@ void srio_boot_master_release_slave(int port)
* And then set the BRR register * And then set the BRR register
* to release slave core * to release slave core
*/ */
out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
+ SRIO_MAINT_WIN_SIZE + SRIO_MAINT_WIN_SIZE
+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, + CFG_SRIO_PCIE_BOOT_BRR_OFFSET,
CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); CFG_SRIO_PCIE_BOOT_RELEASE_MASK);
} }
debug("SRIOBOOT - MASTER: " debug("SRIOBOOT - MASTER: "
"Release slave successfully! Now the slave should start up!\n"); "Release slave successfully! Now the slave should start up!\n");

8
board/freescale/common/p_corenet/tlb.c
View File

@ -69,8 +69,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff00000, it covered the 0xfffff000. * space is at 0xfff00000, it covered the 0xfffff000.
*/ */
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1), 0, 0, BOOKE_PAGESZ_1M, 1),
#else #else
@ -150,8 +150,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
* fetching ucode and ENV from master * fetching ucode and ENV from master
*/ */
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 17, BOOKE_PAGESZ_1M, 1), 0, 17, BOOKE_PAGESZ_1M, 1),
#endif #endif

8
board/freescale/t208xqds/tlb.c
View File

@ -43,8 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff00000, it covered the 0xfffff000. * space is at 0xfff00000, it covered the 0xfffff000.
*/ */
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1), 0, 0, BOOKE_PAGESZ_1M, 1),
#else #else
@ -136,8 +136,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
* fetching ucode and ENV from master * fetching ucode and ENV from master
*/ */
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 18, BOOKE_PAGESZ_1M, 1), 0, 18, BOOKE_PAGESZ_1M, 1),
#endif #endif

8
board/freescale/t208xrdb/tlb.c
View File

@ -43,8 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff00000, it covered the 0xfffff000. * space is at 0xfff00000, it covered the 0xfffff000.
*/ */
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1), 0, 0, BOOKE_PAGESZ_1M, 1),
#else #else
@ -136,8 +136,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
* fetching ucode and ENV from master * fetching ucode and ENV from master
*/ */
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 18, BOOKE_PAGESZ_1M, 1), 0, 18, BOOKE_PAGESZ_1M, 1),
#endif #endif

8
include/configs/MPC8548CDS.h
View File

@ -282,13 +282,13 @@
/* /*
* RapidIO MMU * RapidIO MMU
*/ */
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 #define CFG_SYS_SRIO1_MEM_VIRT 0xc0000000
#ifdef CONFIG_PHYS_64BIT #ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull #define CFG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
#else #else
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 #define CFG_SYS_SRIO1_MEM_PHYS 0xc0000000
#endif #endif
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#if defined(CONFIG_TSEC_ENET) #if defined(CONFIG_TSEC_ENET)

46
include/configs/P2041RDB.h
View File

@ -18,9 +18,9 @@
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */ /* Set 1M boot space */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif #endif
@ -173,49 +173,49 @@
/* /*
* RapidIO * RapidIO
*/ */
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 #define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT #ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
#else #else
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 #define CFG_SYS_SRIO1_MEM_PHYS 0xa0000000
#endif #endif
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ #define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 #define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000
#ifdef CONFIG_PHYS_64BIT #ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull #define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
#else #else
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 #define CFG_SYS_SRIO2_MEM_PHYS 0xb0000000
#endif #endif
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ #define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/* /*
* for slave u-boot IMAGE instored in master memory space, * for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE * PHYS must be aligned based on the SIZE
*/ */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/* /*
* for slave UCODE and ENV instored in master memory space, * for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE * PHYS must be aligned based on the SIZE
*/ */
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/ /* slave core release by master*/
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/* /*
* SRIO_PCIE_BOOT - SLAVE * SRIO_PCIE_BOOT - SLAVE
*/ */
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif #endif
/* /*

38
include/configs/T102xRDB.h
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@ -53,40 +53,40 @@
* for slave u-boot IMAGE instored in master memory space, * for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE * PHYS must be aligned based on the SIZE
*/ */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
#ifdef CONFIG_PHYS_64BIT #ifdef CONFIG_PHYS_64BIT
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
#else #else
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
#endif #endif
/* /*
* for slave UCODE and ENV instored in master memory space, * for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE * PHYS must be aligned based on the SIZE
*/ */
#ifdef CONFIG_PHYS_64BIT #ifdef CONFIG_PHYS_64BIT
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#else #else
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
#endif #endif
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/ /* slave core release by master*/
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/* PCIe Boot - Slave */ /* PCIe Boot - Slave */
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
/* Set 1M boot space for PCIe boot */ /* Set 1M boot space for PCIe boot */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif #endif

42
include/configs/T208xQDS.h
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@ -49,9 +49,9 @@
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */ /* Set 1M boot space */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif #endif
@ -295,39 +295,39 @@
/* /*
* RapidIO * RapidIO
*/ */
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 #define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ #define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 #define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull #define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ #define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/* /*
* for slave u-boot IMAGE instored in master memory space, * for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE * PHYS must be aligned based on the SIZE
*/ */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/* /*
* for slave UCODE and ENV instored in master memory space, * for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE * PHYS must be aligned based on the SIZE
*/ */
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/ /* slave core release by master*/
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/* /*
* SRIO_PCIE_BOOT - SLAVE * SRIO_PCIE_BOOT - SLAVE
*/ */
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif #endif
/* /*

42
include/configs/T208xRDB.h
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@ -49,9 +49,9 @@
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */ /* Set 1M boot space */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif #endif
@ -254,39 +254,39 @@
/* /*
* RapidIO * RapidIO
*/ */
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 #define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ #define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 #define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull #define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ #define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/* /*
* for slave u-boot IMAGE instored in master memory space, * for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE * PHYS must be aligned based on the SIZE
*/ */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/* /*
* for slave UCODE and ENV instored in master memory space, * for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE * PHYS must be aligned based on the SIZE
*/ */
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/ /* slave core release by master*/
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/* /*
* SRIO_PCIE_BOOT - SLAVE * SRIO_PCIE_BOOT - SLAVE
*/ */
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif #endif
/* /*