* Make sure to use a bus clock divider of 2 only when running TQM8xxM
modules at CPU clock frequencies above 66 MHz. * Optimize flash programming speed for LWMON (by another 100% :-)
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wdenk
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@ -2,6 +2,11 @@
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Changes since U-Boot 1.0.1:
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======================================================================
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* Make sure to use a bus clock divider of 2 only when running TQM8xxM
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modules at CPU clock frequencies above 66 MHz.
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* Optimize flash programming speed for LWMON (by another 100% :-)
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* Patch by Jian Zhang, 3 Feb 2004:
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- Changed the incorrect FAT12BUFSIZE
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- data_begin in fsdata can be negative. Changed it to be short.
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@ -64,18 +64,18 @@ static __inline__ void set_msr(unsigned long msr)
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* These strange values for the timing interval and prescaling are used
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* because the formula for the CPU clock is:
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*
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* CPU clock = count * (177 * (8192 / 58))
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* CPU clock = count * (177 * (8192 / 58))
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*
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* = count * 24999.7241
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* = count * 24999.7241
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*
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* which is very close to
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* which is very close to
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*
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* = count * 25000
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* = count * 25000
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*
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* Since the count gives the CPU clock divided by 25000, we can get
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* the CPU clock rounded to the nearest 0.1 MHz by
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*
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* CPU clock = ((count + 2) / 4) * 100000;
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* CPU clock = ((count + 2) / 4) * 100000;
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*
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* The rounding is important since the measurement is sometimes going
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* to be high or low by 0.025 MHz, depending on exactly how the clocks
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@ -112,8 +112,8 @@ unsigned long measure_gclk(void)
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*/
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timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN;
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timerp->cpmt_tcn2 = 0; /* reset state */
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timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2 */
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timerp->cpmt_tcn2 = 0; /* reset state */
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timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2 */
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/*
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* PIT setup:
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@ -148,9 +148,9 @@ unsigned long measure_gclk(void)
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/* spin until get exact count when we want to start */
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while (immr->im_sit.sit_pitr > SPEED_PITC);
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timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */
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timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */
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while ((immr->im_sit.sit_piscr & PISCR_PS) == 0);
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timerp->cpmt_tgcr |= TGCR_STP2; /* Stop Timer 2 */
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timerp->cpmt_tgcr |= TGCR_STP2; /* Stop Timer 2 */
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/* re-enable external interrupts if they were on */
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set_msr (msr_val);
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@ -166,7 +166,7 @@ unsigned long measure_gclk(void)
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/* not using OSCM, using XIN, so scale appropriately */
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return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
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#else
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return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
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return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
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#endif
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}
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@ -224,8 +224,9 @@ int get_clocks_866 (void)
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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char tmp[64];
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long cpuclk = 0;
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char tmp[64];
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long cpuclk = 0;
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long sccr_reg;
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if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
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cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
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@ -238,10 +239,19 @@ int get_clocks_866 (void)
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gd->cpu_clk = measure_gclk ();
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#endif
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if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0)
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/* if cpu clock <= 66 MHz then set bus division factor to 1,
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* otherwise set it to 2
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*/
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sccr_reg = immr->im_clkrst.car_sccr;
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sccr_reg &= ~SCCR_EBDF11;
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if (gd->cpu_clk <= 66000000) {
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sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */
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gd->bus_clk = gd->cpu_clk;
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else
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} else {
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sccr_reg |= SCCR_EBDF01; /* bus division factor = 2 */
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gd->bus_clk = gd->cpu_clk / 2;
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}
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immr->im_clkrst.car_sccr = sccr_reg;
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return (0);
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}
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@ -253,7 +263,7 @@ int sdram_adjust_866 (void)
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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long mamr;
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long mamr;
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mamr = immr->im_memctl.memc_mamr;
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mamr &= ~MAMR_PTA_MSK;
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@ -272,9 +282,9 @@ static long init_pll_866 (long clk)
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extern void plprcr_write_866 (long);
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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long n, plprcr;
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char mfi, mfn, mfd, s, pdf;
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long step_mfi, step_mfn;
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long n, plprcr;
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char mfi, mfn, mfd, s, pdf;
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long step_mfi, step_mfn;
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if (clk < 20000000) {
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clk *= 2;
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@ -284,7 +284,11 @@
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#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_USE_BUFFER_WRITE
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#define CFG_FLASH_BUFFER_WRITE_TOUT 2048 /* Timeout for Flash Buffer Write (in ms) */
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#define CFG_FLASH_BUFFER_SIZE 32 /* Buffer size */
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/* Buffer size.
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We have two flash devices connected in parallel.
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Each device incorporates a Write Buffer of 32 bytes.
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*/
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#define CFG_FLASH_BUFFER_SIZE (2*32)
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#if 1
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/* Put environment in flash which is much faster to boot */
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