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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

Browse Source 
- fsl-qoriq: Bug fixes related pfe, eth, thermal node, vid.c, cpu release,
  mmc, usb, env, etc for Layerscape boards
- powerpc: Update Maintainers for some boards.
This commit is contained in:
Tom Rini
2021-06-17 08:44:56 -04:00
parent 7e585b5a61 b7efcaff8b
commit a298d4fbcd
76 changed files with 1218 additions and 260 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
board/freescale/common/vid.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
* Copyright 2020-21 NXP
* Copyright 2020 Stephen Carlson <stcarlso@linux.microsoft.com>
*/
@@ -793,13 +793,16 @@ static int do_vdd_override(struct cmd_tbl *cmdtp,
char *const argv[])
{
ulong override;
int ret = 0;
if (argc < 2)
return CMD_RET_USAGE;
if (!strict_strtoul(argv[1], 10, &override))
adjust_vdd(override); /* the value is checked by callee */
else
if (!strict_strtoul(argv[1], 10, &override)) {
ret = adjust_vdd(override);
if (ret < 0)
return CMD_RET_FAILURE;
} else
return CMD_RET_USAGE;
return 0;
}

8
board/freescale/ls1012afrdm/ls1012afrdm.c
View File

@@ -23,6 +23,7 @@
#include <fsl_mmdc.h>
#include <netdev.h>
#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -185,6 +186,13 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_FSL_PFE
void board_quiesce_devices(void)
{
pfe_command_stop(0, NULL);
}
#endif
int ft_board_setup(void *blob, struct bd_info *bd)
{
arch_fixup_fdt(blob);

8
board/freescale/ls1012aqds/ls1012aqds.c
View File

@@ -32,6 +32,7 @@
#include "../common/qixis.h"
#include "ls1012aqds_qixis.h"
#include "ls1012aqds_pfe.h"
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -163,6 +164,13 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_FSL_PFE
void board_quiesce_devices(void)
{
pfe_command_stop(0, NULL);
}
#endif
int esdhc_status_fixup(void *blob, const char *compat)
{
char esdhc0_path[] = "/soc/esdhc@1560000";

8
board/freescale/ls1012ardb/ls1012ardb.c
View File

@@ -28,6 +28,7 @@
#include <fsl_mmdc.h>
#include <netdev.h>
#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -186,6 +187,13 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_FSL_PFE
void board_quiesce_devices(void)
{
pfe_command_stop(0, NULL);
}
#endif
#ifdef CONFIG_TARGET_LS1012ARDB
int esdhc_status_fixup(void *blob, const char *compat)
{

2
board/freescale/p1_p2_rdb_pc/MAINTAINERS
View File

@@ -1,5 +1,5 @@
P1_P2_RDB_PC BOARD
#M: -
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/p1_p2_rdb_pc/
F: include/configs/p1_p2_rdb_pc.h

2
board/freescale/p2041rdb/MAINTAINERS
View File

@@ -1,5 +1,5 @@
P2041RDB BOARD
#M: -
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/p2041rdb/
F: include/configs/P2041RDB.h

4
board/freescale/t102xrdb/MAINTAINERS
View File

@@ -1,6 +1,6 @@
T102XRDB BOARD
#M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
S: Orphan (since 2018-05)
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/t102xrdb/
F: include/configs/T102xRDB.h
F: configs/T1024RDB_defconfig

4
board/freescale/t208xrdb/Kconfig
View File

@@ -9,6 +9,10 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "T208xRDB"
config T2080RDB_REV_D
bool "Support for T2080RDB revisions D and up"
default n
source "board/freescale/common/Kconfig"
endif

4
board/freescale/t208xrdb/MAINTAINERS
View File

@@ -8,6 +8,10 @@ F: configs/T2080RDB_NAND_defconfig
F: configs/T2080RDB_SDCARD_defconfig
F: configs/T2080RDB_SPIFLASH_defconfig
F: configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
F: configs/T2080RDB_revD_defconfig
F: configs/T2080RDB_revD_NAND_defconfig
F: configs/T2080RDB_revD_SDCARD_defconfig
F: configs/T2080RDB_revD_SPIFLASH_defconfig
T2080RDB_SECURE_BOOT BOARD
M: Ruchika Gupta <ruchika.gupta@nxp.com>

112
board/freescale/t208xrdb/eth_t208xrdb.c
View File

@@ -26,84 +26,7 @@
#include <fsl_dtsec.h>
#include <asm/fsl_serdes.h>
int board_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_FMAN_ENET)
int i, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
switch (srds_s1) {
case 0x66:
case 0x6b:
fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
break;
default:
printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
srds_s1);
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}
extern u8 get_hw_revision(void);
/* Disable the MAC5 and MAC6 "fsl,fman-memac" nodes and the two
* "fsl,dpa-ethernet" nodes that reference them.
@@ -139,6 +62,39 @@ void fdt_fixup_board_fman_ethernet(void *fdt)
}
}
/* Update the address of the second Aquantia PHY on boards revision D and up.
* Also rename the PHY node to align with the address change.
*/
void fdt_fixup_board_phy(void *fdt)
{
const char phy_path[] =
"/soc@ffe000000/fman@400000/mdio@fd000/ethernet-phy@1";
int ret, offset, new_addr = AQR113C_PHY_ADDR2;
char new_name[] = "ethernet-phy@00";
if (get_hw_revision() == 'C')
return;
offset = fdt_path_offset(fdt, phy_path);
if (offset < 0) {
printf("ethernet-phy@1 node not found in the dts\n");
return;
}
ret = fdt_setprop(fdt, offset, "reg", &new_addr, sizeof(new_addr));
if (ret < 0) {
printf("Unable to set 'reg' for node ethernet-phy@1: %s\n",
fdt_strerror(ret));
return;
}
sprintf(new_name, "ethernet-phy@%x", new_addr);
ret = fdt_set_name(fdt, offset, new_name);
if (ret < 0)
printf("Unable to rename node ethernet-phy@1: %s\n",
fdt_strerror(ret));
}
void fdt_fixup_board_enet(void *fdt)
{
return;

24
board/freescale/t208xrdb/t208xrdb.c
View File

@@ -27,14 +27,29 @@
DECLARE_GLOBAL_DATA_PTR;
u8 get_hw_revision(void)
{
u8 ver = CPLD_READ(hw_ver);
switch (ver) {
default:
case 0x1:
return 'C';
case 0x0:
return 'D';
case 0x2:
return 'E';
}
}
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
printf("Board: %sRDB, ", cpu->name);
printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
CPLD_READ(hw_ver), CPLD_READ(sw_ver));
printf("Board rev: %c CPLD ver: 0x%02x, boot from ",
get_hw_revision(), CPLD_READ(sw_ver));
#ifdef CONFIG_SDCARD
puts("SD/MMC\n");
@@ -136,12 +151,9 @@ int ft_board_setup(void *blob, struct bd_info *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#else
fdt_fixup_board_fman_ethernet(blob);
#endif
fdt_fixup_board_enet(blob);
fdt_fixup_board_phy(blob);
#endif
return 0;

1
board/freescale/t208xrdb/t208xrdb.h
View File

@@ -10,5 +10,6 @@
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, struct bd_info *bd);
void fdt_fixup_board_fman_ethernet(void *blob);
void fdt_fixup_board_phy(void *blob);
#endif

4
board/freescale/t4rdb/MAINTAINERS
View File

@@ -1,6 +1,6 @@
T4RDB BOARD
#M: Chunhe Lan <Chunhe.Lan@freescale.com>
S: Orphan (since 2018-05)
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/t4rdb/
F: include/configs/T4240RDB.h
F: configs/T4160RDB_defconfig

7
board/keymile/Kconfig
View File

@@ -64,6 +64,13 @@ config SYS_PAX_BASE
help
IFC Base Address for PAXx FPGA.
config SYS_CLIPS_BASE
hex "CLIPS IFC Base Address"
default 0x78000000
depends on ARCH_LS1021A
help
IFC Base Address for CLIPS FPGA.
config KM_CONSOLE_TTY
string "KM Console"
default "ttyS0"

11
board/keymile/common/common.c
View File

@@ -46,12 +46,14 @@ int set_km_env(void)
unsigned int pram;
unsigned int varaddr;
unsigned int kernelmem;
char *p;
unsigned long rootfssize = 0;
char envval[16];
char *p;
pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM;
env_set_hex("pnvramaddr", pnvramaddr);
sprintf(envval, "0x%x", pnvramaddr);
env_set("pnvramaddr", envval);
/* try to read rootfssize (ram image) from environment */
p = env_get("rootfssize");
@@ -64,9 +66,12 @@ int set_km_env(void)
varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
env_set_hex("varaddr", varaddr);
sprintf(envval, "0x%x", varaddr);
env_set("varaddr", envval);
kernelmem = gd->ram_size - 0x400 * pram;
env_set_hex("kernelmem", kernelmem);
sprintf(envval, "0x%x", kernelmem);
env_set("kernelmem", envval);
return 0;
}

20
board/keymile/pg-wcom-ls102xa/Kconfig
View File

@@ -17,3 +17,23 @@ config BOARD_SPECIFIC_OPTIONS
imply FS_CRAMFS
endif
if TARGET_PG_WCOM_EXPU1
config SYS_BOARD
default "pg-wcom-ls102xa"
config SYS_VENDOR
default "keymile"
config SYS_SOC
default "ls102xa"
config SYS_CONFIG_NAME
default "pg-wcom-expu1"
config BOARD_SPECIFIC_OPTIONS
def_bool y
imply FS_CRAMFS
endif

3
board/keymile/pg-wcom-ls102xa/MAINTAINERS
View File

@@ -6,5 +6,8 @@ S: Maintained
F: board/keymile/pg-wcom-ls102xa/
F: include/configs/km/pg-wcom-ls102xa.h
F: include/configs/pg-wcom-seli8.h
F: include/configs/pg-wcom-expu1.h
F: configs/pg_wcom_seli8_defconfig
F: configs/pg_wcom_expu1_defconfig
F: arch/arm/dts/ls1021a-pg-wcom-seli8.dts
F: arch/arm/dts/ls1021a-pg-wcom-expu1.dts

69
board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
View File

@@ -70,19 +70,38 @@ int board_early_init_f(void)
/* QRIO Configuration */
qrio_uprstreq(UPREQ_CORE_RST);
if (IS_ENABLED(CONFIG_TARGET_PG_WCOM_SELI8)) {
qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_LIU_RST, true);
#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_SELI8)
qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_LIU_RST, true);
qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_PAXK_RST, true);
qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_PAXK_RST, true);
#endif
qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
qrio_prst(KM_DBG_ETH_RST, false, false);
}
#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_EXPU1)
qrio_prstcfg(WCOM_TMG_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(WCOM_TMG_RST, true);
qrio_prstcfg(WCOM_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_prst(WCOM_PHY_RST, false, false);
qrio_prstcfg(WCOM_QSFP_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(WCOM_QSFP_RST, true);
qrio_prstcfg(WCOM_CLIPS_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_prst(WCOM_CLIPS_RST, false, false);
#endif
qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
qrio_prst(KM_DBG_ETH_RST, false, false);
i2c_deblock_gpio_cfg();
/* enable the Unit LED (red) & Boot LED (on) */
qrio_set_leds();
/* enable Application Buffer */
qrio_enable_app_buffer();
arch_soc_init();
return 0;
@@ -128,6 +147,40 @@ int ft_board_setup(void *blob, struct bd_info *bd)
return 0;
}
#if defined(CONFIG_POST)
int post_hotkeys_pressed(void)
{
/* DIC26_SELFTEST: GPRTA0, GPA0 */
qrio_gpio_direction_input(QRIO_GPIO_A, 0);
return qrio_get_gpio(QRIO_GPIO_A, 0);
}
ulong post_word_load(void)
{
/* POST word is located at the beginning of reserved physical RAM */
void *addr = (void *)(CONFIG_SYS_SDRAM_BASE +
gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8);
return in_le32(addr);
}
void post_word_store(ulong value)
{
/* POST word is located at the beginning of reserved physical RAM */
void *addr = (void *)(CONFIG_SYS_SDRAM_BASE +
gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8);
out_le32(addr, value);
}
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
/* Define only 1MiB range for mem_regions at the middle of the RAM */
/* For 1GiB range mem_regions takes approx. 4min */
*vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
*size = 1 << 20;
return 0;
}
#endif
u8 flash_read8(void *addr)
{
return __raw_readb(addr + 1);

2
board/keymile/scripts/ramfs-common.txt
View File

@@ -3,7 +3,7 @@ boot_bank=-1
altbootcmd=run ${subbootcmds}
bootcmd=run ${subbootcmds}
subbootcmds=save_and_reset_once tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot
save_and_reset_once=setenv save_and_reset_once true && save && reset
save_and_reset_once=setenv save_and_reset_once true && saveenv && reset
nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}
configure=run set_uimage; run set_tftppath; km_setboardid && run try_import_rootfssize && saveenv && reset
setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value}