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MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig

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This converts the following to Kconfig:
    CONFIG_SYS_MIPS_TIMER_REQ

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Daniel Schwierzeck 2022-07-10 17:15:14 +02:00
parent ea24b0eacf
commit a29491ade0
71 changed files with 61 additions and 68 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
arch/mips/Kconfig
View File

@ -14,6 +14,7 @@ choice
config TARGET_MALTA config TARGET_MALTA
bool "Support malta" bool "Support malta"
select HAS_FIXED_TIMER_FREQUENCY
select BOARD_EARLY_INIT_R select BOARD_EARLY_INIT_R
select DM select DM
select DM_SERIAL select DM_SERIAL
@ -41,17 +42,20 @@ config TARGET_MALTA
config ARCH_ATH79 config ARCH_ATH79
bool "Support QCA/Atheros ath79" bool "Support QCA/Atheros ath79"
select HAS_FIXED_TIMER_FREQUENCY
select DM select DM
select OF_CONTROL select OF_CONTROL
imply CMD_DM imply CMD_DM
config ARCH_MSCC config ARCH_MSCC
bool "Support MSCC VCore-III" bool "Support MSCC VCore-III"
select HAS_FIXED_TIMER_FREQUENCY
select OF_CONTROL select OF_CONTROL
select DM select DM
config ARCH_BMIPS config ARCH_BMIPS
bool "Support BMIPS SoCs" bool "Support BMIPS SoCs"
select HAS_FIXED_TIMER_FREQUENCY
select CLK select CLK
select CPU select CPU
select DM select DM
@ -62,6 +66,7 @@ config ARCH_BMIPS
config ARCH_MTMIPS config ARCH_MTMIPS
bool "Support MediaTek MIPS platforms" bool "Support MediaTek MIPS platforms"
select HAS_FIXED_TIMER_FREQUENCY
select CLK select CLK
imply CMD_DM imply CMD_DM
select DISPLAY_CPUINFO select DISPLAY_CPUINFO
@ -88,6 +93,7 @@ config ARCH_MTMIPS
config ARCH_JZ47XX config ARCH_JZ47XX
bool "Support Ingenic JZ47xx" bool "Support Ingenic JZ47xx"
select SUPPORT_SPL select SUPPORT_SPL
select HAS_FIXED_TIMER_FREQUENCY
select OF_CONTROL select OF_CONTROL
select DM select DM
@ -116,12 +122,14 @@ config ARCH_OCTEON
config MACH_PIC32 config MACH_PIC32
bool "Support Microchip PIC32" bool "Support Microchip PIC32"
select HAS_FIXED_TIMER_FREQUENCY
select DM select DM
select OF_CONTROL select OF_CONTROL
imply CMD_DM imply CMD_DM
config TARGET_BOSTON config TARGET_BOSTON
bool "Support Boston" bool "Support Boston"
select HAS_FIXED_TIMER_FREQUENCY
select DM select DM
imply DM_EVENT imply DM_EVENT
select DM_SERIAL select DM_SERIAL
@ -143,6 +151,7 @@ config TARGET_BOSTON
config TARGET_XILFPGA config TARGET_XILFPGA
bool "Support Imagination Xilfpga" bool "Support Imagination Xilfpga"
select HAS_FIXED_TIMER_FREQUENCY
select DM select DM
select DM_ETH select DM_ETH
select DM_GPIO select DM_GPIO
@ -246,6 +255,12 @@ config ROM_EXCEPTION_VECTORS
Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
In that case the image size will be reduced by 0x500 bytes. In that case the image size will be reduced by 0x500 bytes.
config SYS_MIPS_TIMER_FREQ
int "Fixed MIPS CPU timer frequency in Hz"
depends on HAS_FIXED_TIMER_FREQUENCY
help
Configures a fixed CPU timer frequency.
config MIPS_CM_BASE config MIPS_CM_BASE
hex "MIPS CM GCR Base Address" hex "MIPS CM GCR Base Address"
depends on MIPS_CM depends on MIPS_CM
@ -427,6 +442,9 @@ config SUPPORTS_CPU_MIPS64_R6
config SUPPORTS_CPU_MIPS64_OCTEON config SUPPORTS_CPU_MIPS64_OCTEON
bool bool
config HAS_FIXED_TIMER_FREQUENCY
bool
config CPU_CAVIUM_OCTEON config CPU_CAVIUM_OCTEON
bool bool

1
configs/ap121_defconfig
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@ -11,6 +11,7 @@ CONFIG_DEBUG_UART_CLOCK=25000000
CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ARCH_ATH79=y CONFIG_ARCH_ATH79=y
CONFIG_SYS_MIPS_TIMER_FREQ=200000000
CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x80100000 CONFIG_SYS_MEMTEST_START=0x80100000
CONFIG_SYS_MEMTEST_END=0x83f00000 CONFIG_SYS_MEMTEST_END=0x83f00000

1
configs/ap143_defconfig
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@ -13,6 +13,7 @@ CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ARCH_ATH79=y CONFIG_ARCH_ATH79=y
CONFIG_TARGET_AP143=y CONFIG_TARGET_AP143=y
CONFIG_SYS_MIPS_TIMER_FREQ=325000000
CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x80100000 CONFIG_SYS_MEMTEST_START=0x80100000
CONFIG_SYS_MEMTEST_END=0x83f00000 CONFIG_SYS_MEMTEST_END=0x83f00000

1
configs/ap152_defconfig
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@ -13,6 +13,7 @@ CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ARCH_ATH79=y CONFIG_ARCH_ATH79=y
CONFIG_TARGET_AP152=y CONFIG_TARGET_AP152=y
CONFIG_SYS_MIPS_TIMER_FREQ=375000000
CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x80100000 CONFIG_SYS_MEMTEST_START=0x80100000
CONFIG_SYS_MEMTEST_END=0x83f00000 CONFIG_SYS_MEMTEST_END=0x83f00000

1
configs/bcm968380gerg_ram_defconfig
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@ -9,6 +9,7 @@ CONFIG_SYS_PROMPT="bcm968380gerg # "
CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6838=y CONFIG_SOC_BMIPS_BCM6838=y
CONFIG_SYS_MIPS_TIMER_FREQ=160000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set

1
configs/boston32r2_defconfig
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@ -9,6 +9,7 @@ CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_ENV_ADDR=0xBFFE0000 CONFIG_ENV_ADDR=0xBFFE0000
CONFIG_TARGET_BOSTON=y CONFIG_TARGET_BOSTON=y
CONFIG_SYS_MIPS_TIMER_FREQ=30000000
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y CONFIG_MIPS_BOOT_FDT=y

1
configs/boston32r2el_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_ENV_ADDR=0xBFFE0000 CONFIG_ENV_ADDR=0xBFFE0000
CONFIG_TARGET_BOSTON=y CONFIG_TARGET_BOSTON=y
CONFIG_SYS_MIPS_TIMER_FREQ=30000000
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y CONFIG_MIPS_BOOT_FDT=y

1
configs/boston32r6_defconfig
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@ -10,6 +10,7 @@ CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_ENV_ADDR=0xBFFE0000 CONFIG_ENV_ADDR=0xBFFE0000
CONFIG_TARGET_BOSTON=y CONFIG_TARGET_BOSTON=y
CONFIG_CPU_MIPS32_R6=y CONFIG_CPU_MIPS32_R6=y
CONFIG_SYS_MIPS_TIMER_FREQ=30000000
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y CONFIG_MIPS_BOOT_FDT=y

1
configs/boston32r6el_defconfig
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@ -10,6 +10,7 @@ CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_ENV_ADDR=0xBFFE0000 CONFIG_ENV_ADDR=0xBFFE0000
CONFIG_TARGET_BOSTON=y CONFIG_TARGET_BOSTON=y
CONFIG_CPU_MIPS32_R6=y CONFIG_CPU_MIPS32_R6=y
CONFIG_SYS_MIPS_TIMER_FREQ=30000000
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y CONFIG_MIPS_BOOT_FDT=y

1
configs/boston64r2_defconfig
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@ -10,6 +10,7 @@ CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
CONFIG_TARGET_BOSTON=y CONFIG_TARGET_BOSTON=y
CONFIG_CPU_MIPS64_R2=y CONFIG_CPU_MIPS64_R2=y
CONFIG_SYS_MIPS_TIMER_FREQ=30000000
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y CONFIG_MIPS_BOOT_FDT=y

1
configs/boston64r2el_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
CONFIG_TARGET_BOSTON=y CONFIG_TARGET_BOSTON=y
CONFIG_CPU_MIPS64_R2=y CONFIG_CPU_MIPS64_R2=y
CONFIG_SYS_MIPS_TIMER_FREQ=30000000
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y CONFIG_MIPS_BOOT_FDT=y

1
configs/boston64r6_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
CONFIG_TARGET_BOSTON=y CONFIG_TARGET_BOSTON=y
CONFIG_CPU_MIPS64_R6=y CONFIG_CPU_MIPS64_R6=y
CONFIG_SYS_MIPS_TIMER_FREQ=30000000
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y CONFIG_MIPS_BOOT_FDT=y

1
configs/boston64r6el_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
CONFIG_TARGET_BOSTON=y CONFIG_TARGET_BOSTON=y
CONFIG_CPU_MIPS64_R6=y CONFIG_CPU_MIPS64_R6=y
CONFIG_SYS_MIPS_TIMER_FREQ=30000000
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y CONFIG_MIPS_BOOT_FDT=y

1
configs/ci20_mmc_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_SPL_MMC=y
CONFIG_SPL=y CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ARCH_JZ47XX=y CONFIG_ARCH_JZ47XX=y
CONFIG_SYS_MIPS_TIMER_FREQ=1200000000
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1" CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1"

1
configs/comtrend_ar5315u_ram_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_SYS_PROMPT="AR-5315un # "
CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6318=y CONFIG_SOC_BMIPS_BCM6318=y
CONFIG_SYS_MIPS_TIMER_FREQ=166500000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set

1
configs/comtrend_ar5387un_ram_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_SYS_PROMPT="AR-5387un # "
CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6328=y CONFIG_SOC_BMIPS_BCM6328=y
CONFIG_SYS_MIPS_TIMER_FREQ=160000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set

1
configs/comtrend_ct5361_ram_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_SYS_PROMPT="CT-5361 # "
CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6348=y CONFIG_SOC_BMIPS_BCM6348=y
CONFIG_SYS_MIPS_TIMER_FREQ=128000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set

1
configs/comtrend_vr3032u_ram_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_SYS_PROMPT="VR-3032u # "
CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM63268=y CONFIG_SOC_BMIPS_BCM63268=y
CONFIG_SYS_MIPS_TIMER_FREQ=200000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set

1
configs/comtrend_wap5813n_ram_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_SYS_PROMPT="WAP-5813n # "
CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6368=y CONFIG_SOC_BMIPS_BCM6368=y
CONFIG_SYS_MIPS_TIMER_FREQ=200000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set

1
configs/gardena-smart-gateway-mt7688_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_ENV_OFFSET_REDUND=0xB0000
CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_MTMIPS=y CONFIG_ARCH_MTMIPS=y
CONFIG_SOC_MT7628=y CONFIG_SOC_MT7628=y
CONFIG_SYS_MIPS_TIMER_FREQ=290000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y

1
configs/huawei_hg556a_ram_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_SYS_PROMPT="HG556a # "
CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6358=y CONFIG_SOC_BMIPS_BCM6358=y
CONFIG_SYS_MIPS_TIMER_FREQ=150000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set

1
configs/imgtec_xilfpga_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr"
CONFIG_SYS_PROMPT="MIPSfpga # " CONFIG_SYS_PROMPT="MIPSfpga # "
CONFIG_SYS_LOAD_ADDR=0x80500000 CONFIG_SYS_LOAD_ADDR=0x80500000
CONFIG_TARGET_XILFPGA=y CONFIG_TARGET_XILFPGA=y
CONFIG_SYS_MIPS_TIMER_FREQ=50000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set

1
configs/linkit-smart-7688_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_MTMIPS=y CONFIG_ARCH_MTMIPS=y
CONFIG_SOC_MT7628=y CONFIG_SOC_MT7628=y
CONFIG_BOARD_LINKIT_SMART_7688=y CONFIG_BOARD_LINKIT_SMART_7688=y
CONFIG_SYS_MIPS_TIMER_FREQ=290000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y

1
configs/malta64_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_SYS_LOAD_ADDR=0xffffffff81000000
CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000 CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000
CONFIG_TARGET_MALTA=y CONFIG_TARGET_MALTA=y
CONFIG_CPU_MIPS64_R2=y CONFIG_CPU_MIPS64_R2=y
CONFIG_SYS_MIPS_TIMER_FREQ=250000000
# CONFIG_AUTOBOOT is not set # CONFIG_AUTOBOOT is not set
CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y CONFIG_MISC_INIT_R=y

1
configs/malta64el_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000
CONFIG_TARGET_MALTA=y CONFIG_TARGET_MALTA=y
CONFIG_BUILD_TARGET="u-boot-swap.bin" CONFIG_BUILD_TARGET="u-boot-swap.bin"
CONFIG_CPU_MIPS64_R2=y CONFIG_CPU_MIPS64_R2=y
CONFIG_SYS_MIPS_TIMER_FREQ=250000000
CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_SYS_LITTLE_ENDIAN=y
# CONFIG_AUTOBOOT is not set # CONFIG_AUTOBOOT is not set
CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_F=y

1
configs/malta_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_SYS_PROMPT="malta # "
CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ENV_ADDR=0xBE3E0000 CONFIG_ENV_ADDR=0xBE3E0000
CONFIG_TARGET_MALTA=y CONFIG_TARGET_MALTA=y
CONFIG_SYS_MIPS_TIMER_FREQ=250000000
# CONFIG_AUTOBOOT is not set # CONFIG_AUTOBOOT is not set
CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y CONFIG_MISC_INIT_R=y

1
configs/maltael_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ENV_ADDR=0xBE3E0000 CONFIG_ENV_ADDR=0xBE3E0000
CONFIG_TARGET_MALTA=y CONFIG_TARGET_MALTA=y
CONFIG_BUILD_TARGET="u-boot-swap.bin" CONFIG_BUILD_TARGET="u-boot-swap.bin"
CONFIG_SYS_MIPS_TIMER_FREQ=250000000
CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_SYS_LITTLE_ENDIAN=y
# CONFIG_AUTOBOOT is not set # CONFIG_AUTOBOOT is not set
CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_F=y

1
configs/mscc_jr2_defconfig
View File

@ -14,6 +14,7 @@ CONFIG_ENV_OFFSET_REDUND=0x140000
CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ARCH_MSCC=y CONFIG_ARCH_MSCC=y
CONFIG_SOC_JR2=y CONFIG_SOC_JR2=y
CONFIG_SYS_MIPS_TIMER_FREQ=250000000
CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fc00000 CONFIG_SYS_MEMTEST_END=0x9fc00000

1
configs/mscc_luton_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ARCH_MSCC=y CONFIG_ARCH_MSCC=y
CONFIG_SOC_LUTON=y CONFIG_SOC_LUTON=y
CONFIG_DDRTYPE_MT47H128M8HQ=y CONFIG_DDRTYPE_MT47H128M8HQ=y
CONFIG_SYS_MIPS_TIMER_FREQ=208333333
CONFIG_MIPS_BOOT_FDT=y CONFIG_MIPS_BOOT_FDT=y
CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_START=0x80000000

1
configs/mscc_ocelot_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ENV_OFFSET_REDUND=0x140000 CONFIG_ENV_OFFSET_REDUND=0x140000
CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ARCH_MSCC=y CONFIG_ARCH_MSCC=y
CONFIG_SYS_MIPS_TIMER_FREQ=250000000
CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fc00000 CONFIG_SYS_MEMTEST_END=0x9fc00000

1
configs/mscc_serval_defconfig
View File

@ -12,6 +12,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ARCH_MSCC=y CONFIG_ARCH_MSCC=y
CONFIG_SOC_SERVAL=y CONFIG_SOC_SERVAL=y
CONFIG_DDRTYPE_H5TQ1G63BFA=y CONFIG_DDRTYPE_H5TQ1G63BFA=y
CONFIG_SYS_MIPS_TIMER_FREQ=208333333
CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_SYS_LITTLE_ENDIAN=y

1
configs/mscc_servalt_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_ENV_OFFSET_REDUND=0x140000
CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ARCH_MSCC=y CONFIG_ARCH_MSCC=y
CONFIG_SOC_SERVALT=y CONFIG_SOC_SERVALT=y
CONFIG_SYS_MIPS_TIMER_FREQ=250000000
CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fc00000 CONFIG_SYS_MEMTEST_END=0x9fc00000
CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_SYS_LITTLE_ENDIAN=y

1
configs/mt7620_mt7530_rfb_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_SYS_LOAD_ADDR=0x80010000 CONFIG_SYS_LOAD_ADDR=0x80010000
CONFIG_ARCH_MTMIPS=y CONFIG_ARCH_MTMIPS=y
CONFIG_BOARD_MT7620_MT7530_RFB=y CONFIG_BOARD_MT7620_MT7530_RFB=y
CONFIG_SYS_MIPS_TIMER_FREQ=290000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y

1
configs/mt7620_rfb_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_DEBUG_UART_BASE=0xb0000c00
CONFIG_DEBUG_UART_CLOCK=40000000 CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_SYS_LOAD_ADDR=0x80010000 CONFIG_SYS_LOAD_ADDR=0x80010000
CONFIG_ARCH_MTMIPS=y CONFIG_ARCH_MTMIPS=y
CONFIG_SYS_MIPS_TIMER_FREQ=290000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y

1
configs/mt7621_nand_rfb_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_ARCH_MTMIPS=y
CONFIG_SOC_MT7621=y CONFIG_SOC_MT7621=y
CONFIG_MT7621_BOOT_FROM_NAND=y CONFIG_MT7621_BOOT_FROM_NAND=y
CONFIG_BOARD_MT7621_NAND_RFB=y CONFIG_BOARD_MT7621_NAND_RFB=y
CONFIG_SYS_MIPS_TIMER_FREQ=440000000
# CONFIG_MIPS_CACHE_SETUP is not set # CONFIG_MIPS_CACHE_SETUP is not set
# CONFIG_MIPS_CACHE_DISABLE is not set # CONFIG_MIPS_CACHE_DISABLE is not set
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y

1
configs/mt7621_rfb_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_SYS_LOAD_ADDR=0x83000000 CONFIG_SYS_LOAD_ADDR=0x83000000
CONFIG_ARCH_MTMIPS=y CONFIG_ARCH_MTMIPS=y
CONFIG_SOC_MT7621=y CONFIG_SOC_MT7621=y
CONFIG_SYS_MIPS_TIMER_FREQ=440000000
# CONFIG_MIPS_CACHE_SETUP is not set # CONFIG_MIPS_CACHE_SETUP is not set
# CONFIG_MIPS_CACHE_DISABLE is not set # CONFIG_MIPS_CACHE_DISABLE is not set
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y

1
configs/mt7628_rfb_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x80010000
CONFIG_ARCH_MTMIPS=y CONFIG_ARCH_MTMIPS=y
CONFIG_SOC_MT7628=y CONFIG_SOC_MT7628=y
CONFIG_BOARD_MT7628_RFB=y CONFIG_BOARD_MT7628_RFB=y
CONFIG_SYS_MIPS_TIMER_FREQ=290000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y

1
configs/netgear_cg3100d_ram_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="netgear,cg3100d"
CONFIG_SYS_PROMPT="CG3100D # " CONFIG_SYS_PROMPT="CG3100D # "
CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y CONFIG_ARCH_BMIPS=y
CONFIG_SYS_MIPS_TIMER_FREQ=166500000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set

1
configs/netgear_dgnd3700v2_ram_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_SYS_PROMPT="DGND3700v2 # "
CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6362=y CONFIG_SOC_BMIPS_BCM6362=y
CONFIG_SYS_MIPS_TIMER_FREQ=200000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set

1
configs/pic32mzdask_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk"
CONFIG_SYS_PROMPT="dask # " CONFIG_SYS_PROMPT="dask # "
CONFIG_SYS_LOAD_ADDR=0x88500000 CONFIG_SYS_LOAD_ADDR=0x88500000
CONFIG_MACH_PIC32=y CONFIG_MACH_PIC32=y
CONFIG_SYS_MIPS_TIMER_FREQ=100000000
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y CONFIG_MIPS_BOOT_FDT=y
CONFIG_SYS_MEMTEST_START=0x88000000 CONFIG_SYS_MEMTEST_START=0x88000000

1
configs/sagem_f@st1704_ram_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_SYS_PROMPT="F@ST1704 # "
CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6338=y CONFIG_SOC_BMIPS_BCM6338=y
CONFIG_SYS_MIPS_TIMER_FREQ=120000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set

1
configs/sfr_nb4-ser_ram_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_BMIPS=y CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6358=y CONFIG_SOC_BMIPS_BCM6358=y
CONFIG_BOARD_SFR_NB4_SER=y CONFIG_BOARD_SFR_NB4_SER=y
CONFIG_SYS_MIPS_TIMER_FREQ=150000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set

1
configs/tplink_wdr4300_defconfig
View File

@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
CONFIG_SYS_LOAD_ADDR=0xa1000000 CONFIG_SYS_LOAD_ADDR=0xa1000000
CONFIG_ARCH_ATH79=y CONFIG_ARCH_ATH79=y
CONFIG_BOARD_TPLINK_WDR4300=y CONFIG_BOARD_TPLINK_WDR4300=y
CONFIG_SYS_MIPS_TIMER_FREQ=280000000
CONFIG_SYS_MEMTEST_START=0x80100000 CONFIG_SYS_MEMTEST_START=0x80100000
CONFIG_SYS_MEMTEST_END=0x83f00000 CONFIG_SYS_MEMTEST_END=0x83f00000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y

1
configs/vocore2_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_ARCH_MTMIPS=y CONFIG_ARCH_MTMIPS=y
CONFIG_SOC_MT7628=y CONFIG_SOC_MT7628=y
CONFIG_BOARD_VOCORE2=y CONFIG_BOARD_VOCORE2=y
CONFIG_SYS_MIPS_TIMER_FREQ=290000000
CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y CONFIG_MIPS_CACHE_DISABLE=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y

2
include/configs/ap121.h
View File

@ -6,8 +6,6 @@
#ifndef __CONFIG_H #ifndef __CONFIG_H
#define __CONFIG_H #define __CONFIG_H
#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000

2
include/configs/ap143.h
View File

@ -6,8 +6,6 @@
#ifndef __CONFIG_H #ifndef __CONFIG_H
#define __CONFIG_H #define __CONFIG_H
#define CONFIG_SYS_MIPS_TIMER_FREQ 325000000
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000

2
include/configs/ap152.h
View File

@ -6,8 +6,6 @@
#ifndef __CONFIG_H #ifndef __CONFIG_H
#define __CONFIG_H #define __CONFIG_H
#define CONFIG_SYS_MIPS_TIMER_FREQ 375000000
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000

3
include/configs/bmips_bcm3380.h
View File

@ -8,9 +8,6 @@
#include <linux/sizes.h> #include <linux/sizes.h>
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 166500000
/* RAM */ /* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000

3
include/configs/bmips_bcm6318.h
View File

@ -8,9 +8,6 @@
#include <linux/sizes.h> #include <linux/sizes.h>
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 166500000
/* RAM */ /* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000

3
include/configs/bmips_bcm63268.h
View File

@ -8,9 +8,6 @@
#include <linux/sizes.h> #include <linux/sizes.h>
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
/* RAM */ /* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000

3
include/configs/bmips_bcm6328.h
View File

@ -8,9 +8,6 @@
#include <linux/sizes.h> #include <linux/sizes.h>
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 160000000
/* RAM */ /* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000

3
include/configs/bmips_bcm6338.h
View File

@ -8,9 +8,6 @@
#include <linux/sizes.h> #include <linux/sizes.h>
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 120000000
/* RAM */ /* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000

3
include/configs/bmips_bcm6348.h
View File

@ -8,9 +8,6 @@
#include <linux/sizes.h> #include <linux/sizes.h>
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 128000000
/* RAM */ /* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000

3
include/configs/bmips_bcm6358.h
View File

@ -8,9 +8,6 @@
#include <linux/sizes.h> #include <linux/sizes.h>
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 150000000
/* RAM */ /* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000

3
include/configs/bmips_bcm6362.h
View File

@ -8,9 +8,6 @@
#include <linux/sizes.h> #include <linux/sizes.h>
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
/* RAM */ /* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000

3
include/configs/bmips_bcm6368.h
View File

@ -8,9 +8,6 @@
#include <linux/sizes.h> #include <linux/sizes.h>
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
/* RAM */ /* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000

3
include/configs/bmips_bcm6838.h
View File

@ -8,9 +8,6 @@
#include <linux/sizes.h> #include <linux/sizes.h>
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 160000000
/* RAM */ /* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000

1
include/configs/boston.h
View File

@ -13,7 +13,6 @@
/* /*
* CPU * CPU
*/ */
#define CONFIG_SYS_MIPS_TIMER_FREQ 30000000
/* /*
* PCI * PCI

3
include/configs/ci20.h
View File

@ -9,9 +9,6 @@
#ifndef __CONFIG_CI20_H__ #ifndef __CONFIG_CI20_H__
#define __CONFIG_CI20_H__ #define __CONFIG_CI20_H__
/* Ingenic JZ4780 clock configuration. */
#define CONFIG_SYS_MIPS_TIMER_FREQ 1200000000
/* Memory configuration */ /* Memory configuration */
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024)

3
include/configs/gardena-smart-gateway-mt7688.h
View File

@ -6,9 +6,6 @@
#ifndef __CONFIG_GARDENA_SMART_GATEWAY_H #ifndef __CONFIG_GARDENA_SMART_GATEWAY_H
#define __CONFIG_GARDENA_SMART_GATEWAY_H #define __CONFIG_GARDENA_SMART_GATEWAY_H
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
/* RAM */ /* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000

2
include/configs/imgtec_xilfpga.h
View File

@ -15,8 +15,6 @@
/*-------------------------------------------- /*--------------------------------------------
* CPU configuration * CPU configuration
*/ */
/* CPU Timer rate */
#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
* Memory Layout * Memory Layout

3
include/configs/linkit-smart-7688.h
View File

@ -6,9 +6,6 @@
#ifndef __CONFIG_LINKIT_SMART_7688_H #ifndef __CONFIG_LINKIT_SMART_7688_H
#define __CONFIG_LINKIT_SMART_7688_H #define __CONFIG_LINKIT_SMART_7688_H
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
/* RAM */ /* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000

1
include/configs/malta.h
View File

@ -18,7 +18,6 @@
/* /*
* CPU Configuration * CPU Configuration
*/ */
#define CONFIG_SYS_MIPS_TIMER_FREQ 250000000
/* /*
* Memory map * Memory map

2
include/configs/mt7620.h
View File

@ -8,8 +8,6 @@
#ifndef __CONFIG_MT7620_H #ifndef __CONFIG_MT7620_H
#define __CONFIG_MT7620_H #define __CONFIG_MT7620_H
#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000

2
include/configs/mt7621.h
View File

@ -8,8 +8,6 @@
#ifndef __CONFIG_MT7621_H #ifndef __CONFIG_MT7621_H
#define __CONFIG_MT7621_H #define __CONFIG_MT7621_H
#define CONFIG_SYS_MIPS_TIMER_FREQ 440000000
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_VERY_BIG_RAM #define CONFIG_VERY_BIG_RAM

2
include/configs/mt7628.h
View File

@ -8,8 +8,6 @@
#ifndef __CONFIG_MT7628_H #ifndef __CONFIG_MT7628_H
#define __CONFIG_MT7628_H #define __CONFIG_MT7628_H
#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x80000 #define CONFIG_SYS_INIT_SP_OFFSET 0x80000

2
include/configs/pic32mzdask.h
View File

@ -13,8 +13,6 @@
/*-------------------------------------------- /*--------------------------------------------
* CPU configuration * CPU configuration
*/ */
/* CPU Timer rate */
#define CONFIG_SYS_MIPS_TIMER_FREQ 100000000
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
* Memory Layout * Memory Layout

2
include/configs/tplink_wdr4300.h
View File

@ -6,8 +6,6 @@
#ifndef __CONFIG_H #ifndef __CONFIG_H
#define __CONFIG_H #define __CONFIG_H
#define CONFIG_SYS_MIPS_TIMER_FREQ 280000000
#define CONFIG_SYS_SDRAM_BASE 0xa0000000 #define CONFIG_SYS_SDRAM_BASE 0xa0000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000

5
include/configs/vcoreiii.h
View File

@ -12,11 +12,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
#if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL)
#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333
#else
#define CONFIG_SYS_MIPS_TIMER_FREQ 250000000
#endif
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000

3
include/configs/vocore2.h
View File

@ -6,9 +6,6 @@
#ifndef __VOCORE2_CONFIG_H__ #ifndef __VOCORE2_CONFIG_H__
#define __VOCORE2_CONFIG_H__ #define __VOCORE2_CONFIG_H__
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
/* RAM */ /* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000

1
scripts/config_whitelist.txt
View File

@ -872,7 +872,6 @@ CONFIG_SYS_MDIO1_OFFSET
CONFIG_SYS_MEMORY_BASE CONFIG_SYS_MEMORY_BASE
CONFIG_SYS_MEM_RESERVE_SECURE CONFIG_SYS_MEM_RESERVE_SECURE
CONFIG_SYS_MFD CONFIG_SYS_MFD
CONFIG_SYS_MIPS_TIMER_FREQ
CONFIG_SYS_MMC_CD_PIN CONFIG_SYS_MMC_CD_PIN
CONFIG_SYS_MMC_CLK_OD CONFIG_SYS_MMC_CLK_OD
CONFIG_SYS_MMC_MAX_BLK_COUNT CONFIG_SYS_MMC_MAX_BLK_COUNT