mx6: Fix use of improper value in enable_ipu_clock
The value MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET that was used to initialize the CCGR3 register caused an undefined value for CG0. Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de> Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
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@ -487,7 +487,7 @@ void enable_ipu_clock(void)
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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int reg;
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reg = readl(&mxc_ccm->CCGR3);
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reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
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reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
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writel(reg, &mxc_ccm->CCGR3);
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}
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/***************************************************/
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