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Merge branch '2022-01-12-pci-updates'

Browse Source 
- PCI code clean up and bug fixes from Pali
This commit is contained in:
Tom Rini 2022-01-12 20:49:39 -05:00
commit a02af84e03
19 changed files with 117 additions and 171 deletions
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7
arch/m68k/cpu/mcf5445x/pci.c
View File

@ -26,12 +26,11 @@
int pci_##rw##_cfg_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
u32 addr = 0; \
u16 cfg_type = 0; \
addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
u32 addr = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), \
PCI_FUNC(dev), offset); \
out_be32(hose->cfg_addr, addr); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
out_be32(hose->cfg_addr, addr & 0x7fffffff); \
out_be32(hose->cfg_addr, addr & ~PCI_CONF1_ENABLE); \
return 0; \
}

4
arch/x86/cpu/pci.c
View File

@ -20,7 +20,7 @@
int pci_x86_read_config(pci_dev_t bdf, uint offset, ulong *valuep,
enum pci_size_t size)
{
outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
outl(PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset), PCI_REG_ADDR);
switch (size) {
case PCI_SIZE_8:
*valuep = inb(PCI_REG_DATA + (offset & 3));
@ -39,7 +39,7 @@ int pci_x86_read_config(pci_dev_t bdf, uint offset, ulong *valuep,
int pci_x86_write_config(pci_dev_t bdf, uint offset, ulong value,
enum pci_size_t size)
{
outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
outl(PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset), PCI_REG_ADDR);
switch (size) {
case PCI_SIZE_8:
outb(value, PCI_REG_DATA + (offset & 3));

4
board/armltd/vexpress64/pcie.c
View File

@ -56,10 +56,6 @@
#define XR3PCI_ATR_TRSLID_PCIE_IO (0x020000)
#define XR3PCI_ATR_TRSLID_PCIE_MEMORY (0x000000)
#define XR3PCI_ECAM_OFFSET(b, d, o) (((b) << 20) | \
(PCI_SLOT(d) << 15) | \
(PCI_FUNC(d) << 12) | o)
#define JUNO_RESET_CTRL 0x1004
#define JUNO_RESET_CTRL_PHY BIT(0)
#define JUNO_RESET_CTRL_RC BIT(1)

12
drivers/pci/pci_auto.c
View File

@ -197,7 +197,7 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
dm_pci_read_config8(dev, PCI_IO_LIMIT, &io_32);
dm_pci_read_config8(dev, PCI_IO_BASE, &io_32);
io_32 &= PCI_IO_RANGE_TYPE_MASK;
/* Configure bus number registers */
@ -243,7 +243,7 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
cmdstat |= PCI_COMMAND_MEMORY;
} else {
/* We don't support prefetchable memory for now, so disable */
dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000 |
dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0xfff0 |
prefechable_64);
dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 |
prefechable_64);
@ -265,6 +265,14 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
(pci_io->bus_lower & 0xffff0000) >> 16);
cmdstat |= PCI_COMMAND_IO;
} else {
/* Disable I/O if unsupported */
dm_pci_write_config8(dev, PCI_IO_BASE, 0xf0 | io_32);
dm_pci_write_config8(dev, PCI_IO_LIMIT, 0x0 | io_32);
if (io_32 == PCI_IO_RANGE_TYPE_32) {
dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0x0);
dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0x0);
}
}
/* Enable memory and I/O accesses, enable bus master */

7
drivers/pci/pci_gt64120.c
View File

@ -48,7 +48,7 @@ static int gt_config_access(struct gt64120_pci_controller *gt,
{
unsigned int bus = PCI_BUS(bdf);
unsigned int dev = PCI_DEV(bdf);
unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
unsigned int func = PCI_FUNC(bdf);
u32 intr;
u32 addr;
u32 val;
@ -65,10 +65,7 @@ static int gt_config_access(struct gt64120_pci_controller *gt,
/* Clear cause register bits */
writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
addr = GT_PCI0_CFGADDR_CONFIGEN_BIT;
addr |= bus << GT_PCI0_CFGADDR_BUSNUM_SHF;
addr |= devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF;
addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF;
addr = PCI_CONF1_ADDRESS(bus, dev, func, where);
/* Setup address */
writel(addr, &gt->regs->pci0_cfgaddr);

4
drivers/pci/pci_mpc85xx.c
View File

@ -23,7 +23,7 @@ static int mpc85xx_pci_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
u32 addr;
addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
out_be32(priv->cfg_addr, addr);
sync();
*value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size);
@ -38,7 +38,7 @@ static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf,
struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
u32 addr;
addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
out_be32(priv->cfg_addr, addr);
sync();
out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size));

7
drivers/pci/pci_msc01.c
View File

@ -34,16 +34,13 @@ static int msc01_config_access(struct msc01_pci_controller *msc01,
void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS;
unsigned int bus = PCI_BUS(bdf);
unsigned int dev = PCI_DEV(bdf);
unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
unsigned int func = PCI_FUNC(bdf);
/* clear abort status */
__raw_writel(aborts, intstat);
/* setup address */
__raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) |
(dev << MSC01_PCI_CFGADDR_DNUM_SHF) |
(devfn << MSC01_PCI_CFGADDR_FNUM_SHF) |
((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF),
__raw_writel((PCI_CONF1_ADDRESS(bus, dev, func, where) & ~PCI_CONF1_ENABLE),
msc01->base + MSC01_PCI_CFGADDR_OFS);
/* perform access */

17
drivers/pci/pci_mvebu.c
View File

@ -46,15 +46,6 @@
#define PCIE_WIN5_BASE_OFF 0x1884
#define PCIE_WIN5_REMAP_OFF 0x188c
#define PCIE_CONF_ADDR_OFF 0x18f8
#define PCIE_CONF_ADDR_EN BIT(31)
#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
#define PCIE_CONF_ADDR(b, d, f, reg) \
(PCIE_CONF_BUS(b) | PCIE_CONF_DEV(d) | \
PCIE_CONF_FUNC(f) | PCIE_CONF_REG(reg) | \
PCIE_CONF_ADDR_EN)
#define PCIE_CONF_DATA_OFF 0x18fc
#define PCIE_MASK_OFF 0x1910
#define PCIE_MASK_ENABLE_INTS (0xf << 24)
@ -186,9 +177,9 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
* secondary bus with device number 1.
*/
if (busno == pcie->first_busno)
addr = PCIE_CONF_ADDR(pcie->sec_busno, 1, 0, offset);
addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset);
else
addr = PCIE_CONF_ADDR(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
/* write address */
writel(addr, pcie->base + PCIE_CONF_ADDR_OFF);
@ -284,9 +275,9 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
* secondary bus with device number 1.
*/
if (busno == pcie->first_busno)
addr = PCIE_CONF_ADDR(pcie->sec_busno, 1, 0, offset);
addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset);
else
addr = PCIE_CONF_ADDR(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
/* write address */
writel(addr, pcie->base + PCIE_CONF_ADDR_OFF);

61
drivers/pci/pci_octeontx.c
View File

@ -49,25 +49,6 @@ struct octeontx_pci {
struct resource bus;
};
static uintptr_t octeontx_cfg_addr(struct octeontx_pci *pcie,
int bus_offs, int shift_offs,
pci_dev_t bdf, uint offset)
{
u32 bus, dev, func;
uintptr_t address;
bus = PCI_BUS(bdf) + bus_offs;
dev = PCI_DEV(bdf);
func = PCI_FUNC(bdf);
address = (bus << (20 + shift_offs)) |
(dev << (15 + shift_offs)) |
(func << (12 + shift_offs)) | offset;
address += pcie->cfg.start;
return address;
}
static ulong readl_size(uintptr_t addr, enum pci_size_t size)
{
ulong val;
@ -123,9 +104,9 @@ static int octeontx_ecam_read_config(const struct udevice *bus, pci_dev_t bdf,
struct pci_controller *hose = dev_get_uclass_priv(bus);
uintptr_t address;
address = octeontx_cfg_addr(pcie, pcie->bus.start - hose->first_busno,
0, bdf, offset);
*valuep = readl_size(address, size);
address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + pcie->bus.start - hose->first_busno,
PCI_DEV(bdf), PCI_FUNC(bdf), offset);
*valuep = readl_size(pcie->cfg.start + address, size);
debug("%02x.%02x.%02x: u%d %x -> %lx\n",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, *valuep);
@ -141,9 +122,9 @@ static int octeontx_ecam_write_config(struct udevice *bus, pci_dev_t bdf,
struct pci_controller *hose = dev_get_uclass_priv(bus);
uintptr_t address;
address = octeontx_cfg_addr(pcie, pcie->bus.start - hose->first_busno,
0, bdf, offset);
writel_size(address, size, value);
address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + pcie->bus.start - hose->first_busno,
PCI_DEV(bdf), PCI_FUNC(bdf), offset);
writel_size(pcie->cfg.start + address, size, value);
debug("%02x.%02x.%02x: u%d %x <- %lx\n",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, value);
@ -162,17 +143,16 @@ static int octeontx_pem_read_config(const struct udevice *bus, pci_dev_t bdf,
u8 pri_bus = pcie->bus.start + 1 - hose->first_busno;
u32 bus_offs = (pri_bus << 16) | (pri_bus << 8) | (pri_bus << 0);
address = octeontx_cfg_addr(pcie, 1 - hose->first_busno, 4,
bdf, 0);
*valuep = pci_conv_32_to_size(~0UL, offset, size);
if (octeontx_bdf_invalid(bdf))
return -EPERM;
*valuep = readl_size(address + offset, size);
address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno,
PCI_DEV(bdf), PCI_FUNC(bdf), 0) << 4;
*valuep = readl_size(pcie->cfg.start + address + offset, size);
hdrtype = readb(address + PCI_HEADER_TYPE);
hdrtype = readb(pcie->cfg.start + address + PCI_HEADER_TYPE);
if (hdrtype == PCI_HEADER_TYPE_BRIDGE &&
offset >= PCI_PRIMARY_BUS &&
offset <= PCI_SUBORDINATE_BUS &&
@ -193,9 +173,10 @@ static int octeontx_pem_write_config(struct udevice *bus, pci_dev_t bdf,
u8 pri_bus = pcie->bus.start + 1 - hose->first_busno;
u32 bus_offs = (pri_bus << 16) | (pri_bus << 8) | (pri_bus << 0);
address = octeontx_cfg_addr(pcie, 1 - hose->first_busno, 4, bdf, 0);
address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno,
PCI_DEV(bdf), PCI_FUNC(bdf), 0) << 4;
hdrtype = readb(address + PCI_HEADER_TYPE);
hdrtype = readb(pcie->cfg.start + address + PCI_HEADER_TYPE);
if (hdrtype == PCI_HEADER_TYPE_BRIDGE &&
offset >= PCI_PRIMARY_BUS &&
offset <= PCI_SUBORDINATE_BUS &&
@ -205,7 +186,7 @@ static int octeontx_pem_write_config(struct udevice *bus, pci_dev_t bdf,
if (octeontx_bdf_invalid(bdf))
return -EPERM;
writel_size(address + offset, size, value);
writel_size(pcie->cfg.start + address + offset, size, value);
debug("%02x.%02x.%02x: u%d %x (%lx) <- %lx\n",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset,
@ -222,15 +203,14 @@ static int octeontx2_pem_read_config(const struct udevice *bus, pci_dev_t bdf,
struct pci_controller *hose = dev_get_uclass_priv(bus);
uintptr_t address;
address = octeontx_cfg_addr(pcie, 1 - hose->first_busno, 0,
bdf, 0);
*valuep = pci_conv_32_to_size(~0UL, offset, size);
if (octeontx_bdf_invalid(bdf))
return -EPERM;
*valuep = readl_size(address + offset, size);
address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno,
PCI_DEV(bdf), PCI_FUNC(bdf), offset);
*valuep = readl_size(pcie->cfg.start + address, size);
debug("%02x.%02x.%02x: u%d %x (%lx) -> %lx\n",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset,
@ -247,13 +227,12 @@ static int octeontx2_pem_write_config(struct udevice *bus, pci_dev_t bdf,
struct pci_controller *hose = dev_get_uclass_priv(bus);
uintptr_t address;
address = octeontx_cfg_addr(pcie, 1 - hose->first_busno, 0,
bdf, 0);
if (octeontx_bdf_invalid(bdf))
return -EPERM;
writel_size(address + offset, size, value);
address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno,
PCI_DEV(bdf), PCI_FUNC(bdf), offset);
writel_size(pcie->cfg.start + address, size, value);
debug("%02x.%02x.%02x: u%d %x (%lx) <- %lx\n",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset,

29
drivers/pci/pci_sh7751.c
View File

@ -74,33 +74,13 @@
#define p4_in(addr) (*addr)
#define p4_out(data, addr) (*addr) = (data)
static int sh7751_pci_addr_valid(pci_dev_t d, uint offset)
{
if (PCI_FUNC(d))
return -EINVAL;
return 0;
}
static u32 get_bus_address(const struct udevice *dev, pci_dev_t bdf, u32 offset)
{
return BIT(31) | (PCI_DEV(bdf) << 8) | (offset & ~3);
}
static int sh7751_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
uint offset, ulong *value,
enum pci_size_t size)
{
u32 addr, reg;
int ret;
ret = sh7751_pci_addr_valid(bdf, offset);
if (ret) {
*value = pci_get_ff(size);
return 0;
}
addr = get_bus_address(dev, bdf, offset);
addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
p4_out(addr, SH7751_PCIPAR);
reg = p4_in(SH7751_PCIPDR);
*value = pci_conv_32_to_size(reg, offset, size);
@ -113,13 +93,8 @@ static int sh7751_pci_write_config(struct udevice *dev, pci_dev_t bdf,
enum pci_size_t size)
{
u32 addr, reg, old;
int ret;
ret = sh7751_pci_addr_valid(bdf, offset);
if (ret)
return ret;
addr = get_bus_address(dev, bdf, offset);
addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
p4_out(addr, SH7751_PCIPAR);
old = p4_in(SH7751_PCIPDR);
reg = pci_conv_size_to_32(old, value, offset, size);

8
drivers/pci/pci_sh7780.c
View File

@ -34,9 +34,9 @@
int pci_sh4_read_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 *value)
{
u32 par_data = 0x80000000 | dev;
u32 par_data = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), offset);
p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
p4_out(par_data, SH7780_PCIPAR);
*value = p4_in(SH7780_PCIPDR);
return 0;
@ -45,9 +45,9 @@ int pci_sh4_read_config_dword(struct pci_controller *hose,
int pci_sh4_write_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value)
{
u32 par_data = 0x80000000 | dev;
u32 par_data = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), offset);
p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
p4_out(par_data, SH7780_PCIPAR);
p4_out(value, SH7780_PCIPDR);
return 0;
}

11
drivers/pci/pci_tegra.c
View File

@ -275,13 +275,6 @@ static void rp_writel(struct tegra_pcie_port *port, unsigned long value,
writel(value, port->regs.start + offset);
}
static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where)
{
return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) |
(PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) |
(where & 0xfc);
}
static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
int where, unsigned long *address)
{
@ -305,7 +298,9 @@ static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
return -EFAULT;
#endif
*address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where);
*address = pcie->cs.start +
(PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf),
PCI_FUNC(bdf), where) & ~PCI_CONF1_ENABLE);
return 0;
}
}

7
drivers/pci/pcie_brcmstb.c
View File

@ -97,9 +97,6 @@
#define PCIE_EXT_CFG_DATA 0x8000
#define PCIE_EXT_CFG_INDEX 0x9000
#define PCIE_EXT_BUSNUM_SHIFT 20
#define PCIE_EXT_SLOT_SHIFT 15
#define PCIE_EXT_FUNC_SHIFT 12
#define PCIE_RGR1_SW_INIT_1 0x9210
#define RGR1_SW_INIT_1_PERST_MASK 0x1
@ -227,9 +224,7 @@ static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf,
}
/* For devices, write to the config space index register */
idx = (pci_bus << PCIE_EXT_BUSNUM_SHIFT)
| (pci_dev << PCIE_EXT_SLOT_SHIFT)
| (pci_func << PCIE_EXT_FUNC_SHIFT);
idx = PCIE_ECAM_OFFSET(pci_bus, pci_dev, pci_func, 0);
writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
*paddress = pcie->base + PCIE_EXT_CFG_DATA + offset;

10
drivers/pci/pcie_fsl.c
View File

@ -58,8 +58,9 @@ static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
return 0;
}
bdf = bdf - PCI_BDF(dev_seq(bus), 0, 0);
val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus),
PCI_DEV(bdf), PCI_FUNC(bdf),
offset);
out_be32(&regs->cfg_addr, val);
sync();
@ -94,8 +95,9 @@ static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
if (fsl_pcie_addr_valid(pcie, bdf))
return 0;
bdf = bdf - PCI_BDF(dev_seq(bus), 0, 0);
val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus),
PCI_DEV(bdf), PCI_FUNC(bdf),
offset);
out_be32(&regs->cfg_addr, val);
sync();

17
drivers/pci/pcie_iproc.c
View File

@ -24,15 +24,7 @@
#define CFG_IND_ADDR_MASK 0x00001ffc
#define CFG_ADDR_BUS_NUM_SHIFT 20
#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
#define CFG_ADDR_DEV_NUM_SHIFT 15
#define CFG_ADDR_DEV_NUM_MASK 0x000f8000
#define CFG_ADDR_FUNC_NUM_SHIFT 12
#define CFG_ADDR_FUNC_NUM_MASK 0x00007000
#define CFG_ADDR_REG_NUM_SHIFT 2
#define CFG_ADDR_REG_NUM_MASK 0x00000ffc
#define CFG_ADDR_CFG_TYPE_SHIFT 0
#define CFG_ADDR_CFG_ECAM_MASK 0xfffffffc
#define CFG_ADDR_CFG_TYPE_MASK 0x00000003
#define IPROC_PCI_PM_CAP 0x48
@ -473,11 +465,8 @@ static int iproc_pcie_map_ep_cfg_reg(const struct udevice *udev, pci_dev_t bdf,
return -ENODEV;
/* EP device access */
val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
(slot << CFG_ADDR_DEV_NUM_SHIFT) |
(fn << CFG_ADDR_FUNC_NUM_SHIFT) |
(where & CFG_ADDR_REG_NUM_MASK) |
(1 & CFG_ADDR_CFG_TYPE_MASK);
val = (PCIE_ECAM_OFFSET(busno, slot, fn, where) & CFG_ADDR_CFG_ECAM_MASK)
| (1 & CFG_ADDR_CFG_TYPE_MASK);
iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);

17
drivers/pci/pcie_mediatek.c
View File

@ -41,10 +41,6 @@
#define PCIE_BAR_ENABLE BIT(0)
#define PCIE_REVISION_ID BIT(0)
#define PCIE_CLASS_CODE (0x60400 << 8)
#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
((((regn) >> 8) & GENMASK(3, 0)) << 24))
#define PCIE_CONF_ADDR(regn, bdf) \
(PCIE_CONF_REG(regn) | (bdf))
/* MediaTek specific configuration registers */
#define PCIE_FTS_NUM 0x70c
@ -147,8 +143,11 @@ static int mtk_pcie_config_address(const struct udevice *udev, pci_dev_t bdf,
uint offset, void **paddress)
{
struct mtk_pcie *pcie = dev_get_priv(udev);
u32 val;
writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR);
val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf),
PCI_FUNC(bdf), offset) & ~PCI_CONF1_ENABLE;
writel(val, pcie->base + PCIE_CFG_ADDR);
*paddress = pcie->base + PCIE_CFG_DATA + (offset & 3);
return 0;
@ -330,7 +329,6 @@ static void mtk_pcie_port_free(struct mtk_pcie_port *port)
static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
{
struct mtk_pcie *pcie = port->pcie;
u32 slot = PCI_DEV(port->slot << 11);
u32 val;
int err;
@ -357,13 +355,14 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
/* configure FC credit */
writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot),
pcie->base + PCIE_CFG_ADDR);
val = PCI_CONF1_EXT_ADDRESS(0, port->slot, 0, PCIE_FC_CREDIT) & ~PCI_CONF1_ENABLE;
writel(val, pcie->base + PCIE_CFG_ADDR);
clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK,
PCIE_FC_CREDIT_VAL(0x806c));
/* configure RC FTS number to 250 when it leaves L0s */
writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR);
val = PCI_CONF1_EXT_ADDRESS(0, port->slot, 0, PCIE_FTS_NUM) & ~PCI_CONF1_ENABLE;
writel(val, pcie->base + PCIE_CFG_ADDR);
clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK,
PCIE_FTS_NUM_L0(0x50));

12
include/gt64120.h
View File

@ -491,18 +491,6 @@
#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK
#define GT_PCI0_CFGADDR_REGNUM_SHF 2
#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8
#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
#define GT_PCI0_CFGADDR_DEVNUM_SHF 11
#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
#define GT_PCI0_CFGADDR_BUSNUM_SHF 16
#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31
#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK
#define GT_PCI0_CMD_MBYTESWAP_SHF 0
#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK

9
include/msc01.h
View File

@ -71,15 +71,6 @@
#define MSC01_PCI_INTSTAT_MA_SHF 7
#define MSC01_PCI_INTSTAT_MA_MSK (0x1 << MSC01_PCI_INTSTAT_MA_SHF)
#define MSC01_PCI_CFGADDR_BNUM_SHF 16
#define MSC01_PCI_CFGADDR_BNUM_MSK (0xff << MSC01_PCI_CFGADDR_BNUM_SHF)
#define MSC01_PCI_CFGADDR_DNUM_SHF 11
#define MSC01_PCI_CFGADDR_DNUM_MSK (0x1f << MSC01_PCI_CFGADDR_DNUM_SHF)
#define MSC01_PCI_CFGADDR_FNUM_SHF 8
#define MSC01_PCI_CFGADDR_FNUM_MSK (0x3 << MSC01_PCI_CFGADDR_FNUM_SHF)
#define MSC01_PCI_CFGADDR_RNUM_SHF 2
#define MSC01_PCI_CFGADDR_RNUM_MSK (0x3f << MSC01_PCI_CFGADDR_RNUM_SHF)
#define MSC01_PCI_HEAD0_VENDORID_SHF 0
#define MSC01_PCI_HEAD0_DEVICEID_SHF 16

45
include/pci.h
View File

@ -522,6 +522,51 @@
#include <pci_ids.h>
/*
* Config Address for PCI Configuration Mechanism #1
*
* See PCI Local Bus Specification, Revision 3.0,
* Section 3.2.2.3.2, Figure 3-2, p. 50.
*/
#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
#define PCI_CONF1_DEV_SHIFT 11 /* Device number */
#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
#define PCI_CONF1_BUS_MASK 0xff
#define PCI_CONF1_DEV_MASK 0x1f
#define PCI_CONF1_FUNC_MASK 0x7
#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
#define PCI_CONF1_ENABLE BIT(31)
#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
(PCI_CONF1_ENABLE | \
PCI_CONF1_BUS(bus) | \
PCI_CONF1_DEV(dev) | \
PCI_CONF1_FUNC(func) | \
PCI_CONF1_REG(reg))
/*
* Extension of PCI Config Address for accessing extended PCIe registers
*
* No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
* or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
* are used for specifying additional 4 high bits of PCI Express register.
*/
#define PCI_CONF1_EXT_REG_SHIFT 16
#define PCI_CONF1_EXT_REG_MASK 0xf00
#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
(PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
PCI_CONF1_EXT_REG(reg))
/*
* Enhanced Configuration Access Mechanism (ECAM)
*