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rockchip: clk: rk3368: implement DPLL (DRAM PLL) support

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To implement a TPL stage (incl. its DRAM controller setup) for the
RK3368, we'll want to configure the DPLL (DRAM PLL).

This commit implements setting the DPLL (CLK_DDR) and provides PLL
configuration details for the common DRAM operating speeds found on
RK3368 boards.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Philipp Tomsich 2017-06-23 00:01:10 +02:00
parent 4bebf94e85
commit a00dfa042d
1 changed files with 35 additions and 0 deletions
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35
drivers/clk/rockchip/clk_rk3368.c
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@ -250,6 +250,37 @@ static ulong rk3368_clk_get_rate(struct clk *clk)
return rate;
}
static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
{
const struct pll_div *dpll_cfg = NULL;
const ulong MHz = 1000000;
/* Fout = ((Fin /NR) * NF )/ NO */
static const struct pll_div dpll_1200 =
PLL_DIVISORS(1200 * MHz, 1, 1);
static const struct pll_div dpll_1332 =
PLL_DIVISORS(1332 * MHz, 2, 1);
static const struct pll_div dpll_1600 =
PLL_DIVISORS(1600 * MHz, 3, 2);
switch (set_rate) {
case 1200*MHz:
dpll_cfg = &dpll_1200;
break;
case 1332*MHz:
dpll_cfg = &dpll_1332;
break;
case 1600*MHz:
dpll_cfg = &dpll_1600;
break;
default:
error("Unsupported SDRAM frequency!,%ld\n", set_rate);
}
rkclk_set_pll(cru, DPLL, dpll_cfg);
return set_rate;
}
static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
{
struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
@ -257,6 +288,10 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
switch (clk->id) {
case CLK_DDR:
ret = rk3368_ddr_set_clk(priv->cru, rate);
break;
case SCLK_SDMMC:
case SCLK_EMMC:
ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);