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fsl_upm: Add MxMR/MDR synchronization

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According to Freescale reference manuals (eg section "13.4.4.2
Programming the UPMs" of the P4080 Reference Manual):

"Since the result of any update to the MxMR/MDR register must be in
effect before the dummy read or write to the UPM region, a write to
MxMR/MDR should be followed immediately by a read of MxMR/MDR."

The UPM on a custom P4080-based board did not work without performing
a read of MxMR/MDR after a write.

Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
John Schmoller 2010-12-02 11:43:10 -06:00 committed by Kumar Gala
parent 72c96a6802
commit 9fd84915a9
1 changed files with 2 additions and 0 deletions
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2
drivers/mtd/nand/fsl_upm.c
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@ -21,6 +21,7 @@
static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
{
clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
(void)in_be32(upm->mxmr);
}
static void fsl_upm_end_pattern(struct fsl_upm *upm)
@ -35,6 +36,7 @@ static void fsl_upm_run_pattern(struct fsl_upm *upm, int width,
void __iomem *io_addr, u32 mar)
{
out_be32(upm->mar, mar);
(void)in_be32(upm->mar);
switch (width) {
case 8:
out_8(io_addr, 0x0);