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Merge commit 'ef5ba2cef4a08b68caaa9215fcac142d3025bbf7' of https://github.com/tienfong/uboot_mainline

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This commit is contained in:
Tom Rini
2022-07-01 09:14:32 -04:00
parent 085fea0b65 ef5ba2cef4
commit 9fcc2fb3fe
28 changed files with 1170 additions and 22 deletions
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2
arch/arm/dts/Makefile
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@@ -418,6 +418,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex_socdk.dtb \
socfpga_arria5_secu1.dtb \
socfpga_arria5_socdk.dtb \
socfpga_arria10_chameleonv3_270_3.dtb \
socfpga_arria10_chameleonv3_480_2.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_is1.dtb \

90
arch/arm/dts/socfpga_arria10_chameleonv3.dts Normal file
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@@ -0,0 +1,90 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
/dts-v1/;
#include "socfpga_arria10_mercury_aa1.dtsi"
/ {
model = "Google Chameleon V3";
compatible = "google,chameleon-v3",
"altr,socfpga-arria10", "altr,socfpga";
aliases {
serial0 = &uart0;
i2c0 = &i2c0;
i2c1 = &i2c1;
};
};
&gmac0 {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&i2c0 {
status = "okay";
ssm2603: ssm2603@1a {
compatible = "adi,ssm2603";
reg = <0x1a>;
};
};
&i2c1 {
status = "okay";
u80: u80@21 {
compatible = "nxp,pca9535";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"SOM_AUD_MUTE",
"DP1_OUT_CEC_EN",
"DP2_OUT_CEC_EN",
"DP1_SOM_PS8469_CAD",
"DPD_SOM_PS8469_CAD",
"DP_OUT_PWR_EN",
"STM32_RST_L",
"STM32_BOOT0",
"FPGA_PROT",
"STM32_FPGA_COMM0",
"TP119",
"TP120",
"TP121",
"TP122",
"TP123",
"TP124";
};
};
&mmc {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};

8
arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi Normal file
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@@ -0,0 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
#include "socfpga_arria10_chameleonv3_270_3_handoff.h"
#include "socfpga_arria10-handoff.dtsi"
#include "socfpga_arria10_handoff_u-boot.dtsi"
#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"

5
arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts Normal file
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@@ -0,0 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
#include "socfpga_arria10_chameleonv3.dts"

305
arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h Normal file
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@@ -0,0 +1,305 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Intel Arria 10 SoCFPGA configuration
*/
#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
#define __SOCFPGA_ARRIA10_CONFIG_H__
/* Clocks */
#define CB_INTOSC_LS_CLK_HZ 60000000
#define EMAC0_CLK_HZ 250000000
#define EMAC1_CLK_HZ 250000000
#define EMAC2_CLK_HZ 250000000
#define EOSC1_CLK_HZ 33330000
#define F2H_FREE_CLK_HZ 200000000
#define H2F_USER0_CLK_HZ 200000000
#define H2F_USER1_CLK_HZ 100000000
#define L3_MAIN_FREE_CLK_HZ 200000000
#define SDMMC_CLK_HZ 200000000
#define TPIU_CLK_HZ 100000000
#define MAINPLLGRP_CNTR15CLK_CNT 900
#define MAINPLLGRP_CNTR2CLK_CNT 900
#define MAINPLLGRP_CNTR3CLK_CNT 900
#define MAINPLLGRP_CNTR4CLK_CNT 900
#define MAINPLLGRP_CNTR5CLK_CNT 900
#define MAINPLLGRP_CNTR6CLK_CNT 7
#define MAINPLLGRP_CNTR7CLK_CNT 7
#define MAINPLLGRP_CNTR7CLK_SRC 0
#define MAINPLLGRP_CNTR8CLK_CNT 15
#define MAINPLLGRP_CNTR9CLK_CNT 900
#define MAINPLLGRP_CNTR9CLK_SRC 0
#define MAINPLLGRP_MPUCLK_CNT 0
#define MAINPLLGRP_MPUCLK_SRC 0
#define MAINPLLGRP_NOCCLK_CNT 0
#define MAINPLLGRP_NOCCLK_SRC 0
#define MAINPLLGRP_NOCDIV_CSATCLK 0
#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
#define MAINPLLGRP_NOCDIV_CSTRACECLK 0
#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
#define MAINPLLGRP_NOCDIV_L4MPCLK 1
#define MAINPLLGRP_NOCDIV_L4SPCLK 2
#define MAINPLLGRP_VCO0_PSRC 0
#define MAINPLLGRP_VCO1_DENOM 32
#define MAINPLLGRP_VCO1_NUMER 1584
#define PERPLLGRP_CNTR2CLK_CNT 5
#define PERPLLGRP_CNTR2CLK_SRC 1
#define PERPLLGRP_CNTR3CLK_CNT 900
#define PERPLLGRP_CNTR3CLK_SRC 1
#define PERPLLGRP_CNTR4CLK_CNT 14
#define PERPLLGRP_CNTR4CLK_SRC 1
#define PERPLLGRP_CNTR5CLK_CNT 374
#define PERPLLGRP_CNTR5CLK_SRC 1
#define PERPLLGRP_CNTR6CLK_CNT 900
#define PERPLLGRP_CNTR6CLK_SRC 0
#define PERPLLGRP_CNTR7CLK_CNT 900
#define PERPLLGRP_CNTR8CLK_CNT 900
#define PERPLLGRP_CNTR8CLK_SRC 0
#define PERPLLGRP_CNTR9CLK_CNT 900
#define PERPLLGRP_EMACCTL_EMAC0SEL 0
#define PERPLLGRP_EMACCTL_EMAC1SEL 0
#define PERPLLGRP_EMACCTL_EMAC2SEL 0
#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
#define PERPLLGRP_VCO0_PSRC 0
#define PERPLLGRP_VCO1_DENOM 32
#define PERPLLGRP_VCO1_NUMER 1485
#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
#define ALTERAGRP_MPUCLK_MAINCNT 1
#define ALTERAGRP_MPUCLK_PERICNT 900
#define ALTERAGRP_NOCCLK_MAINCNT 7
#define ALTERAGRP_NOCCLK_PERICNT 900
#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
(ALTERAGRP_MPUCLK_MAINCNT))
#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
(ALTERAGRP_NOCCLK_MAINCNT))
/* Pin Mux Configuration */
#define CONFIG_IO_10_INPUT_BUF_EN 1
#define CONFIG_IO_10_PD_DRV_STRG 10
#define CONFIG_IO_10_PD_SLW_RT 1
#define CONFIG_IO_10_PU_DRV_STRG 8
#define CONFIG_IO_10_PU_SLW_RT 1
#define CONFIG_IO_10_RTRIM 1
#define CONFIG_IO_10_WK_PU_EN 0
#define CONFIG_IO_11_INPUT_BUF_EN 1
#define CONFIG_IO_11_PD_DRV_STRG 10
#define CONFIG_IO_11_PD_SLW_RT 1
#define CONFIG_IO_11_PU_DRV_STRG 8
#define CONFIG_IO_11_PU_SLW_RT 1
#define CONFIG_IO_11_RTRIM 1
#define CONFIG_IO_11_WK_PU_EN 0
#define CONFIG_IO_12_INPUT_BUF_EN 0
#define CONFIG_IO_12_PD_DRV_STRG 0
#define CONFIG_IO_12_PD_SLW_RT 0
#define CONFIG_IO_12_PU_DRV_STRG 0
#define CONFIG_IO_12_PU_SLW_RT 0
#define CONFIG_IO_12_RTRIM 1
#define CONFIG_IO_12_WK_PU_EN 1
#define CONFIG_IO_13_INPUT_BUF_EN 0
#define CONFIG_IO_13_PD_DRV_STRG 0
#define CONFIG_IO_13_PD_SLW_RT 0
#define CONFIG_IO_13_PU_DRV_STRG 0
#define CONFIG_IO_13_PU_SLW_RT 0
#define CONFIG_IO_13_RTRIM 1
#define CONFIG_IO_13_WK_PU_EN 1
#define CONFIG_IO_14_INPUT_BUF_EN 0
#define CONFIG_IO_14_PD_DRV_STRG 0
#define CONFIG_IO_14_PD_SLW_RT 0
#define CONFIG_IO_14_PU_DRV_STRG 0
#define CONFIG_IO_14_PU_SLW_RT 0
#define CONFIG_IO_14_RTRIM 1
#define CONFIG_IO_14_WK_PU_EN 1
#define CONFIG_IO_15_INPUT_BUF_EN 0
#define CONFIG_IO_15_PD_DRV_STRG 0
#define CONFIG_IO_15_PD_SLW_RT 0
#define CONFIG_IO_15_PU_DRV_STRG 0
#define CONFIG_IO_15_PU_SLW_RT 0
#define CONFIG_IO_15_RTRIM 1
#define CONFIG_IO_15_WK_PU_EN 1
#define CONFIG_IO_16_INPUT_BUF_EN 0
#define CONFIG_IO_16_PD_DRV_STRG 10
#define CONFIG_IO_16_PD_SLW_RT 1
#define CONFIG_IO_16_PU_DRV_STRG 8
#define CONFIG_IO_16_PU_SLW_RT 1
#define CONFIG_IO_16_RTRIM 1
#define CONFIG_IO_16_WK_PU_EN 0
#define CONFIG_IO_17_INPUT_BUF_EN 1
#define CONFIG_IO_17_PD_DRV_STRG 10
#define CONFIG_IO_17_PD_SLW_RT 1
#define CONFIG_IO_17_PU_DRV_STRG 8
#define CONFIG_IO_17_PU_SLW_RT 1
#define CONFIG_IO_17_RTRIM 1
#define CONFIG_IO_17_WK_PU_EN 0
#define CONFIG_IO_1_INPUT_BUF_EN 1
#define CONFIG_IO_1_PD_DRV_STRG 10
#define CONFIG_IO_1_PD_SLW_RT 0
#define CONFIG_IO_1_PU_DRV_STRG 8
#define CONFIG_IO_1_PU_SLW_RT 0
#define CONFIG_IO_1_RTRIM 1
#define CONFIG_IO_1_WK_PU_EN 1
#define CONFIG_IO_2_INPUT_BUF_EN 1
#define CONFIG_IO_2_PD_DRV_STRG 10
#define CONFIG_IO_2_PD_SLW_RT 0
#define CONFIG_IO_2_PU_DRV_STRG 8
#define CONFIG_IO_2_PU_SLW_RT 0
#define CONFIG_IO_2_RTRIM 1
#define CONFIG_IO_2_WK_PU_EN 1
#define CONFIG_IO_3_INPUT_BUF_EN 1
#define CONFIG_IO_3_PD_DRV_STRG 10
#define CONFIG_IO_3_PD_SLW_RT 0
#define CONFIG_IO_3_PU_DRV_STRG 8
#define CONFIG_IO_3_PU_SLW_RT 0
#define CONFIG_IO_3_RTRIM 1
#define CONFIG_IO_3_WK_PU_EN 1
#define CONFIG_IO_4_INPUT_BUF_EN 1
#define CONFIG_IO_4_PD_DRV_STRG 10
#define CONFIG_IO_4_PD_SLW_RT 1
#define CONFIG_IO_4_PU_DRV_STRG 8
#define CONFIG_IO_4_PU_SLW_RT 1
#define CONFIG_IO_4_RTRIM 1
#define CONFIG_IO_4_WK_PU_EN 0
#define CONFIG_IO_5_INPUT_BUF_EN 1
#define CONFIG_IO_5_PD_DRV_STRG 10
#define CONFIG_IO_5_PD_SLW_RT 1
#define CONFIG_IO_5_PU_DRV_STRG 8
#define CONFIG_IO_5_PU_SLW_RT 1
#define CONFIG_IO_5_RTRIM 1
#define CONFIG_IO_5_WK_PU_EN 0
#define CONFIG_IO_6_INPUT_BUF_EN 0
#define CONFIG_IO_6_PD_DRV_STRG 10
#define CONFIG_IO_6_PD_SLW_RT 1
#define CONFIG_IO_6_PU_DRV_STRG 8
#define CONFIG_IO_6_PU_SLW_RT 1
#define CONFIG_IO_6_RTRIM 1
#define CONFIG_IO_6_WK_PU_EN 0
#define CONFIG_IO_7_INPUT_BUF_EN 1
#define CONFIG_IO_7_PD_DRV_STRG 10
#define CONFIG_IO_7_PD_SLW_RT 1
#define CONFIG_IO_7_PU_DRV_STRG 8
#define CONFIG_IO_7_PU_SLW_RT 1
#define CONFIG_IO_7_RTRIM 1
#define CONFIG_IO_7_WK_PU_EN 0
#define CONFIG_IO_8_INPUT_BUF_EN 1
#define CONFIG_IO_8_PD_DRV_STRG 10
#define CONFIG_IO_8_PD_SLW_RT 1
#define CONFIG_IO_8_PU_DRV_STRG 8
#define CONFIG_IO_8_PU_SLW_RT 1
#define CONFIG_IO_8_RTRIM 1
#define CONFIG_IO_8_WK_PU_EN 0
#define CONFIG_IO_9_INPUT_BUF_EN 1
#define CONFIG_IO_9_PD_DRV_STRG 10
#define CONFIG_IO_9_PD_SLW_RT 1
#define CONFIG_IO_9_PU_DRV_STRG 8
#define CONFIG_IO_9_PU_SLW_RT 1
#define CONFIG_IO_9_RTRIM 1
#define CONFIG_IO_9_WK_PU_EN 0
#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
#define PINMUX_DEDICATED_IO_10_SEL 15
#define PINMUX_DEDICATED_IO_11_SEL 15
#define PINMUX_DEDICATED_IO_12_SEL 1
#define PINMUX_DEDICATED_IO_13_SEL 1
#define PINMUX_DEDICATED_IO_14_SEL 10
#define PINMUX_DEDICATED_IO_15_SEL 10
#define PINMUX_DEDICATED_IO_16_SEL 13
#define PINMUX_DEDICATED_IO_17_SEL 13
#define PINMUX_DEDICATED_IO_4_SEL 8
#define PINMUX_DEDICATED_IO_5_SEL 8
#define PINMUX_DEDICATED_IO_6_SEL 8
#define PINMUX_DEDICATED_IO_7_SEL 8
#define PINMUX_DEDICATED_IO_8_SEL 8
#define PINMUX_DEDICATED_IO_9_SEL 8
#define PINMUX_I2C0_USEFPGA_SEL 1
#define PINMUX_I2C1_USEFPGA_SEL 0
#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
#define PINMUX_I2CEMAC1_USEFPGA_SEL 0
#define PINMUX_I2CEMAC2_USEFPGA_SEL 0
#define PINMUX_NAND_USEFPGA_SEL 0
#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0
#define PINMUX_QSPI_USEFPGA_SEL 0
#define PINMUX_RGMII0_USEFPGA_SEL 0
#define PINMUX_RGMII1_USEFPGA_SEL 0
#define PINMUX_RGMII2_USEFPGA_SEL 0
#define PINMUX_SDMMC_USEFPGA_SEL 0
#define PINMUX_SHARED_IO_Q1_10_SEL 8
#define PINMUX_SHARED_IO_Q1_11_SEL 8
#define PINMUX_SHARED_IO_Q1_12_SEL 8
#define PINMUX_SHARED_IO_Q1_1_SEL 8
#define PINMUX_SHARED_IO_Q1_2_SEL 8
#define PINMUX_SHARED_IO_Q1_3_SEL 8
#define PINMUX_SHARED_IO_Q1_4_SEL 8
#define PINMUX_SHARED_IO_Q1_5_SEL 8
#define PINMUX_SHARED_IO_Q1_6_SEL 8
#define PINMUX_SHARED_IO_Q1_7_SEL 8
#define PINMUX_SHARED_IO_Q1_8_SEL 8
#define PINMUX_SHARED_IO_Q1_9_SEL 8
#define PINMUX_SHARED_IO_Q2_10_SEL 4
#define PINMUX_SHARED_IO_Q2_11_SEL 4
#define PINMUX_SHARED_IO_Q2_12_SEL 4
#define PINMUX_SHARED_IO_Q2_1_SEL 4
#define PINMUX_SHARED_IO_Q2_2_SEL 4
#define PINMUX_SHARED_IO_Q2_3_SEL 4
#define PINMUX_SHARED_IO_Q2_4_SEL 4
#define PINMUX_SHARED_IO_Q2_5_SEL 4
#define PINMUX_SHARED_IO_Q2_6_SEL 4
#define PINMUX_SHARED_IO_Q2_7_SEL 4
#define PINMUX_SHARED_IO_Q2_8_SEL 4
#define PINMUX_SHARED_IO_Q2_9_SEL 4
#define PINMUX_SHARED_IO_Q3_10_SEL 15
#define PINMUX_SHARED_IO_Q3_11_SEL 1
#define PINMUX_SHARED_IO_Q3_12_SEL 1
#define PINMUX_SHARED_IO_Q3_1_SEL 15
#define PINMUX_SHARED_IO_Q3_2_SEL 15
#define PINMUX_SHARED_IO_Q3_3_SEL 15
#define PINMUX_SHARED_IO_Q3_4_SEL 15
#define PINMUX_SHARED_IO_Q3_5_SEL 15
#define PINMUX_SHARED_IO_Q3_6_SEL 15
#define PINMUX_SHARED_IO_Q3_7_SEL 0
#define PINMUX_SHARED_IO_Q3_8_SEL 0
#define PINMUX_SHARED_IO_Q3_9_SEL 15
#define PINMUX_SHARED_IO_Q4_10_SEL 10
#define PINMUX_SHARED_IO_Q4_11_SEL 10
#define PINMUX_SHARED_IO_Q4_12_SEL 10
#define PINMUX_SHARED_IO_Q4_1_SEL 10
#define PINMUX_SHARED_IO_Q4_2_SEL 10
#define PINMUX_SHARED_IO_Q4_3_SEL 10
#define PINMUX_SHARED_IO_Q4_4_SEL 10
#define PINMUX_SHARED_IO_Q4_5_SEL 10
#define PINMUX_SHARED_IO_Q4_6_SEL 10
#define PINMUX_SHARED_IO_Q4_7_SEL 10
#define PINMUX_SHARED_IO_Q4_8_SEL 10
#define PINMUX_SHARED_IO_Q4_9_SEL 10
#define PINMUX_SPIM0_USEFPGA_SEL 0
#define PINMUX_SPIM1_USEFPGA_SEL 0
#define PINMUX_SPIS0_USEFPGA_SEL 0
#define PINMUX_SPIS1_USEFPGA_SEL 0
#define PINMUX_UART0_USEFPGA_SEL 1
#define PINMUX_UART1_USEFPGA_SEL 0
#define PINMUX_USB0_USEFPGA_SEL 0
#define PINMUX_USB1_USEFPGA_SEL 0
/* Bridge Configuration */
#define F2H_AXI_SLAVE 1
#define F2SDRAM0_AXI_SLAVE 1
#define F2SDRAM1_AXI_SLAVE 1
#define F2SDRAM2_AXI_SLAVE 1
#define H2F_AXI_MASTER 1
#define LWH2F_AXI_MASTER 1
/* Voltage Select for Config IO */
#define CONFIG_IO_BANK_VSEL \
(((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
(CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
/* Macro for Config IO bit mapping */
#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
((NAME ## _WK_PU_EN & 0x1) << 16) | \
((NAME ## _PU_SLW_RT & 0x1) << 13) | \
((NAME ## _PU_DRV_STRG & 0xf) << 8) | \
((NAME ## _PD_SLW_RT & 0x1) << 5) | \
(NAME ## _PD_DRV_STRG & 0x1f))
#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */

8
arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi Normal file
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@@ -0,0 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
#include "socfpga_arria10_chameleonv3_480_2_handoff.h"
#include "socfpga_arria10-handoff.dtsi"
#include "socfpga_arria10_handoff_u-boot.dtsi"
#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"

5
arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts Normal file
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@@ -0,0 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
#include "socfpga_arria10_chameleonv3.dts"

305
arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h Normal file
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@@ -0,0 +1,305 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Intel Arria 10 SoCFPGA configuration
*/
#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
#define __SOCFPGA_ARRIA10_CONFIG_H__
/* Clocks */
#define CB_INTOSC_LS_CLK_HZ 60000000
#define EMAC0_CLK_HZ 250000000
#define EMAC1_CLK_HZ 250000000
#define EMAC2_CLK_HZ 250000000
#define EOSC1_CLK_HZ 33330000
#define F2H_FREE_CLK_HZ 200000000
#define H2F_USER0_CLK_HZ 200000000
#define H2F_USER1_CLK_HZ 100000000
#define L3_MAIN_FREE_CLK_HZ 200000000
#define SDMMC_CLK_HZ 200000000
#define TPIU_CLK_HZ 100000000
#define MAINPLLGRP_CNTR15CLK_CNT 900
#define MAINPLLGRP_CNTR2CLK_CNT 900
#define MAINPLLGRP_CNTR3CLK_CNT 900
#define MAINPLLGRP_CNTR4CLK_CNT 900
#define MAINPLLGRP_CNTR5CLK_CNT 900
#define MAINPLLGRP_CNTR6CLK_CNT 9
#define MAINPLLGRP_CNTR7CLK_CNT 9
#define MAINPLLGRP_CNTR7CLK_SRC 0
#define MAINPLLGRP_CNTR8CLK_CNT 19
#define MAINPLLGRP_CNTR9CLK_CNT 900
#define MAINPLLGRP_CNTR9CLK_SRC 0
#define MAINPLLGRP_MPUCLK_CNT 0
#define MAINPLLGRP_MPUCLK_SRC 0
#define MAINPLLGRP_NOCCLK_CNT 0
#define MAINPLLGRP_NOCCLK_SRC 0
#define MAINPLLGRP_NOCDIV_CSATCLK 0
#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
#define MAINPLLGRP_NOCDIV_CSTRACECLK 0
#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
#define MAINPLLGRP_NOCDIV_L4MPCLK 1
#define MAINPLLGRP_NOCDIV_L4SPCLK 2
#define MAINPLLGRP_VCO0_PSRC 0
#define MAINPLLGRP_VCO1_DENOM 32
#define MAINPLLGRP_VCO1_NUMER 1980
#define PERPLLGRP_CNTR2CLK_CNT 7
#define PERPLLGRP_CNTR2CLK_SRC 1
#define PERPLLGRP_CNTR3CLK_CNT 900
#define PERPLLGRP_CNTR3CLK_SRC 1
#define PERPLLGRP_CNTR4CLK_CNT 19
#define PERPLLGRP_CNTR4CLK_SRC 1
#define PERPLLGRP_CNTR5CLK_CNT 499
#define PERPLLGRP_CNTR5CLK_SRC 1
#define PERPLLGRP_CNTR6CLK_CNT 900
#define PERPLLGRP_CNTR6CLK_SRC 0
#define PERPLLGRP_CNTR7CLK_CNT 900
#define PERPLLGRP_CNTR8CLK_CNT 900
#define PERPLLGRP_CNTR8CLK_SRC 0
#define PERPLLGRP_CNTR9CLK_CNT 900
#define PERPLLGRP_EMACCTL_EMAC0SEL 0
#define PERPLLGRP_EMACCTL_EMAC1SEL 0
#define PERPLLGRP_EMACCTL_EMAC2SEL 0
#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
#define PERPLLGRP_VCO0_PSRC 0
#define PERPLLGRP_VCO1_DENOM 32
#define PERPLLGRP_VCO1_NUMER 1980
#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
#define ALTERAGRP_MPUCLK_MAINCNT 1
#define ALTERAGRP_MPUCLK_PERICNT 900
#define ALTERAGRP_NOCCLK_MAINCNT 9
#define ALTERAGRP_NOCCLK_PERICNT 900
#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
(ALTERAGRP_MPUCLK_MAINCNT))
#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
(ALTERAGRP_NOCCLK_MAINCNT))
/* Pin Mux Configuration */
#define CONFIG_IO_10_INPUT_BUF_EN 1
#define CONFIG_IO_10_PD_DRV_STRG 10
#define CONFIG_IO_10_PD_SLW_RT 1
#define CONFIG_IO_10_PU_DRV_STRG 8
#define CONFIG_IO_10_PU_SLW_RT 1
#define CONFIG_IO_10_RTRIM 1
#define CONFIG_IO_10_WK_PU_EN 0
#define CONFIG_IO_11_INPUT_BUF_EN 1
#define CONFIG_IO_11_PD_DRV_STRG 10
#define CONFIG_IO_11_PD_SLW_RT 1
#define CONFIG_IO_11_PU_DRV_STRG 8
#define CONFIG_IO_11_PU_SLW_RT 1
#define CONFIG_IO_11_RTRIM 1
#define CONFIG_IO_11_WK_PU_EN 0
#define CONFIG_IO_12_INPUT_BUF_EN 0
#define CONFIG_IO_12_PD_DRV_STRG 0
#define CONFIG_IO_12_PD_SLW_RT 0
#define CONFIG_IO_12_PU_DRV_STRG 0
#define CONFIG_IO_12_PU_SLW_RT 0
#define CONFIG_IO_12_RTRIM 1
#define CONFIG_IO_12_WK_PU_EN 1
#define CONFIG_IO_13_INPUT_BUF_EN 0
#define CONFIG_IO_13_PD_DRV_STRG 0
#define CONFIG_IO_13_PD_SLW_RT 0
#define CONFIG_IO_13_PU_DRV_STRG 0
#define CONFIG_IO_13_PU_SLW_RT 0
#define CONFIG_IO_13_RTRIM 1
#define CONFIG_IO_13_WK_PU_EN 1
#define CONFIG_IO_14_INPUT_BUF_EN 0
#define CONFIG_IO_14_PD_DRV_STRG 0
#define CONFIG_IO_14_PD_SLW_RT 0
#define CONFIG_IO_14_PU_DRV_STRG 0
#define CONFIG_IO_14_PU_SLW_RT 0
#define CONFIG_IO_14_RTRIM 1
#define CONFIG_IO_14_WK_PU_EN 1
#define CONFIG_IO_15_INPUT_BUF_EN 0
#define CONFIG_IO_15_PD_DRV_STRG 0
#define CONFIG_IO_15_PD_SLW_RT 0
#define CONFIG_IO_15_PU_DRV_STRG 0
#define CONFIG_IO_15_PU_SLW_RT 0
#define CONFIG_IO_15_RTRIM 1
#define CONFIG_IO_15_WK_PU_EN 1
#define CONFIG_IO_16_INPUT_BUF_EN 0
#define CONFIG_IO_16_PD_DRV_STRG 10
#define CONFIG_IO_16_PD_SLW_RT 1
#define CONFIG_IO_16_PU_DRV_STRG 8
#define CONFIG_IO_16_PU_SLW_RT 1
#define CONFIG_IO_16_RTRIM 1
#define CONFIG_IO_16_WK_PU_EN 0
#define CONFIG_IO_17_INPUT_BUF_EN 1
#define CONFIG_IO_17_PD_DRV_STRG 10
#define CONFIG_IO_17_PD_SLW_RT 1
#define CONFIG_IO_17_PU_DRV_STRG 8
#define CONFIG_IO_17_PU_SLW_RT 1
#define CONFIG_IO_17_RTRIM 1
#define CONFIG_IO_17_WK_PU_EN 0
#define CONFIG_IO_1_INPUT_BUF_EN 1
#define CONFIG_IO_1_PD_DRV_STRG 10
#define CONFIG_IO_1_PD_SLW_RT 0
#define CONFIG_IO_1_PU_DRV_STRG 8
#define CONFIG_IO_1_PU_SLW_RT 0
#define CONFIG_IO_1_RTRIM 1
#define CONFIG_IO_1_WK_PU_EN 1
#define CONFIG_IO_2_INPUT_BUF_EN 1
#define CONFIG_IO_2_PD_DRV_STRG 10
#define CONFIG_IO_2_PD_SLW_RT 0
#define CONFIG_IO_2_PU_DRV_STRG 8
#define CONFIG_IO_2_PU_SLW_RT 0
#define CONFIG_IO_2_RTRIM 1
#define CONFIG_IO_2_WK_PU_EN 1
#define CONFIG_IO_3_INPUT_BUF_EN 1
#define CONFIG_IO_3_PD_DRV_STRG 10
#define CONFIG_IO_3_PD_SLW_RT 0
#define CONFIG_IO_3_PU_DRV_STRG 8
#define CONFIG_IO_3_PU_SLW_RT 0
#define CONFIG_IO_3_RTRIM 1
#define CONFIG_IO_3_WK_PU_EN 1
#define CONFIG_IO_4_INPUT_BUF_EN 1
#define CONFIG_IO_4_PD_DRV_STRG 10
#define CONFIG_IO_4_PD_SLW_RT 1
#define CONFIG_IO_4_PU_DRV_STRG 8
#define CONFIG_IO_4_PU_SLW_RT 1
#define CONFIG_IO_4_RTRIM 1
#define CONFIG_IO_4_WK_PU_EN 0
#define CONFIG_IO_5_INPUT_BUF_EN 1
#define CONFIG_IO_5_PD_DRV_STRG 10
#define CONFIG_IO_5_PD_SLW_RT 1
#define CONFIG_IO_5_PU_DRV_STRG 8
#define CONFIG_IO_5_PU_SLW_RT 1
#define CONFIG_IO_5_RTRIM 1
#define CONFIG_IO_5_WK_PU_EN 0
#define CONFIG_IO_6_INPUT_BUF_EN 0
#define CONFIG_IO_6_PD_DRV_STRG 10
#define CONFIG_IO_6_PD_SLW_RT 1
#define CONFIG_IO_6_PU_DRV_STRG 8
#define CONFIG_IO_6_PU_SLW_RT 1
#define CONFIG_IO_6_RTRIM 1
#define CONFIG_IO_6_WK_PU_EN 0
#define CONFIG_IO_7_INPUT_BUF_EN 1
#define CONFIG_IO_7_PD_DRV_STRG 10
#define CONFIG_IO_7_PD_SLW_RT 1
#define CONFIG_IO_7_PU_DRV_STRG 8
#define CONFIG_IO_7_PU_SLW_RT 1
#define CONFIG_IO_7_RTRIM 1
#define CONFIG_IO_7_WK_PU_EN 0
#define CONFIG_IO_8_INPUT_BUF_EN 1
#define CONFIG_IO_8_PD_DRV_STRG 10
#define CONFIG_IO_8_PD_SLW_RT 1
#define CONFIG_IO_8_PU_DRV_STRG 8
#define CONFIG_IO_8_PU_SLW_RT 1
#define CONFIG_IO_8_RTRIM 1
#define CONFIG_IO_8_WK_PU_EN 0
#define CONFIG_IO_9_INPUT_BUF_EN 1
#define CONFIG_IO_9_PD_DRV_STRG 10
#define CONFIG_IO_9_PD_SLW_RT 1
#define CONFIG_IO_9_PU_DRV_STRG 8
#define CONFIG_IO_9_PU_SLW_RT 1
#define CONFIG_IO_9_RTRIM 1
#define CONFIG_IO_9_WK_PU_EN 0
#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
#define PINMUX_DEDICATED_IO_10_SEL 15
#define PINMUX_DEDICATED_IO_11_SEL 15
#define PINMUX_DEDICATED_IO_12_SEL 1
#define PINMUX_DEDICATED_IO_13_SEL 1
#define PINMUX_DEDICATED_IO_14_SEL 10
#define PINMUX_DEDICATED_IO_15_SEL 10
#define PINMUX_DEDICATED_IO_16_SEL 13
#define PINMUX_DEDICATED_IO_17_SEL 13
#define PINMUX_DEDICATED_IO_4_SEL 8
#define PINMUX_DEDICATED_IO_5_SEL 8
#define PINMUX_DEDICATED_IO_6_SEL 8
#define PINMUX_DEDICATED_IO_7_SEL 8
#define PINMUX_DEDICATED_IO_8_SEL 8
#define PINMUX_DEDICATED_IO_9_SEL 8
#define PINMUX_I2C0_USEFPGA_SEL 1
#define PINMUX_I2C1_USEFPGA_SEL 0
#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
#define PINMUX_I2CEMAC1_USEFPGA_SEL 0
#define PINMUX_I2CEMAC2_USEFPGA_SEL 0
#define PINMUX_NAND_USEFPGA_SEL 0
#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0
#define PINMUX_QSPI_USEFPGA_SEL 0
#define PINMUX_RGMII0_USEFPGA_SEL 0
#define PINMUX_RGMII1_USEFPGA_SEL 0
#define PINMUX_RGMII2_USEFPGA_SEL 0
#define PINMUX_SDMMC_USEFPGA_SEL 0
#define PINMUX_SHARED_IO_Q1_10_SEL 8
#define PINMUX_SHARED_IO_Q1_11_SEL 8
#define PINMUX_SHARED_IO_Q1_12_SEL 8
#define PINMUX_SHARED_IO_Q1_1_SEL 8
#define PINMUX_SHARED_IO_Q1_2_SEL 8
#define PINMUX_SHARED_IO_Q1_3_SEL 8
#define PINMUX_SHARED_IO_Q1_4_SEL 8
#define PINMUX_SHARED_IO_Q1_5_SEL 8
#define PINMUX_SHARED_IO_Q1_6_SEL 8
#define PINMUX_SHARED_IO_Q1_7_SEL 8
#define PINMUX_SHARED_IO_Q1_8_SEL 8
#define PINMUX_SHARED_IO_Q1_9_SEL 8
#define PINMUX_SHARED_IO_Q2_10_SEL 4
#define PINMUX_SHARED_IO_Q2_11_SEL 4
#define PINMUX_SHARED_IO_Q2_12_SEL 4
#define PINMUX_SHARED_IO_Q2_1_SEL 4
#define PINMUX_SHARED_IO_Q2_2_SEL 4
#define PINMUX_SHARED_IO_Q2_3_SEL 4
#define PINMUX_SHARED_IO_Q2_4_SEL 4
#define PINMUX_SHARED_IO_Q2_5_SEL 4
#define PINMUX_SHARED_IO_Q2_6_SEL 4
#define PINMUX_SHARED_IO_Q2_7_SEL 4
#define PINMUX_SHARED_IO_Q2_8_SEL 4
#define PINMUX_SHARED_IO_Q2_9_SEL 4
#define PINMUX_SHARED_IO_Q3_10_SEL 15
#define PINMUX_SHARED_IO_Q3_11_SEL 1
#define PINMUX_SHARED_IO_Q3_12_SEL 1
#define PINMUX_SHARED_IO_Q3_1_SEL 15
#define PINMUX_SHARED_IO_Q3_2_SEL 15
#define PINMUX_SHARED_IO_Q3_3_SEL 15
#define PINMUX_SHARED_IO_Q3_4_SEL 15
#define PINMUX_SHARED_IO_Q3_5_SEL 15
#define PINMUX_SHARED_IO_Q3_6_SEL 15
#define PINMUX_SHARED_IO_Q3_7_SEL 0
#define PINMUX_SHARED_IO_Q3_8_SEL 0
#define PINMUX_SHARED_IO_Q3_9_SEL 15
#define PINMUX_SHARED_IO_Q4_10_SEL 10
#define PINMUX_SHARED_IO_Q4_11_SEL 10
#define PINMUX_SHARED_IO_Q4_12_SEL 10
#define PINMUX_SHARED_IO_Q4_1_SEL 10
#define PINMUX_SHARED_IO_Q4_2_SEL 10
#define PINMUX_SHARED_IO_Q4_3_SEL 10
#define PINMUX_SHARED_IO_Q4_4_SEL 10
#define PINMUX_SHARED_IO_Q4_5_SEL 10
#define PINMUX_SHARED_IO_Q4_6_SEL 10
#define PINMUX_SHARED_IO_Q4_7_SEL 10
#define PINMUX_SHARED_IO_Q4_8_SEL 10
#define PINMUX_SHARED_IO_Q4_9_SEL 10
#define PINMUX_SPIM0_USEFPGA_SEL 0
#define PINMUX_SPIM1_USEFPGA_SEL 0
#define PINMUX_SPIS0_USEFPGA_SEL 0
#define PINMUX_SPIS1_USEFPGA_SEL 0
#define PINMUX_UART0_USEFPGA_SEL 1
#define PINMUX_UART1_USEFPGA_SEL 0
#define PINMUX_USB0_USEFPGA_SEL 0
#define PINMUX_USB1_USEFPGA_SEL 0
/* Bridge Configuration */
#define F2H_AXI_SLAVE 1
#define F2SDRAM0_AXI_SLAVE 1
#define F2SDRAM1_AXI_SLAVE 1
#define F2SDRAM2_AXI_SLAVE 1
#define H2F_AXI_MASTER 1
#define LWH2F_AXI_MASTER 1
/* Voltage Select for Config IO */
#define CONFIG_IO_BANK_VSEL \
(((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
(CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
/* Macro for Config IO bit mapping */
#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
((NAME ## _WK_PU_EN & 0x1) << 16) | \
((NAME ## _PU_SLW_RT & 0x1) << 13) | \
((NAME ## _PU_DRV_STRG & 0xf) << 8) | \
((NAME ## _PD_SLW_RT & 0x1) << 5) | \
(NAME ## _PD_DRV_STRG & 0x1f))
#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */

54
arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi Normal file
View File

@@ -0,0 +1,54 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
#include "socfpga_arria10-u-boot.dtsi"
/ {
chosen {
firmware-loader = <&fs_loader0>;
};
fs_loader0: fs-loader {
u-boot,dm-pre-reloc;
compatible = "u-boot,fs-loader";
phandlepart = <&mmc 1>;
};
};
&atsha204a {
u-boot,dm-pre-reloc;
};
&fpga_mgr {
u-boot,dm-pre-reloc;
altr,bitstream = "fpga.itb";
};
&i2c1 {
u-boot,dm-pre-reloc;
};
&main_sdmmc_clk {
u-boot,dm-pre-reloc;
};
&mmc {
u-boot,dm-pre-reloc;
};
&peri_sdmmc_clk {
u-boot,dm-pre-reloc;
};
&sdmmc_clk {
u-boot,dm-pre-reloc;
};
&sdmmc_free_clk {
u-boot,dm-pre-reloc;
};
&uart1 {
u-boot,dm-pre-reloc;
};

72
arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi Normal file
View File

@@ -0,0 +1,72 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
#include "socfpga_arria10.dtsi"
/ {
aliases {
ethernet0 = &gmac0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial1:115200n8";
};
memory@0 {
name = "memory";
device_type = "memory";
reg = <0x0 0x80000000>; /* 2GB */
};
};
&gmac0 {
phy-mode = "rgmii";
phy-handle = <&phy3>;
max-frame-size = <3800>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy3: ethernet-phy@3 {
reg = <3>;
txd0-skew-ps = <0>; /* -420ps */
txd1-skew-ps = <0>; /* -420ps */
txd2-skew-ps = <0>; /* -420ps */
txd3-skew-ps = <0>; /* -420ps */
rxd0-skew-ps = <420>; /* 0ps */
rxd1-skew-ps = <420>; /* 0ps */
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
txc-skew-ps = <1860>; /* 960ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
};
};
};
&i2c1 {
atsha204a: atsha204a@64 {
compatible = "atmel,atsha204a";
reg = <0x64>;
};
isl12022: isl12022@6f {
compatible = "isil,isl12022";
reg = <0x6f>;
};
};
&mmc {
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
};
&osc1 {
clock-frequency = <33330000>;
};

7
arch/arm/mach-socfpga/Kconfig
View File

@@ -143,6 +143,10 @@ config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
config TARGET_SOCFPGA_CHAMELEONV3
bool "Google Chameleon v3 (Arria 10)"
select TARGET_SOCFPGA_ARRIA10
config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -198,6 +202,7 @@ config SYS_BOARD
default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -224,6 +229,7 @@ config SYS_VENDOR
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "google" if TARGET_SOCFPGA_CHAMELEONV3
default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -240,6 +246,7 @@ config SYS_CONFIG_NAME
default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO

31
arch/arm/mach-socfpga/clock_manager_arria10.c
View File

@@ -15,6 +15,10 @@
#ifdef CONFIG_SPL_BUILD
void sdelay(unsigned long loops);
u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
u32 bound);
static u32 eosc1_hz;
static u32 cb_intosc_hz;
static u32 f2s_free_hz;
@@ -551,13 +555,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
mdelay(1);
sdelay(1000000); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
main_cfg->vco1_numer,
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
mdelay(1);
sdelay(1000000); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
@@ -585,16 +589,25 @@ static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg,
clk_hz),
socfpga_get_clkmgr_addr() +
CLKMGR_A10_PERPLL_VCO1);
mdelay(1);
sdelay(1000000); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
per_cfg->vco1_numer,
socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
mdelay(1);
sdelay(1000000); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
/* function to poll in the fsm busy bit */
static int cm_busy_wait_for_fsm(void)
{
void *reg = (void *)(socfpga_get_clkmgr_addr() + CLKMGR_STAT);
/* 20s timeout */
return wait_on_value(CLKMGR_STAT_BUSY, 0, reg, 100000000);
}
/*
* Setup clocks while making no assumptions of the
* previous state of the clocks.
@@ -727,7 +740,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
/* Wait for at least 5 us */
udelay(5);
sdelay(5000);
/* Now deassert BGPWRDN and PWRDN */
clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
@@ -738,7 +751,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
/* Wait for at least 7 us */
udelay(7);
sdelay(7000);
/* enable the VCO and disable the external regulator to PLL */
writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) &
@@ -878,19 +891,19 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
writel(CLKMGR_MAINPLL_BYPASS_RESET,
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSR);
/* wait till Clock Manager is not busy */
cm_wait_for_fsm();
cm_busy_wait_for_fsm();
/* release perpll from bypass */
writel(CLKMGR_PERPLL_BYPASS_RESET,
socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSR);
/* wait till Clock Manager is not busy */
cm_wait_for_fsm();
cm_busy_wait_for_fsm();
/* clear boot mode */
clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL,
CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
/* wait till Clock Manager is not busy */
cm_wait_for_fsm();
cm_busy_wait_for_fsm();
/* At here, we need to ramp to final value if needed */
if (pll_ramp_main_hz != 0)

26
arch/arm/mach-socfpga/misc_arria10.c
View File

@@ -246,3 +246,29 @@ int qspi_flash_software_reset(void)
return 0;
}
#endif
void dram_bank_mmu_setup(int bank)
{
struct bd_info *bd = gd->bd;
u32 start, size;
int i;
/* If we're still in OCRAM, don't set the XN bit on it */
if (!(gd->flags & GD_FLG_RELOC)) {
set_section_dcache(
CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
DCACHE_WRITETHROUGH);
}
/*
* The default implementation of this function allows the DRAM dcache
* to be enabled only after relocation. However, to speed up ECC
* initialization, we want to be able to enable DRAM dcache before
* relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram
* is set first).
*/
start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
for (i = start; i < start + size; i++)
set_section_dcache(i, DCACHE_DEFAULT_OPTION);
}