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ppc4xx: Fixed offset of refresh rate type for Bamboo on-board DDR SDRAM

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This patch also adds a note to the fixed DDR setup for Bamboo NAND booting:

Note:
As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
modules are still plugged in. So it is recommended to remove the DIMM
modules while using the NAND booting code with the fixed SDRAM setup!

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Eugene O'Brien
2007-10-23 08:29:10 +02:00
committed by Stefan Roese
parent afe9fa59cb
commit 9f798766aa
2 changed files with 8 additions and 2 deletions
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4
board/amcc/bamboo/bamboo.c
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@@ -67,13 +67,13 @@ const unsigned char cfg_simulate_spd_eeprom[128] = {
0x00, /* Module data width continued: +0 */
0x04, /* 2.5 Volt */
0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
0x00, /* SDRAM Access from clock */
#ifdef CONFIG_DDR_ECC
0x02, /* ECC ON : 02 OFF : 00 */
#else
0x00, /* ECC ON : 02 OFF : 00 */
#endif
0x82, /* refresh Rate Type: Normal (15.625us) + Self refresh */
0,
0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
0,
0,
0x01, /* wcsbc = 1 */