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Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD
2013-08-17 18:24:13 +02:00
parent 425faf74cd 326ea986ac
commit 9ed887caec
28 changed files with 603 additions and 1968 deletions
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8
arch/arm/cpu/armv7/mx6/clock.c
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@@ -452,6 +452,14 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
void enable_ipu_clock(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
int reg;
reg = readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
writel(reg, &mxc_ccm->CCGR3);
}
/***************************************************/
U_BOOT_CMD(

43
arch/arm/cpu/armv7/mx6/soc.c
View File

@@ -16,6 +16,8 @@
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <stdbool.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
struct scu_regs {
u32 ctrl;
@@ -212,3 +214,44 @@ const struct boot_mode soc_boot_modes[] = {
void s_init(void)
{
}
#ifdef CONFIG_IMX_HDMI
void imx_enable_hdmi_phy(void)
{
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
u8 reg;
reg = readb(&hdmi->phy_conf0);
reg |= HDMI_PHY_CONF0_PDZ_MASK;
writeb(reg, &hdmi->phy_conf0);
udelay(3000);
reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
writeb(reg, &hdmi->phy_conf0);
udelay(3000);
reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
writeb(reg, &hdmi->phy_conf0);
writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
}
void imx_setup_hdmi(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
int reg;
/* Turn on HDMI PHY clock */
reg = readl(&mxc_ccm->CCGR2);
reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
writel(reg, &mxc_ccm->CCGR2);
writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
reg = readl(&mxc_ccm->chsccdr);
reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
reg |= (CHSCCDR_PODF_DIVIDE_BY_3
<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
|(CHSCCDR_IPU_PRE_CLK_540M_PFD
<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
}
#endif

3
arch/arm/imx-common/cmd_hdmidet.c
View File

@@ -11,8 +11,7 @@
static int do_hdmidet(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
u8 reg = readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
return (reg&HDMI_PHY_HPD) ? 0 : 1;
return (readb(&hdmi->phy_stat0) & HDMI_DVI_STAT) ? 0 : 1;
}
U_BOOT_CMD(hdmidet, 1, 1, do_hdmidet,

2
arch/arm/include/asm/arch-mx6/clock.h
View File

@@ -49,5 +49,5 @@ void enable_ocotp_clk(unsigned char enable);
void enable_usboh3_clk(unsigned char enable);
int enable_sata_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
void enable_ipu_clock(void);
#endif /* __ASM_ARCH_CLOCK_H */

8
arch/arm/include/asm/arch-mx6/mxc_hdmi.h
View File

@@ -9,6 +9,11 @@
#ifndef __MXC_HDMI_H__
#define __MXC_HDMI_H__
#ifdef CONFIG_IMX_HDMI
void imx_enable_hdmi_phy(void);
void imx_setup_hdmi(void);
#endif
/*
* Hdmi controller registers
*/
@@ -884,6 +889,9 @@ enum {
HDMI_PHY_HPD = 0x02,
HDMI_PHY_TX_PHY_LOCK = 0x01,
/* Convenience macro RX_SENSE | HPD */
HDMI_DVI_STAT = 0xF2,
/* PHY_I2CM_SLAVE_ADDR field values */
HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,