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rockchip: Add support for chromebook_bob

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Bob is a 10-inch chromebook produced by Asus. It has two USB 3.0 type-C
ports, 4GB of SDRAM, WiFi and a 1280x800 display. It uses its USB ports
for both power and external display. It includes a Chrome OS EC
(Cortex-M3) to provide access to the keyboard and battery functions.

Support so far includes only:
- UART
- SDRAM
- MMC, SD card
- Cros EC (but not keyboard)

Not included:
- Keyboard
- Display
- Sound
- USB
- TPM

Bob is quite similar to Kevin, the Samsung Chromebook Plus, but support
for this is not provided in this series.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Simon Glass 2019-01-21 14:53:36 -07:00 committed by Philipp Tomsich
parent 08c85b57a5
commit 9e92116bc8
10 changed files with 215 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/include/asm/arch-rockchip/sys_proto.h
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@ -29,4 +29,7 @@ static void configure_l2ctlr(void)
}
#endif /* CONFIG_ROCKCHIP_RK3288 */
/* provided to defeat compiler optimisation in board_init_f() */
void gru_dummy_function(int i);
#endif /* _ASM_ARCH_SYS_PROTO_H */

39
arch/arm/mach-rockchip/rk3399-board-spl.c
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@ -9,6 +9,7 @@
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <spl_gpio.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/bootrom.h>
@ -16,6 +17,7 @@
#include <asm/arch/grf_rk3399.h>
#include <asm/arch/hardware.h>
#include <asm/arch/periph.h>
#include <asm/arch/sys_proto.h>
#include <dm/pinctrl.h>
void board_return_to_bootrom(void)
@ -128,7 +130,13 @@ void secure_timer_init(void)
void board_debug_uart_init(void)
{
#define GRF_BASE 0xff770000
#define GPIO0_BASE 0xff720000
#define PMUGRF_BASE 0xff320000
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
#ifdef CONFIG_TARGET_CHROMEBOOK_BOB
struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
#endif
#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
/* Enable early UART0 on the RK3399 */
@ -139,6 +147,20 @@ void board_debug_uart_init(void)
GRF_GPIO2C1_SEL_MASK,
GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
#else
# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
rk_setreg(&grf->io_vsel, 1 << 0);
/*
* Let's enable these power rails here, we are already running the SPI
* Flash based code.
*/
spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
/* Enable early UART2 channel C on the RK3399 */
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C3_SEL_MASK,
@ -163,6 +185,22 @@ void board_init_f(ulong dummy)
#define EARLY_UART
#ifdef EARLY_UART
# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
int sum, i;
debug_uart_init();
/*
* Add a delay and ensure that the compiler does not optimise this out.
* This is needed since the power rails tail a while to turn on, and
* we get garbage serial output otherwise.
*/
sum = 0;
for (i = 0; i < 150000; i++)
sum += i;
gru_dummy_function(sum);
#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
/*
* Debug UART can be used from here if required:
*
@ -171,7 +209,6 @@ void board_init_f(ulong dummy)
* printhex8(0x1234);
* printascii("string");
*/
debug_uart_init();
printascii("U-Boot SPL board init\n");
#endif

10
arch/arm/mach-rockchip/rk3399/Kconfig
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@ -53,6 +53,15 @@ config TARGET_ROCK960_RK3399
* 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only),
1x USB 3.0 type C OTG
config TARGET_CHROMEBOOK_BOB
bool "Asus Flip C101PA Chromebook (RK3399)"
help
Bob is a small RK3299-based device similar in apperance to Minnie.
It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 10.1",
1280x800 display. It uses its USB ports for both power and external
display. It includes a Chrome OS EC (Cortex-M3) to provide access to
the keyboard and battery functions.
endchoice
config SYS_SOC
@ -64,5 +73,6 @@ config SYS_MALLOC_F_LEN
source "board/rockchip/evb_rk3399/Kconfig"
source "board/theobroma-systems/puma_rk3399/Kconfig"
source "board/vamrs/rock960_rk3399/Kconfig"
source "board/google/gru/Kconfig"
endif

15
board/google/gru/Kconfig Normal file
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@ -0,0 +1,15 @@
if TARGET_CHROMEBOOK_BOB
config SYS_BOARD
default "gru"
config SYS_VENDOR
default "google"
config SYS_CONFIG_NAME
default "gru"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

6
board/google/gru/MAINTAINERS Normal file
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@ -0,0 +1,6 @@
CHROMEBOOK BOB BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: board/google/gru/
F: include/configs/gru.h
F: configs/chromebook_bob_defconfig

5
board/google/gru/Makefile Normal file
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@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2019 Google LLC
obj-y += gru.o

16
board/google/gru/gru.c Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 Google
*/
#include <common.h>
int board_init(void)
{
return 0;
}
/* provided to defeat compiler optimisation in board_init_f() */
void gru_dummy_function(int i)
{
}

100
configs/chromebook_bob_defconfig Normal file
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@ -0,0 +1,100 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_TARGET_CHROMEBOOK_BOB=y
CONFIG_DEBUG_UART_BASE=0xff1a0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
CONFIG_LOG_DEFAULT_LEVEL=7
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_LOG=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_DM_KEYBOARD=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y

6
doc/README.rockchip
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@ -52,13 +52,14 @@ One RK3328 board is supported:
- EVB RK3328
Five RK3399 boards are supported (aarch64):
Size RK3399 boards are supported (aarch64):
- EBV RK3399 - use evb_rk3399 configuration
- Firefly RK3399 - use the firefly_rk3399 configuration
- Puma - use puma_rk3399 configuration
- Ficus - use ficus-rk3399 configuration
- Rock960 (Vamrs) - use rock960-rk3399 configuration
- Bob - use chromebook_bob configuration
Four RK3368 boards are supported:
@ -253,7 +254,8 @@ You should see something like:
Booting from SPI
================
To write an image that boots from SPI flash (e.g. for the Haier Chromebook):
To write an image that boots from SPI flash (e.g. for the Haier Chromebook or
Bob):
./chromebook_jerry/tools/mkimage -n rk3288 -T rkspi \
-d chromebook_jerry/spl/u-boot-spl-dtb.bin spl.bin && \

18
include/configs/gru.h Normal file
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@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015 Google, Inc
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define ROCKCHIP_DEVICE_SETTINGS \
"stdin=serial,cros-ec-keyb\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#include <configs/rk3399_common.h>
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif