i2c: zynq: Support for 0-length register address
Fixed bug with alen == 0 in 'i2c_write', 'i2c_read' Further minor corrections: - Write 'address' register before 'data' register. - Write 'transfer_size' register before 'address' register. Signed-off-by: Michael Burr <michael.burr@logicpd.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@ -189,12 +189,13 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
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* Temporarily disable restart (by clearing hold)
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* It doesn't seem to work.
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*/
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clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW |
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ZYNQ_I2C_CONTROL_HOLD);
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clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
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writel(0xFF, &zynq_i2c->interrupt_status);
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if (alen) {
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clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
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writel(dev, &zynq_i2c->address);
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while (alen--)
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writel(addr >> (8 * alen), &zynq_i2c->data);
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writel(dev, &zynq_i2c->address);
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/* Wait for the address to be sent */
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if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
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@ -203,6 +204,7 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
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return -ETIMEDOUT;
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}
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debug("Device acked address\n");
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}
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setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
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ZYNQ_I2C_CONTROL_RW);
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@ -247,17 +249,19 @@ static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
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ZYNQ_I2C_CONTROL_HOLD);
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clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
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writel(0xFF, &zynq_i2c->interrupt_status);
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writel(dev, &zynq_i2c->address);
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if (alen) {
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while (alen--)
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writel(addr >> (8 * alen), &zynq_i2c->data);
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/* Start the tranfer */
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writel(dev, &zynq_i2c->address);
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if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
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/* Release the bus */
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clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
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return -ETIMEDOUT;
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}
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debug("Device acked address\n");
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}
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while (length--) {
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writel(*(cur_data++), &zynq_i2c->data);
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if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
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